JPH04362810A - Logic signal delay circuit - Google Patents

Abstract

PURPOSE:To delay a leading time and a trailing time independently of each other for a delay circuit of a logic signal. CONSTITUTION:An output 01a of a logic circuit as a same logic signal is given to a buffer 1-1 with a short delay time and a buffer 2-1 with a long delay time and outputs 1a, 2a of the two buffers are given to a NAND gate 3-1 to allow an output 3a of the gate to rise in a short time and to fall down in a long time.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit for delaying signals of a general-purpose logic IC, and more particularly to a logic signal delay circuit that can independently set a rise delay time and a fall delay time of a signal. Note that in the following figures, the same reference numerals indicate the same or corresponding parts.

0002

2. Description of the Related Art FIG. 7 shows an example of the configuration of a conventional logic signal delay circuit. In the figure, 01 is a logic circuit that outputs H and L logic signals 01a, and is composed of a general-purpose logic IC or the like. 02
is a buffer that delays this input signal 01a and outputs it as signal 02a. FIG. 8 shows an example of the configuration of the buffer 02. That is, the buffer 02 consists of one or more inverters 03 connected in series. Since this is a fixed value for the rise time and fall time of each inverter 03, a desired delay time is obtained by selecting the number of inverters 03 connected in series.

0003

[Problems to be Solved by the Invention] However, in the conventional delay circuit described above, since the rise time and fall time of each buffer are fixed, the delay circuit as a whole The rise time and fall time of the input signal 01 are fixed, and in order to change the rise time and fall time independently, the buffer 02 needs to change the input signal 01.
It is necessary to change the threshold voltage as a voltage level for determining the logic of a, and as this threshold voltage changes, the margin for noise contained in the input voltage 01a increases. There was a problem in that the performance decreased (in other words, malfunctions were more likely to occur due to noise). Therefore, it is an object of the present invention to provide a logic signal delay circuit that can solve this problem.

0004

Means for Solving the Problems In order to solve the above problems, the delay circuit of the present invention has two buffer circuits (one
-1, 2-1, etc.) and a gate circuit (NA
ND gate 3-1, etc.). The threshold voltage of the delay circuit is 1 between the supply voltage and ground.
/2.

[0005]

[Operation] From two buffer circuits with different delay times whose threshold voltage is 1/2 of the power supply potential and ground potential, and a gate circuit that determines the AND or OR condition of the output signals of these two buffer circuits. Create a delay circuit.

[0006]

Embodiments An embodiment of the present invention will be described below with reference to FIGS. 1 to 6. FIG. 1 shows a circuit configuration as a first embodiment of the present invention. In FIG. 1, the output 01a of the logic circuit 01
is input to a buffer 1-1 with a short delay time and a buffer 2-1 with a long delay time, and outputs 1a and 2a of the buffers 1-1 and 2-1 are input to a NAND gate 3-1. Then, a signal 3a is output from the NAND gate 3-1. In this example, both buffers 1-1 and 2-1 have inverted outputs, but their internal configuration is the same as that in FIG. 8 and consists of an odd number of inverters 03. The operating threshold voltage is 1/2 of the power supply potential and the ground potential.

FIG. 2 is a time chart for explaining the operation of FIG. In FIG. 2, t11 and t12 are buffer 1, respectively.
Similarly, t21 and t21 are the rise and fall delay times of buffer 2-1, respectively, and t31 and t32 are the NAND
These are the rise delay time and fall delay time of the gate 3-1. Next, the operation of FIG. 1 will be explained with reference to FIG. 2. First, when the output signal 01a of the logic circuit 01 is "H", the outputs of the two buffers 1-1 and 2-1 are "L", and the outputs 1a and 2a of the two buffers 1-1 and 2-1 are N as input
The output 3a of the AND gate 3-1 is "H". Next, when the logic circuit output 01a becomes "L", at this falling time, the output 1a of the buffer 1-1, which has a short rise delay time t11, becomes "H", but the NAND gate 3-
The output 3a of No. 1 remains at "H". Then, the output 2a of the buffer 2-1, which has a long rise delay time t21, becomes “H”.
”, the output 3a of the NAND gate 3-1 becomes “L”. This time, when the logic circuit output 01a becomes “H” again, at this rising time, first the short falling delay time t
The output 1a of the buffer 1-1 having 12 becomes "L" and the output 3a of the NAND gate becomes "H". Therefore, NA
The ND gate output 3a has a long delay time t31 corresponding to the rise delay time t21 of the buffer 2-1 at the time of falling with respect to the logic circuit output 01a, and has a long delay time t31 corresponding to the rise delay time t21 of the buffer 2-1 at the time of the rise.
A short delay time t3 corresponding to the falling delay time t12 of 1
Has 2.

FIG. 3 shows the configuration of a circuit as a second embodiment of the present invention. In FIG. 3, the NAND gate 3-1 in FIG. 1 is replaced with an AND gate 3-2. In this case, the logic circuit output 01a and the output of the AND gate 3-2 have an inverted logic relationship, but the AND gate output 3a in this case rises slowly and falls quickly.

FIG. 4 shows a circuit configuration as a third embodiment of the present invention. This FIG. 4 shows the buffer 1-1 in FIG.
2-1 are respectively designated as output non-inverting type buffers 1-2 and 2-2. In this case as well, logic circuit output 01a and NA
It has an inverse relationship with the ND gate output 3a, but in this case N
The AND gate output 3a is fast when rising and slow when falling. Note that each of the buffers 1-2 and 2-2 consists of an even number of inverters 03 connected in series as shown in FIG.

FIG. 5 shows a circuit configuration as a fourth embodiment of the present invention. This FIG. 5 shows the buffer 1-1, buffer 1-1 in FIG.
2-1 are respectively non-inverted buffers 1-2 and 2-2,
Also, the NAND gate 3-1 in FIG. 1 is replaced by the AND gate 3-2.
That is. In this case, logic circuit outputs 01a and A
The ND gate output 3a has a non-inverting relationship, and the AND gate output 3a rises slowly and falls quickly.

FIG. 6 shows a circuit configuration as a fifth embodiment of the present invention. In FIG. 6, the NAND gate 3-1 in FIG. 1 is replaced with an OR gate 3-3. In this case, the logic circuit output 01a and the OR gate output 3a are in an inverted relationship, and the OR gate output 3a is fast when rising and slow when falling. Also, if the buffers 1-1 and 2-1 are non-inverting buffers 1-2 and 2-2, respectively, the logic circuit output 01a and the OR gate output will have a non-inverting relationship,
Similarly, the OR gate output rises quickly and falls slowly.

0012

According to the present invention, two buffer circuits that delay the same logic signal by different predetermined delay times, and a gate circuit that obtains an AND condition or an OR condition of the outputs of these two buffer circuits, are provided. Since the logic signal delay circuit is configured, the input threshold voltage of both buffers is 1/2 of the power supply voltage and ground, and the rise and fall of the logic output can be independently controlled while maintaining a large noise margin. It can be delayed.

[Brief explanation of drawings]

FIG. 1: A configuration diagram as a first embodiment of the present invention.

[Figure 2]
Time chart for explaining the operation in Figure 1

[Fig. 3] Configuration diagram as a second embodiment of the present invention

[Fig. 4] Configuration diagram as a third embodiment of the present invention

[Fig. 5] Configuration diagram as a fourth embodiment of the present invention

FIG. 6 is a configuration diagram as a fifth embodiment of the present invention.

[Figure 7] Configuration diagram of a conventional delay circuit

[Figure 8] Configuration diagram of the buffer in Figure 7

[Explanation of symbols]

01 Logic circuit 1-1, 1-2 Buffer with short delay time 2-1, 2
-2 Buffer with long delay time 3-1 NAND gate 3-2 AND gate 3-3 OR gate

Claims (3)

[Claims] Claim 1: A method comprising two delay circuits that delay the same logic signal by different predetermined delay times, and a gate circuit that obtains an AND condition or an OR condition of the outputs of the two delay circuits. Logic signal delay circuit. 2. The logic signal delay circuit according to claim 1, wherein the delay circuit is a buffer circuit. 3. The device according to claim 2, wherein the threshold voltage of the buffer circuit is 1 between the power supply voltage and ground.
A logic signal delay circuit characterized in that: /2.