JPS60204116A - Logic circuit - Google Patents

Abstract

PURPOSE:To obtain a complementary output without phase shift and using a differential circuit by constituting a circuit with inverters provided differently to the 1st branch circuit connecting a signal input terminal and the 1st signal output terminal and to the 2nd branch circuit connecting the input terminal and the 2nd signal output terminal. CONSTITUTION:The 2nd branch circuit 32 comprising the two inverters G2, G3 is provided between the signal input terminal 1 and the 2nd signal output terminal 22 of a logic circuit and the 1st branch circuit 32 comprising the inverter G1 is provided between the input terminal 1 and the 1st signal output terminal 21. An output CL' is retarded (tauD4) largely by the inverter G1 to the input signal CL1 of the circuit. The output of the inverter G2 and an output CL2 of the G3 are brought into small delays tauD5, tauD6 respectively. Then the relation of tauD4=tauD5+ tauD6 is designed, the phase of the outputs CL' and CL2 are formed into complementary outputs of opposite phase without any phase shift so as to eliminate the need for a differential circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a logic circuit that obtains complementary outputs, which is useful as, for example, an input circuit of a master-slave type frig 70.

[Technical background of the invention and its problems]

In semiconductor integrated circuits that require complementary inputs, it is common to obtain complementary signals as outputs of differential circuits. However, it is more convenient to obtain complementary signals using just one inverter. In this case, although the circuit becomes simpler, a phase shift occurs between the complementary signals due to the delay time of the inverter, resulting in a reduction in the operating speed of the entire circuit.

Figure 1 shows a T-type 7-rig float (T-FF) of the Master Throne type using the well-known NOR dart.

FIG. 2 shows its operating waveform, and it is known as a frequency divider circuit because it can obtain a frequency output of 2 of the input frequency.

This circuit requires complementary inputs of CL and CL.

Considering the case where there is no phase shift between CL and CL and a completely antiphase relationship, the outputs Q and Q are CL and CL as shown in Fig. 2.
It is output as a signal delayed by τI)I with respect to CL. This τD1 is the time it takes to pass through the transfer darts and FFs that make up the circuit.

FIG. 3 shows a circuit used to actually realize complementary inputs CL, CL for this T-FF.

In the figure, this is an inverter for obtaining an inverter of the opposite phase from INVf'iCL.

FIG. 4 shows operating waveforms of the circuit of FIG. 3. C
L is a complementary signal to CL, but in reality, if there is a delay time τD2 due to INV, τD1 + τD2
This will result in a delay.

In order for the T-FF to operate correctly as a frequency divider circuit, the outputs Q and Q must have completely changed by the time CL falls (indicated by the arrow in Figures 2 and 4). There is. In the case of Fig. 2, there is a marsine of τDis, but the fourth
In the case shown in the figure, the margin τ'D5 is smaller than τD3. Therefore, due to the phase shift between CL and CL, the operating frequency of the circuit is limited.

[Purpose of the invention]

In view of the above points, the present invention does not use a differential circuit.
It is an object of the present invention to provide a logic circuit that can obtain complementary outputs without any phase shift.

[Summary of the invention]

The circuit according to the present invention basically employs a method of obtaining an inverted signal using an inverter as explained in FIG. That is, a first branch circuit that connects the signal input terminal and the first signal output terminal, and a second branch circuit that connects the signal input terminal and the second signal output terminal are connected by an inverter having an odd number of stages. The basic idea is to have multiple configurations, and in this case, by combining inverters with different delay time characteristics, the delay time characteristics of the first and second branch circuits are matched.

〔Effect of the invention〕

According to the present invention, it is possible to realize a logic circuit that obtains complementary outputs without phase shift without using a differential circuit. If this logic circuit is used, for example, as an input circuit of a T-FF, it becomes possible to obtain a high operating frequency.

[Embodiments of the invention]

FIG. 5 shows a circuit of an embodiment of the present invention. This circuit is
For the input signal CLi to the signal input terminal 1, the first signal output terminal 2. An output signal CL having an opposite phase to this is obtained at the second signal output terminal 2! The output signal CL is in phase with the output signal CL.

Signal input end 1 and second signal output end 2! The second branch circuit 3° in between has two standard inverters G, , G3 connected in cascade, while the signal input terminal 1 and the first signal output terminal 2
．． The first branch circuit connecting 3. is composed of one inverter G. The inverter G1 is a delay inverter having a negative delay time characteristic equal to the total delay time of G and G3.

The operating waveforms of this circuit are shown in FIG. Delay inverter G! for input signal CL1! Output 1 is delayed by τD4. On the other hand, the output of inverter G and the output CL of G3 are each τD with a slight delay.
5+τ part.

Since it is designed so that τD4'' τD5+τD5, the positive 1 and CL become complementary outputs with completely opposite phases and no phase shift.

Figure 7 is a specific circuit of inverter G, %G, Schottky? -) structure is used. The load MESFET-Qn is of D type, and the driver MESFET-QE is of E type.

Figures 8(,) and (b) are schematic plan views of these inverters, with (a) showing the inverter G and G.
3.(b) is the inverter G. Inverter G shown in (a)! and G3 is the load MESFET-QD,
.

Driver MESFET -Q 1 Both are load MESFET -Q of inverter G1 shown in (b).
n2, Drino Shunkan 5FET-9g2 The dart length is short, so the dart capacity is small. For this reason (b
The input terminal G shown in ) has a longer delay time than the input terminals G and G3 shown in ( , ), and serves as a delay input terminal.

In this way, the logic circuit according to this embodiment can obtain complementary outputs without phase shift with a simple circuit configuration. If this is used, for example, as an input circuit for a T-FF, its operating frequency can be made sufficiently high. Furthermore, if such input circuits are integrated as an IC, there is no need to provide an external delay circuit, and various logic circuits can be made smaller.

High reliability can be achieved.

The present invention can be implemented in various modifications.

Some other embodiments are shown in FIGS. 9-12. 9th
The figure shows each branch circuit 3. , 3t have the same delay time as the node GB.

GB is added. These nine fine gears GB, GB, are necessary to obtain high driving performance.

Another role of the in-house engineers of these CBs, GBs, and CBs is waveform shaping. Especially delay inverter G,
Since both the rising and falling characteristics of the output waveform of G3 are deteriorated, the rising and falling characteristics can be improved with GB1.

FIG. 10 shows the circuit of FIG. 5 with an inverter G4 added to the signal input terminal. Since this inverter G4 functions as a buffer and amplifier circuit, the input sensitivity increases. In FIG. 11, a delay inverter G3 is added to the first branch circuit 31 of the circuit shown in FIG. 5, and a normal inverter G6 is added to the second branch circuit 32. G
Delay time due to I + GII and G,,G.

By designing the outputs and G6 to be equal, it is possible to obtain completely complementary outputs.

In FIG. 12, contrary to FIG. 5, one inverter G with a normal delay time is provided in the first branch circuit 31, and the second branch circuit 3. Two delay input gates GL + GR are provided in the
Second branch circuit 3. This results in a very large delay. This also makes it possible to obtain completely complementary outputs.

The present invention can be further modified in various ways by combining the above embodiments.

[Brief explanation of drawings]

Figure 1 shows a master slavezo type T-FF, Figure 2
The figure shows its operating waveforms, Figure 3 shows a T-FF using an inverter as an input circuit, Figure 4 shows its operating waveforms, and Figure 5 shows the logic of an embodiment of the present invention. 6 is a diagram showing its operating waveforms, FIG. 7 is a diagram showing a specific circuit of an inverter used in this circuit, FIG. 8 is a schematic plan view thereof, and FIGS. 9 to 12 are diagrams of the present invention. FIG. 7 is a diagram showing a logic circuit of another embodiment. 1... Signal input end, 21... First signal output end, 2
, . . . second signal output terminal, 31 . . . first branch circuit,
3. Second branch circuit, 01-G, GB, GB. ...Inverter. Applicant's agent Patent attorney Suzu, Takeshi Jiang Syllable 1 Figure 2

Claims (2)

[Claims] (1) A first branch circuit in which one or more inverters are cascaded between a signal input terminal and a first signal output terminal, and between the signal input terminal and the second signal output terminal. and a second branch circuit in which one or more inverters are cascaded. The number of inverters in the second branch circuit is different from that of the first branch circuit by an odd number. A logic circuit which obtains a complementary output at a second signal output terminal, and which is particularly useful when inverters having different delay time characteristics are combined. A logic circuit characterized in that delay time characteristics in a second branch circuit are matched. (2) the first branch circuit is not composed of one inverter;
2. The logic circuit according to claim 1, wherein said second branch circuit comprises two innocouples having a smaller propagation delay than the inverter of the first branch circuit.