JPS61283094A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain an output buffer which is excellent in the propagating characteristic of a signal, highly speedy and has a high driving capacity by enlarging the driving capacity of a transistor connected serially to a memory device in accordance with the sequence of propagation of the signal. CONSTITUTION:At a memory device 11, tri-state inverters 12 and 16 and inverters 13 and 15 are connected, and the output of the memory device 11 is derivated through an inverter Inv 17 for buffering the output to the output edge of the integrated circuit. The inverter 12 is a small driving capacity and the inverter 15 is a middle-sized driving capacity and the Inv 17 is composed of the transistor with a large driving capacity. For such a reason, respective transistors may drive the transistor a little larger than themselves, and therefore, the propagating characteristic of the signal comes to be excellent, and the output buffer, which is highly speedy and has a high driving force, can be obtained.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to an integrated circuit device having a memory in an output stage, and in particular to an integrated circuit with improved characteristics of an output buffer provided in the integrated circuit device. It is related to the device.

<Summary of the Invention> The present invention provides an integrated circuit device having a memory in the output stage, in which the driving ability of transistors connected in series from the input side to the output side of the memory is adjusted according to the order in which signals propagate. It is configured to be large and serves as an output buffer.

<Prior Art> Generally, when a heavy output load is connected to the output end of an integrated circuit device, the heavy output load is connected to a minute transistor that constitutes the output stage of the integrated circuit device.
If this continues, a large delay will occur in signal propagation.

For this reason, conventionally, when a heavy output load is connected to a microtransistor, an output buffer is provided at the output stage of the integrated circuit device to ensure signal propagation.

<Problems to be solved by the invention> However, in the integrated circuit device having the above configuration,
The output buffer itself provided in the output stage also imposes a somewhat heavy output load on the tiny transistors, resulting in a large delay in signal output and causing waveforms to become dull.

The invention of wood was created with these points in mind.
It is an object of the present invention to provide an integrated circuit device that increases the driving capability of an output buffer and suppresses delays in propagated signals.

<Means for Solving the Problems> The present invention was created by focusing on the fact that in an integrated circuit device in which a memory is connected to the output stage, a plurality of transistors are connected in series in the signal propagation direction. This is what I did.

FIG. 1 is a block diagram showing the configuration of an output stage portion of an integrated circuit device according to the present invention.

In FIG. 1, 1 is a memory device ζ The memory device 1 is an electronic switch (transfer gate) 2 whose opening and closing are controlled by a clock signal φ that controls input and retention of signals, and a clock signal supplied via an inverter 3. an electronic switch (transfer gate) 4 whose opening and closing are controlled by φ;
The memory device 1 is composed of inverters 5 and 6, and is configured such that the output of the memory device 1 is led out to the output end of the integrated circuit device via an output buffer inverter 7.

Further, the inverter 5 is made up of a transistor with medium driving ability, and the inverter 7 is made up of a transistor with a large driving ability, thereby configuring the output buffer of the integrated circuit device of the present invention.

<Operation> The input signal is input to the inverter 5 via the electronic switch 2 in accordance with the clock signal φ, and is held within the closed μm range of the inverters 5, 6 and the electronic switch 4 by the clock signal φ.

In addition, the output of the memory device 1 is derived via the output buffer inverter 7, but in this case, the transistors constituting the inverters 5 and 7 connected in series from the input side to the output side are connected to the inverter. Since a transistor with a medium drive capacity is used for the inverter 5 and a transistor with a large drive capacity is used for the inverter 7, the transistors making up the inverter 5 have a drive capacity slightly larger than that of the inverter itself. It is only necessary to drive the transistors constituting 7, and the signal propagation characteristics are excellent.

<Embodiment> FIG. 2 is a block diagram showing the configuration of an output stage portion of an integrated circuit device as an embodiment of the present invention.

In FIG. 2, 11 is a memory, and the memory 11 is a three-state inverter 12.16 and an inverter 13.15.
The output of the memory 11 is led out to the output end of the integrated circuit device via an output buffer inverter 17.

Further, the three-state inverter 12 is configured with transistors with a small driving capacity, and the inverters 15 and 17H are configured with transistors with medium and large driving capacities, respectively, so that the output of the integrated circuit device as an embodiment of the present invention is It constitutes a buffer.

In the above configuration, the input signal is input to the inverter 14 by the clock signal φ via the triple-mode inverter 12ft.
and is maintained in a closed loop of three-state inverter 16 and inverter 15 by clock signal φ. Furthermore, the output of the memory 11 is derived via the output buffer inverter 17, but in this case, the transistors forming the inverters 12, 15 and 17 connected in series from the input side to the output side are , inverter 12
Since a transistor with a small driving ability is used for the inverter 12, a transistor with a medium driving ability is used for the inverter 15, and a transistor with a large driving ability is used for the inverter 17. Slightly large drive capacity (DJl <- only the transistors constituting the inverter 15 need to be driven, and the inverter 15
Since the transistors constituting the inverter 17 only need to drive the transistors constituting the inverter 17, which have a drive capacity slightly larger than that of the conventional inverter 17, the signal propagation characteristics are excellent.

FIG. 3 is a block diagram showing the configuration of an output stage portion of an integrated circuit device as another embodiment of the invention.

In Figure 3, M1 to MN are shown in Figure 1 or 2 above.
Memory devices 1 or 11 connected in series with each other as shown in the figure
Inv is an inverter for output buffering, and the input and holding of signals in each of the memories M1 to MN is controlled by the signal φ and its opposite phase signal φ, and each memory M1 to MN connected in series
Adjacent memory devices 1 to MN are configured to be controlled by signals having opposite phases to each other.

The signal is outputted from the input terminal (in) to the input/output terminal (out), and each of the memories M1 to MN is arranged such that the driving capacity increases in sequence from the input end memory M1 to the output end memory MN. The inverter Inv is configured to have the maximum driving capacity.

With the above configuration, each memory device only needs to transmit a signal to a memory device with a slightly larger drive capacity than itself, and as a result, the final stage is an inverter Inv with sufficient drive capacity.
It becomes possible to set it in '.

As described above, according to the present invention, each transistor connected in series from the input side to the high-power side only needs to drive a transistor that is slightly larger than itself, which reduces signal propagation. It becomes possible to provide a transistor with excellent characteristics and sufficient driving ability in the final stage, and thereby it becomes possible to provide an output buffer section with high speed and high driving ability in an integrated circuit device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an output stage portion of an integrated circuit device of the present invention, FIG. 2 is a block diagram showing a configuration of an output stage portion of an integrated circuit device as an embodiment of the present invention, and FIG. FIG. 2 is a block diagram showing the configuration of an output stage portion of an integrated circuit device as another embodiment of the present invention.

Claims (1)

[Claims] 1. In an integrated circuit device having a memory in the output stage, a plurality of transistor elements connected in series from the input side to the output side of the memory are driven in the order in which signals propagate. An integrated circuit device characterized by being configured to have a large capacity. 2. The integrated circuit device according to claim 1, wherein a plurality of the memory devices are connected in series, and the driving capability increases according to the order in which signals are propagated.