JPH0260325A - Paralel serial converting circuit - Google Patents

Abstract

PURPOSE:To shorten the delay time of a circuit and to reduce the delay dispersion between an input and an output by making the switch size of first and second CMOS switches larger than the switch size used in a level shaped D/FF. CONSTITUTION:In first and second input terminals (a) and (b), when a control signal is an H level, a second CMOS switch 4 is turned on, and therefore, the input data of the terminal (b) are outputted to an output terminal (d) and latched to a level latch-shaped D/FF 1. Next, when a control signal is an L level, a first CMOS switch 3 is turned on, and therefore, the data latched to D/FF1 are outputted to the terminal (d). The parallel data inputted to terminals (a) and (b) are converted and outputted to the serial data. At this time, in order to shorten the time constant due to a load capacity 5 and the ON resistance of switches 3 and 4, the switch size is larger than CMOS switches 11 and 12, the ON resistance value is reduced and the delaying time of the circuit is shortened. Thus, the delaying dispersion between the input and the output can be reduced.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a parallel-to-serial conversion circuit used in a CMI-CODEC, etc., manufactured by Kotsu.
The present invention relates to a parallel-to-serial conversion circuit suitable for latching output using a (Dy flip-flop) or the like.

[Conventional technology]

Conventional parallel/7-real conversion circuit is 1 (for example, Honkawa) @
As described in the author "Introduction to Digital IC", published by Dempa Shimbunsha (March 1956), p. 126, it is composed of three stages of gates, and there is a delay of three stages of gates with respect to control signal C.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not take into account the delay time of the circuit, and if the average delay time of one gate is m and the delay variation is ±a%, then the delay time of the parallel-to-serial converter circuit is 3 m and Z 'J, the delay variation between input and output is ±3 × (χa × α/100), and when this output is latched by the next stage D/FF, there is a problem that it cannot be latched if the delay time is large. Ta.

SUMMARY OF THE INVENTION An object of the present invention is to provide a parallel-to-serial converter circuit that reduces the delay time of one circuit and reduces delay variations between input and output.

[Means to solve the problem]

The above purpose is to use a level trigger type (level latch type) that latches the input data of the first input terminal when the control signal is at "H" level between the first input terminal and the output terminal.
A first CMOS switch is connected in series with a first CMOS switch that is turned on when the control signal is at a high level, and a control signal is at a high level between the second input terminal and the output terminal. W, 2 CMOS turned on with
For example, the above level type 1)/F
The first and second C than the switch size used in F
The switch size of the MOS switch is increased, and the inverter used in the level trigger type DyFF and the above inverter are replaced with a BL-CMOS inverter.
This is achieved by a serial conversion circuit.

[Effect]

The above parallel-serial conversion circuit has a control signal @H“
When the second CMOS switch is turned on at level, the second input terminal υ input data is output to the output terminal, and at this time, the input data of the first input terminal is transferred to the level trigger type (c level latch type)D /FF, and the next time the control signal is at the 1L" level, the first CM
When the OS switch is turned on, the data latched in the level latch type D/FF is output to the output terminal, so the parallel data input to the first and second input terminals is converted to serial data at the output terminal. The data delay time with respect to the control signal at this time becomes the delay time of the first or second CMOS switch. Here, let us assume that the average delay time of one of the first or second CMOS switches is 4 (generally smaller than the delay time 1a of one conventional gate) and that the delay variation is ±4.

Since the delay variation of the parallel-to-serial converter circuit configured with this CMOS switch is ~Xa/100,
Therefore, the delay variation can be reduced to 115 compared to the conventional parallel-to-serial conversion circuit configured with three stages of gates. Further, by increasing the switch size of the CMOS switch, the speed can be further increased, and by using the CMOS switch fBL-MOS, the speed can be further increased and delay variations can be further reduced.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 to 5.

FIG. 1 is a circuit diagram showing an embodiment of a parallel-to-serial conversion circuit according to the present invention. In FIG. 1, a and b are 1st. a second data input terminal; C is an input clock terminal;
1 is level latch (level) 17 g) BL-C”M
OS D/F1.2 dBL-CMOS inverter,
5.4 is the first. In the second CMOS switch, 5 is a load capacitor, and d is a data output terminal.

11.12 is CMOS switch, 15.14 is BL
- It is a CMOS inverter.

@10 in Figure 1 Level latch BL-CMO5 type D that latches the input data sound of the first input terminal a when the control signal of the input clock terminal C is "H" between the input terminal a and the output terminal d
/FF1, B-route CMOS inverter 2, and the first CMO that is turned on when the control signal of the input clock terminal C is "L".
A second CMOS switch 4? is connected in series with the S switch 3 and is turned on when the control signal of the input clock terminal C is "H" between the second input terminal and the output terminal d. Connected in parallel with the first CMOS switch 3, output terminal d
There is a load capacity 5 between and ground. It was. Level latch B
b-CMO5 type D/FF1 has first input terminal a and BL-
The C Af OS switch 11, which is turned on when the control signal of the input clock terminal C is -H-, and the BLCMOS inverter 15 are connected in series between the CMOS inverter 20, and
The C'MOS switch 1 is turned on when the clock input terminal 00 control signal is "°L" between the input and output terminals of the inverter 15.
2 and a series circuit of BL-CM OS input 14 in the opposite direction are connected in parallel.

Figure 2 shows that the control signal of the input tarlock terminal C in Figure @1 is “H”.
“Control signal 1H that turns on” ON-type CMOS switch 4
(-1: or 11) is a circuit diagram. In Figure 2,
41 is 0MO5, and a2 is an inverter. Figure 3 shows the control signal "L" ON type CMOS switch 3 (ZUTA 1
2) is a circuit diagram. In Figure 5, 61 is 0MO5
, 52 is an inverter.

FIG. 4 is a timing chart of FIG. 1.

In FIG. 4, the funeral 1. of FIG. *2 input terminals a, b
What is the data for ~An, B, ~B? When L is input in parallel, the control signal of input clock terminal C becomes “H”.
”, the data of the first input terminal 4, 41 to .4n
is latched by the level latch type D/FFt and outputted by the output ef of the inverter 2.

The data BI-Bn of the second input terminal is the second CMOS
The signal is output to the output terminal d for turning on the switch 4. Next, when the control signal of the input clock terminal C is "L", the first CMOS switch 2 is turned on, so that the control signal of the clock input terminal C is "H" and the data latched in the level latch type D/FF1 is first turned on. I, %A? L is output to the output terminal d.

In this way, the control signal of the input clock terminal C is “H”.
”, data B1 to Bn are output alternately, and when -L-, data 71 to .4% are output alternately, and data B, , A, ~BrL, An are serially output to output terminal d. .

As a result of the above, the delay time of the signal at the output terminal d with respect to the control signal at the input clock terminal C of this circuit is determined by the CMOS switch 6.
．． This results in a delay time of 4. here.

The CMOS switches 3 and 4 reduce the number of hours due to the load capacitance 5 and the on-resistance of the CMOS switches 3 and 4.
The switch size is made larger than that of the CMOS switches 11 and 12 used in the level latch type D/FF1 to lower the on-resistance value.

FIG. 5 is a circuit diagram showing another embodiment of the parallel-to-serial conversion circuit according to the present invention. In FIG. 5, the same symbols as in FIG. 1 indicate corresponding parts, and 6 is the level latch CMO.
5 type D/FF, 7 is CMOSMOS Imphal 15.
16 is a CMOS inverter.

This circuit uses level latch 0MO8 type D/FF6 and CMo5 imperme 7 using CMOS imperme 15.16.
It consists of the level latch BL-CMO5 in Figure 1.
Although the gear path consisting of the D/FF1 and the BL-0MO5 inverter 2 is designed to reduce power consumption, other aspects are the same as the circuit shown in FIG.

[Effects of the invention J] According to the present invention, the speed can be increased compared to the conventional method by reducing the number of stages, and by configuring with BL-0MO5, the speed can be increased and the delay variation can be lowered, and the switch size of the CMOS switch can be increased. CMI-CODEC for optical communication
It can be used for etc.

[Brief explanation of the drawing]

FIG. 1 is an example of a parallel-to-serial conversion circuit according to the present invention. The circuit diagram shown in FIG. 2 is the control signal -H- of FIG.
A circuit diagram of an on-type CMOS switch, FIG. 5 is a circuit diagram of an on-type CMOS switch with the control signal @L shown in FIG. 1, FIG. 4 is a timing chart of FIG. 1, and FIG. It is a circuit diagram showing another example of a conversion circuit. 1... Level latch (level trigger) BL-CMO5
Type D/FF. 2..., BLCMOS inverter, 5.4... 1st. Second CMOS switch. 6...Level latch CMO5 type D/FF. 7... CMOS inverter, α, b... 1st. Second input terminal. C...Input clock (control signal) terminal, d...Output terminal. Bi-CMOS inverter 3, + csos switch collection diagram

Claims (1)

[Claims] 1. The control signal is “H” between the first input terminal and the output terminal.
A level trigger type D/FF that latches the input data of the first input terminal at the level, an inverter, and a control signal that is “L”.
A first CMOS switch that is turned on when the control signal is at the "H" level is connected in series with the first CMOS switch that is turned on when the control signal is at the "H" level, and a second CMOS switch that is turned on when the control signal is at the "H" level is connected between the second input terminal and the output terminal. 2. The parallel-to-serial conversion circuit according to claim 1, wherein the switch size of the first and second CMOS switches is larger than the switch size used in the level trigger type D/FF. 3. The parallel-to-serial conversion circuit according to claim 1, wherein the inverter used in the level trigger type D/FF and the inverter are Bi-CMOS inverters. 4. A CMI-CODEC for optical communication. 2. The parallel-to-serial conversion circuit according to claim 1.