JP2821144B2 - Parallel-serial conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a parallel communication system used for an optical communication CMI-CODEC or the like.
The present invention relates to a serial conversion circuit, and more particularly to a parallel-serial conversion circuit suitable for latching an output by a D / FF (D flip-flop) at the next stage.

[Conventional technology]

A conventional parallel-to-serial conversion circuit is described in, for example, Jun Tsukawa, "Introduction to Digital ICs" published by Denpa Shimbun (March 1956).
As described on page 123, it is composed of three gates, and the control signal C is delayed by three gates.

[Problems to be solved by the invention]

The above prior art does not consider the delay time of the circuit. If the average delay time of one gate is ta and the delay variation is ± a%, the delay time of the parallel-serial conversion circuit is 3ta. The delay variation between outputs becomes ± 3 × (ta × a / 100), and this output is
There is a problem that latching cannot be performed if the delay time is long.

An object of the present invention is to provide a parallel-to-serial conversion circuit capable of reducing delay time of a circuit and reducing delay variation between input and output.

[Means for solving the problem]

An object of the present invention is to provide a level trigger type (level latch type) D / FF (D flip-flop) for latching input data of a first input terminal when a control signal is at "H" level between the first input terminal and an output terminal. ), An inverter and a first CMOS switch whose control signal is turned on at "L" level are connected in series, and a control signal is turned on at "H" level between a second input terminal and an output terminal. For example, the switch sizes of the first and second CMOS switches are made larger than the switch size used in the level type D / FF, and the switch size is used in the level trigger type D / FF. This is achieved by an inverter and a parallel-serial conversion circuit in which the inverter is a Bi-CMOS inverter.

[Action]

In the above parallel / serial conversion circuit, the control signal is “H”
When the second CMOS switch is turned on at the time of the level, the input data of the second input terminal is output to the output terminal, and at this time, the input data of the first input terminal is level-triggered (level latch type) D / FF, and the data latched in the level latch type D / FF is output to the output terminal by turning on the first CMOS switch when the control signal is at the "L" level. The parallel data input to the first and second input terminals are converted to serial data and output to the output terminal, and the data delay time for the control signal at this time is the first or second CMOS.
This is the switch delay time. Where the first or second
Assuming that the average delay time of one CMOS switch is t _d (generally, t _d is smaller than the delay time t _{a of} one conventional gate) and the delay variation is ± a%, the parallel switch constituted by the present CMOS switch is used. ± t _d × a /
Therefore, the delay variation is smaller than that of the conventional parallel-serial conversion circuit composed of three stages of gates.
Can be reduced to 1/3. In addition, by increasing the switch size of the CMOS switch, higher speed is achieved.
By using a Bi-MOS CMOS switch, the speed can be increased and the delay variation can be further reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a circuit diagram showing an embodiment of a parallel-serial conversion circuit according to the present invention. In FIG. 1, a and b are first and second data input terminals, c is an input clock terminal, 1
Is a level latch (level trigger) Bi-CMOS D / FF, 2 is
Bi-CMOS inverters, 3 and 4 are first and second CMOS switches,
5 is a load capacitance, and d is a data output terminal. 11,12 is CMO
S switches and 13 and 14 are Bi-CMOS inverters.

A level latch Bi-CMOS D / FF1 for latching the input data of the first input terminal a when the control signal of the input clock terminal c is "H" between the first input terminal a and the output terminal d of FIG.
, A Bi-CMOS inverter 2 and a first CMOS switch 3 that is turned on when the control signal of the input clock terminal c is “L”, and connected in series, and between the second input terminal b and the output terminal d. The second, which is turned on when the control signal of the input clock terminal c is "H"
CMOS switch 4 is connected in parallel with the first CMOS switch 3, and there is a load capacitance 5 between the output terminal d and the ground.
The level latch Bi-CMOS type D / FF1 has a CMOS switch 11 and a Bi-CMOS inverter 13 between the first input terminal a and the Bi-CMOS inverter 2 whose control signal of the input clock terminal c is turned on at "H". Are connected in series, and the inverter 13
The control signal of the clock input terminal c is “L” between the input / output terminals
And a series circuit of a Bi-CMOS inverter 14 in the reverse direction and a CMOS switch 12 which is turned on by a switch.

FIG. 2 is a circuit diagram of the control signal "H" on type CMOS switch 4 (or 11) which turns on when the control signal of the input clock terminal c of FIG. 1 is "H". In FIG. 2, 41 is a CMOS,
42 is an inverter. FIG. 3 shows a control signal "L" ON type in which the control signal of the input clock terminal c shown in FIG. 1 is turned "L".
It is a circuit diagram of CMOS switch 3 (or 12). In FIG. 3, 31 is a CMOS, and 32 is an inverter.

FIG. 4 is a timing chart of FIG. In FIG. 4, when data A _{1 to} A _n and B _{1 to} B _n are input in parallel to the first and second input terminals a and b of FIG. 1, the control signal of the input clock terminal c is changed. when the "H" level is latched by the first input terminal a of the data a ₁ to a _n level latch-type D / FF1 is outputted to the output e of the inverter 2, the data of the second input terminal b B ₁ ~ B _n is the second CMO switch 4
Are turned on to output terminal d. Next, when the control signal of the input clock terminal c is "L", the first
CMOS switch 2 is a control signal previously to the clock input terminal c for the on-the "H" level latch-type D / FF1 data A ₁ latched in to A _n are outputted to the output terminal d. In this way, the data B ₁ .about.B _n when the control signal is "H" of the input clock terminal c, "L" data A ₁ to A _n are output alternately each at the output terminal d the data _{B 1, a 1 ~B n,} a n are outputted serially.

As described above, the delay time of the signal at the output terminal d with respect to the control signal at the input clock terminal c of this circuit is equal to the CMOS switches 3 and 4.
Delay time. Here, the CMOS switches 3 and 4 use the CMO used for the level latch type D / FF1 in order to reduce the time constant due to the load capacitance 5 and the ON resistance of the CMOS switches 3 and 4.
The on-resistance value is reduced by making the switch size of the S switches 11 and 12 larger.

FIG. 5 is a circuit diagram showing another embodiment of the parallel-serial conversion circuit according to the present invention. In FIG. 5, the first
The same reference numerals as those in the figure indicate corresponding parts, and 6 is a level latch CMOS.
The D / FF and 7 are CMOS inverters, and 15 and 16 are CMOS inverters. This circuit is composed of level latch CMOS type D / FF6 using CMOS inverters 15 and 16 and CMOS inverter 7, and the level latch Bi-CMOS type D / FF1 and Bi-CMOS shown in FIG.
Although the power consumption of the circuit composed of the inverter 2 is reduced, the other components are the same as those of the circuit of FIG.

〔The invention's effect〕

According to the present invention, the speed can be increased as compared with the conventional one by reducing the number of stages, the speed can be increased and the delay variation can be reduced by using the Bi-CMOS, and the speed can be increased by increasing the switch size of the CMOS switch. For example, it is possible to increase the speed of the parallel-serial conversion circuit and reduce delay variations, and it can be used for a CMI-CODEC for optical communication.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of a parallel-serial conversion circuit according to the present invention, FIG. 2 is a circuit diagram of a control signal "H" ON type CMOS switch shown in FIG. 3 is a circuit diagram of the control signal "L" ON type CMOS switch of FIG. 1, FIG. 4 is a timing chart of FIG. 1, and FIG. 5 shows another embodiment of the parallel-serial conversion circuit according to the present invention. It is a circuit diagram. 1 ... Level latch (level trigger) Bi-CMOS D / FF, 2 ... Bi-CMOS inverter, 3, 4 ... first and second CMOS switches, 6 ... Level latch CMOS D / FF, 7 CMOS inverter, a, b ... first and second input terminals, c ... input clock (control signal) terminal, d ... output terminal.

Continued on the front page (72) Inventor Masaaki Matsumoto 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Koichi Shuto 1-6-1 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation In-house (56) References JP-A-61-283094 (JP, A) JP-A-61-228841 (JP, U) JP-B-62-47008 (JP, B2) (58) Fields investigated (Int. . ⁶ , DB name) H03M 9/00

Claims (1)

(57) [Claims] 1. A level trigger type D / FF for latching input data of a first input terminal when a control signal is at H level between a first input terminal and an output terminal, and an output of the level trigger type D / FF. And a first CMOS switch, which receives the output of the inverter as an input and turns on the control signal at L level, is connected in series, and the control signal is H between the second input terminal and the output terminal. Connecting a second CMOS switch that is turned on at a level, and operating with a larger delay time of a delay time of the first CMOS switch or a delay time of the second CMOS switch with respect to a control signal; A parallel-serial conversion circuit characterized by the following.