GB2356303A

GB2356303A - Switched current D/A converter with minimized current drain

Info

Publication number: GB2356303A
Application number: GB0027226A
Authority: GB
Inventors: Robert F Lay
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1999-11-12
Filing date: 2000-11-08
Publication date: 2001-05-16
Anticipated expiration: 2020-11-08
Also published as: GB0027226D0; GB2356303B; JP2001168716A

Abstract

A digital-to-analog converter includes a plurality of current sources I-8I adaptable to be turned on and off, coupled to associated switches S1-S8 that are switchable between associated shunt loads R1-R4 and a common current bus. A buffer stage inputs a summed current from the current bus and outputs an analog signal proportional to the summed current. Control signals corresponding to respective bits of the digital input signal are applied to the respective current sources I-8I so as to turn the current sources off and on. Other control signals, also corresponding to bits of the digital input signal, are applied to the switches SI-S8 so as to switch the switches at a predetermined time period after the associated current sources are turned on.

Description

2356303 SWITCHED CURRENT D/A CONVERTER WITH MINIMIZED CURRENT DRAIN

FIELD OF THE INVENTION

This invention relates generally to data conversion and more specifically to 5 digital-to-analog- (D/A) converters.

BACKGROUND OF THE INVENTION

There are a variety of known Digital-to-Analog (D/A) converters which convert a si-nal in di-ital form to analog form. One particular type of D/A converter is a current D/A converter which utilizes current sources controlled by a digital input signal value. The current sources are summed and subsequently converted into an analog equivalent. Current D/A converters utilize resistors to translate a summed current provided by the current sources into a voltage.

Each current source can be implemented to provide a predetermined value of current. In one form, each current source provides a different amount of current, each value being a binary two multiple. Such converters are cominonly said to be binary weighted. In another form, each current source may be implemented to provide the same amount of current, wherein the D/A converter is called a monotonic converter. Monotonic converters require more current sources than binary weighted converters to implement the same amount of resolution. Typically, for higher resolution requirements, a monotonic converter has 2 N equal valued current sources as opposed to only N current sources for the binary weighted converter.

FIG. I is an example of a prior art 4-bit binary weighted D/A converter of the type typically used in portable radio communication devices, for example. This type -I- of high speed switched current D/A converter is becoming increasingly prevalent in portable communication systems, as well as systems of other types. In order to ide high speed switching, this switched current converter operates on the principle provi I I I Zn of switchino, a current either to a shunt load, when the current from the current source is not required, or to a buffered load that generates a desired analog output voltage.

While this configuration produces high speeds, it is wasteful of current through the shunt load, which is undesirable in battery powered devices such as portable communication devices, for example.

Accordingly, there is a need for a high speed D/A converter that rruininlizes current drain while providing stable performance. It is also desirable to provide an improved D/A converter that can be implemented with minimal addition cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. I shows a simplified schematic diagram of a prior art D/A converter;

C FIG. 2 shows a simplified schematic diagram of an improved D/A converter, in C accordance with a preferred embodiment of the present invention; and FIG. 3 shows a timing diagram of the operation of the D/A converter of FIG. 2.

Z DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention provides an improved D/A converter that minimizes current drain while providing stable performance. This is accomplished through relatively simple additional logic controlled circuitry that is implemented with minimal addition cost. As a result the present invention provides a low current drain, high speed D/A converter suitable for use in personal communication devices, and other digital devices requiring a high speed D/A converter.

L- I I Z: C While the specification concludes with claims defining the features of the invention that are regarded as novel, it is believed that the invention will be better understood from a consideration of the following description in conjunction with the drawing figures, in which like reference numerals are carried forward. A Zn -_ radiotelephone is a device that communicates information using electromagnetic waves in the radio frequency range, as is known in the art. The radiotelephone portion of the portable communication device is preferably a cellular radiotelephone adapted for personal communication or personal computing, but may also be a cordless radiotelephone or a personal communication service (PCS) radiotelephone. The radiotelephone portion may be constructed in accordance with a digital communication standard. The radiotelephone portion generally includes a radio frequency (RF) transceiver, a controller, an antenna, batteries, an RF front end, a signal processor, and a D/A converter. The electronics incorporated into a radiotelephone, or for that matter, a portable cellular phone, two-way radio or selective radio receiver, such as a pager, are well known in the art, and may be incorporated into the present invention.

Illustrated in FIG. I is an example of a prior art switched current digital to analog (D/A) converter. The example shown is a 4-bit binary weighted D/A converter wherein each current source (1, 21, 31, 41) provides twice the current of a preceding current source. The current sources are always on during operation. The switched current converter operates on the principle of switching a current from each current source either to a shunt load (RI, R2, R3, R4), when the current source is not required, or sununed with other currents and applied to a buffered load that generates a desired analog output voltage.

A control lo-ic block has a di-ital data input for receiving N bits of a digital input signal, where N is an integer. The N bits represent bits of a digital input signal which is desired to be converted to a corresponding analog value. Various implementations of the control logic block are known in the art. The control loic block appl les control signals to control switches (S 1, S2, S3, S4) that are coupled to each associated current source (1, 21, 31, 41). In this case N=4, and the N bits control N current sources, with each current source providing a current of 1, 21, 41, and 81, 5 respectively.

An input of each of current sources is connected to a power supply terminal for receiving a power supply. An output of each current source is connected to each associated switch adapted to respond to the control signals. The switch can alternately be connected to either an associated shunt load or a common current bus. The common current bus is then coupled to a buffer stage.

The buffer staae, as is known in the art, includes an operational amplifier havina a first or ne-ative input connected through an input resistor to the common cur-rent bus. A second or positive input of operational amplifier is connected to an analoc, reference voltage terminal, preferably a ground. An output of operational amplifier provides an analog output voltage. A feedback resistor has a first terminal connected to the negative input of operational amplifier and a second terminal connected to the output of operational amplifier. A voltage gain of the buffer stage is controlled by the resistor values.

In operation, the digital to analog converter converts an input digital signal havin- a total of N bits into a corresponding range of)N analog current values. The D/A converter always draws a total current of 151, since all the current sources are on and are being drained through either its shunt load or the buffer stage. A logical high C Z:

for any one of the N bits switches the associated switch to connect the respective current source to the common bus. For purposes of facilitating an understanding of 2) 5 D/A converter, a looical hi-h for control sionals S2 and S4, with S I and S3 being louical low, will couple a total current of 101 (21 + 81) to the buffer stage through the common bus. In the buffer stage, this current is converted to an analo output voltage 9 of IOIRA(RB/RA)- FIG. 2 illustrates a preferred embodiment of an improved D/A converter of the present invention which incorporate all of the functionality of the above described prior art D/A converter with the exceptions described below. Again, four current sources are shown, but it should be recognized that a larger number of current stages can be used without departing from the scope of the present invention. D/A converters commonly use eight, twelve, sixteen or more bits of conversion. In addition, it should be recognized that the present invention also works equally well with a monotonic linear D/A converter where each of 2Ncurrents sources provide substantially equal currents and are control by 2 N switch control signals and 2 N current source control si-nals, and a nonlinear D/A converter where the current sources are different in value. In the illustrated form, the D/A converter has four (N) binaryweichted currents controlled by a digital input signal of four (N) bits. In other words, t:1 Zn L- the number of current sources and switches that are implemented are determined by the number of bits of the digital input signal to be converted. This provides the same resolution of monotonic converters with much less circuitry.

In contrast to the prior art, the current sources of the present invention no longer provide constant current but are adapted to be switched on and off by current source control signals (S 1', S2', S3', S4') that are derived from the switch control signals (S 1, S2, S3, S4). The current source control signals are provided by the control logic block in response to the digital input signals. Each of the switch control si-nals are identical to the respective current source control signals but is delayed by a predetermined time period.

Refeming to FIG. 3, a graph is shown wherein a digital input signal (which Z Cl would be equivalent to the current source control signals S I'-S4') is cycled from I I I I to 0000 (shown starting at 0000). The lower portion of FIG. 3 shows the timing of the Z-- current source control signals (Sl'-S4') in relation to the switch control signals (S I - S4) for the first three cycles of dialtal input (0000, 1111, 1110). Only S V and S2' are shown as all the current source control signals precede their associated switch control signals by a similar predeterrruined time delay, A. In other words, the switch control signals are delayed from the current source control signals by the predetermined time delay, A. When the digital input indicates that S I go high, for example, the current source control signal, S 1', is immediately set high, and the switch control signal, S 1, is only set high after the predeterrruined time delay, A.

In operation, (referring back to FIG. 2), when current source control signal S I' goes high the current source, 1, is turned on. After the predetermined time delay, A, signal S 1 goes high switching the switch S I from the shunt load, R 1, to the common L- 4-- In current bus. In effect, the current source is allowed to turn on and settle to a constant current before the switch connects the current to the buffer stage. The predetermined time delay, A, is determined by the start up time required by the current sources, and can be in the nanosecond ranae. The delay is small enough such that no adverse effects are produced in subsequent processing of the output signal. As a result, the tn present invention provides the same output linearity available in the prior art while reducing current drain substantially since the current sources are not on all the time. Moreover, in application such as digital audio, the largest current sources, such as 81 for example, would rarely be turned on since audio volumes this high do not occur very often. This reduces current drain further over the prior art.

In a preferred embodiment (and referencing, FIG. 3), it is not necessary that the current source be turned off before the associated switch reverts back to its shunt load. Therefore, the correspondinc, currents source and switch control signals, S I and S I' for example, can be turned off simultaneously. Also, as the buffer stage converts the summed current from the current sources into a voltace, the buffer stage can provide a voltage gain to supply an analog output within a predetermined output voltage range. This accomplished by making one or both of the input and feedback resistors variable, or by changing the gain of the amplifier itself. This can also be controlled by the control logic block.

Thus it is apparent that there has been provided, in accordance with the present invention, a di gi tal-to- analog converter that fully meets the needs and advantages set forth previously. Although the invention has been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to these illustrative embodiments. For example, the buffer stage is optional and not required. If no buffer stage is used, an output voltage can be directly developed from the common bus which may be used as the equivalent analog output signal.

Further, other types of output stages may be used in addition to the circuit configuration using an operational amplifier. Any type of semiconductor device which functions as a switching element may be used for the switches illustrated herein. Also, it should be well understood that the D/A converter can be implemented in a variety of semiconductor technology, including metal oxide semiconductor (MOS), bipolar, BiMOS, gallium arsenide, and others. Those skilled in the art will recognize that modifications and variations can be made without departing from the scope of the invention. Therefore, it is intended that this invention encompass all such variations and modifications as fall within the scope of the appended claims.

Claims

What is claimed is:

I - A radio communication device incorporating, an antenna, an RF front end, a Z-- radio frequency (RF) transceiver, a signal processor, a controller, and a digital-to- Z-1 analoc, converter for converting a digital input signal to an analog output signal, the daltal-to-analog converter comprising:

:n a plurality of current sources adaptable to be turned on and off, the current sources coupled to associated switches that are switchable between associated shunt loads and a common current bus; a first plurality of control signals corresponding to respective bits of the digital input signal, the first plurality of control signals applied to the respective current sources so as to turn the current sources off and on; and a second plurality of control signals also corresponding to bits of the digital input signal, the second plurality of control signals applied to the switches associated with the respective current sources so as to switch the switches between their associated shunt loads and the common current bus, the second plurality of control signals operate the switches at a predetermined time period after the first plurality of control signals operate the associated current sources.

I
2. The radio communication device converter of claim 1, wherein the second plurality of control signals operate to connect the switches to the common current bus at a predeterrruined time period after the first plurality of control signals operate to turn on the associated current sources so as to give the current sources time to settle. 5
3. The radio communication device converter of claim 2, wherein the second plurality of control signals operate to disconnect the switches from the common current bus at substantially the same time as the first plurality of control signals operate to turn off the associated current sources.
4. The radio communication device converter of claim 1, wherein the curTent sources provides currents that have a binary weighted relationship.
5. The radio communication device of claim 1, further comprising a zD buffer staoe that inputs a summed current from the current bus and outputs the analog 4-- Z:' signal proportional to the summed current; and wherein the buffer stage converts the t-- C) summed current into a volta-e and provides a volta-e uain to supply an analog output Z-D Z-- Z:' within a predetern-Lined voltage range.

C 11=
6. The radio communication device of claim 5, wherein the buffer sta-e includes:

an operational amplifier having an input, an output, and a reference voltage terminal; an input resistor coupled between the input of the operational amplifier and the current bus, and tz.

I a feedback resistor coupled between the input and the output of the operational amplifier, wherein the feedback resistor and input resistor are chosen to provide the gain of the operational amplifier.

f, 3.

5. The radio communication device converter of claim 1, further comprising a buffer stage that inputs a summed current from the cur-rent bus and outputs the analog signal proportional to the summed current; and wherein the buffer stage converts the summed cur-rent into a voltage and provides a voltage gain to supply an analog output within a predetermined voltage range.

6. The radio corn-munication device converter of claim 5, wherein the buffer stage includes:

an operational amplifier having an input, an output, and a reference voltage terminal; an input resistor coupled between the input of the operational amplifier and the current bus, and a feedback resistor coupled between the input and the output of the operational amplifier, the feedback resistor and input resistor are chosen to provide the gain Z-- of the operational amplifier.

Amendments to the claims have been filed as follows What is claimed is:

1. A radio communication device incorporating, an antenna, an RF front end, a C radio frequency (RF) transceiver, a signal processor, a controller, and a di-ital-to- r-- Z' analog, converter for converting a digital input signal to an analog output signal, the ZD dic,ital-to-analoc, converter comprising:

zn C a plurality of current sources adaptable to be turned on and off, the current sources coupled to associated switches that are switchable between associated shunt loads and a conu-non current bus; a first plurality of control signals corresponding to respective bits of the digital input signal, the first plurality of control signals applied to the respective current sources so as to turn the current sources off and on; and a second plurality of control signals also corresponding to bits of the digital input sianal, the second plurality of control signals applied to the switches associated with the respective current sources so as to switch the switches between their associated shunt loads and the common current bus, wherein the second plurality of control signals operate the switches at a predetermined time period after the first plurality of control signals operate the associated current sources.

U.

2. The radio communication device of claim 1, wherein the second plurality of control signals operate to connect the switches to the conunon current bus L- at a predetermined time period after the first plurality of control signals operate to turn on the associated current sources so as to give the current sources time to settle, 3. The radio communication device of claim 2, wherein the second plurality of control signals operate to disconnect the switches from the common cur-rent bus at substantially the same time as the first plurality of control signals operate to tum off the associated current sources.

4. The radio communication device of claim 1, wherein the current sources provide currents that have a binary weighted relationship.