JPS6379415A - Chopper type comparator - Google Patents

Abstract

PURPOSE:To prevent the occurrence of noise by switching a signal potential and a reference potential in opposite phase to each other, applying them to two sets of circuits driven inversely and applying positive feedback from one output terminal to the other input terminal. CONSTITUTION:The signal potential Vs and the reference potential Vr are fed to capacitors 6a, 6b via switches 4a, 4b switched in opposite phase. The other terminals of the capacitors 6a, 6b are connected to output terminals 10a, 10b via inverter amplifiers 7a, 7b. The input and output of the inverter amplifiers 7a, 7b are switched by intermittent switches 8a, 8b and the output of one inverter amplifier 7a(7b) is fed back positively to the input of the other inverter amplifier 7b(7a) via an intermittent switch 9b(9a). Thus, the output of one amplifier is stabilized to a high potential and the other is stabilized to a low potential, a high gain is obtained and the occurrence of noise is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a chopper type comparator used in AD converters and the like.

[Summary of the invention]

The present invention relates to a chopper type comparator, and provides two sets of circuits that are invertedly driven, thereby making it possible to perform a good comparison with high sensitivity.

[Conventional technology]

The chopper type comparator is constructed as shown in FIG. In the figure, the terminal (41) to which the signal potential Vs is supplied
and a terminal (43) to which reference potential Vr is supplied are connected to one end of a capacitor (45) through a changeover switch (44). The other end of this capacitor (45) is connected to the input of an inverter amplifier (46), and this amplifier (45) is connected to the input of an inverter amplifier (46).
6) are connected through an on/off switch (47), and the output of each amplifier (46) is connected to one end of a capacitor (48). The other end of this capacitor (4) (48) is connected to the input of an inverter amplifier (49), and the input and output of this amplifier (49) are connected through a connection switch (50). The output terminal (5) is connected to the output terminal (51) from the output of the
2) is derived.

In this circuit, the switches (44) are alternately controlled by the phase of the clock signal φ, 1, and the switch (4''n (50)) is turned on by the phase of the clock signal j. The reference potential Vr is supplied to the circuit at the phase of , and the capacitors (45) and (48) are charged to stabilize at this potential.Then, the switch (44) is switched at the phase of the clock signal φ. , (47) When (50) is turned off, if the signal potential VS from the terminal (41) is even slightly higher than the reference potential Vr, the output of the amplifier (46) becomes a low potential, and the output of the amplifier (49) becomes high potential and the output terminal (52)
A low potential is output. Also, the signal potential ■s is the reference potential V
If it is even slightly lower than r, a high potential is output to the output terminal (52).

However, when trying to apply this device to a so-called flash type AD converter, for example, in order to obtain an 8-bit digital signal, the above-mentioned device must be
In this case, if the maximum amplitude of the input signal is 1V, the sensitivity of each comparator is required to be about 4mV.

However, when trying to obtain a logic level comparator output from such a small input, for example, inverter amplifiers (46) (49) are used to obtain a desired gain.
) increases the absolute delay time due to the inverter amplifier, so switches (47) (50)
It is necessary to use different timings for each intermittence. For this reason, there is a risk that the timing clock generation circuit becomes complicated or that noise due to the complicated lock signal is generated.

[Problem that the invention seeks to solve]

As described above, the conventional technology requires a complicated timing clock to obtain a desired output, which poses problems such as the risk of noise generation.

[Means for solving problems]

The present invention provides a signal J1-potential terminal (1) and a reference potential terminal (3).
1 are connected to one ends of the first and second capacitors (6a) and (6b), respectively, through first and second changeover switches (4a) and (4b), which are switched in opposite phases to each other. The other ends of the capacitors 2 and 2 are connected to the first and second inverter amplifiers (7a) and (7b), respectively.
The input and output of these first and second inverter amplifiers are connected through first and second on/off switches (8a) and (8b), respectively, and the first and second inverter amplifiers are The outputs of the amplifiers are connected to the inputs of the inverter amplifiers on opposite sides through third and fourth intermittent switches (9a) and (9b), respectively, and the first and second intermittent switches and the third and third This is a chopper type comparator in which the on/off switch No. 4 is driven in opposite phase.

[Effect]

According to this, since positive feedback is applied to each other using two sets of circuits that are invertedly driven, a desired output can be obtained with the ff1i configuration, and the generation of noise can be prevented.

(Example) In Fig. 1, the terminal to which the signal potential v9 is supplied (
1) and a terminal (3) to which the reference potential Vr is supplied are connected to the first and second fixed contacts of the changeover switch (4a) (4b), respectively, and the switch (4a) (
4b) are mutually switched and driven. This switch (4a)
Each movable contact of (4b) is a capacitor (6a)
(6b) is connected to one end of this capacitor (6a
) (6b) The other end is the inverter amplifier (7a) (7
b) is connected to the input of this inverter amplifier (7a)
Output of (7b) and capacitor (6a) (6b)
Intermittent switch (8a) (8
b) and is connected through the inverter amplifier (7
a) The output of (7b) is connected to the on/off switch (9a
) (9b) to the opposite capacitor (6a) (6
b) connected to the other end. And from this inverter amplifier (7a) (7b) the output terminal (10a) (
10b) is derived.

In this circuit, the changeover switch (4a) is the second
It is switched to the terminal (11) side at phase φ as shown in Figure A, and switched to the terminal (3) side at phase 1 as shown in Figure B, and the switch (4b) is switched in the opposite phase. .

Furthermore, the intermittent switches (8a) and (8b) are turned on to the phase T, and the intermittent switches (9a and 9b) are turned on to the phase φ' as shown in FIG.

Therefore, in this circuit, in phase 1, the upper circuit is stabilized at the reference potential Vr, and the lower circuit is stabilized at the signal potential VS. Then, the signal potential V at phase φ.

When Vr is even slightly higher than the reference potential Vr, the input of the inverter amplifier (7a) rises and the output drops by one step. Further, the input of the inverter amplifier (7b) decreases and the output increases. By feeding back these outputs to the inputs of the amplifiers on the opposite side, each amplifier becomes a positive feedback, and the output of the amplifier (7a) is at a low potential, and the amplifier (
The output of 7b) is stabilized at a high potential.

This is how signals are compared,
According to the above-mentioned device, since positive feedback is applied to each amplifier, an output can be obtained with extremely high commercial gain.
A logic level comparator output can be obtained with only one stage of circuit. Therefore, there is no need to use a complicated lock signal or the like, and there is no risk of noise being generated thereby. Note that the phase φ that controls the switches (9a) (9b)
' may be the same as the phase φ, but it is preferable that at least the rising edge is delayed to some extent.

Further, according to the above-mentioned device, since the input signal is supplied in an inverted state, the sensitivity is doubled, and A with more la+accuracy
A D converter or the like can be formed.

Furthermore, FIG. 3 shows the capacitor (6a) (6
b) is applied to a circuit that prevents a reduction in the transfer gain of
) (llb) and LVi connection switch (12a) (1
2b) through the inverter amplifier (7a) (7h)
This switch (12a) is connected to the input of
(12b) is driven on in phase 1. According to this, by providing the buffer circuit (lla) (jlb), the influence of the human power capacity of the inverter amplifier (7a) (7b) on the capacitor (6a) (6b) is reduced, and the capacitor (6a) (6h) This prevents the transmission gain from decreasing.

In addition, Figure 4 was proposed earlier by the applicant (Japanese Patent Application No. 1986-11).
5029), and in this figure, the movable contacts of the switches <4a) (4b) are connected to the buffer circuit (13
a) (13b) through capacitor (6a) (
6b). According to this, by providing the buffer circuits (13a) (13b), the input capacitance is reduced, the signal transmission speed is increased, and power consumption can be reduced.

Note that the above-mentioned circuit is not limited to the school MO8I-transistor, but can be applied to circuits using SOI, SIT, GaAs, etc.

〔Effect of the invention〕

According to this invention, positive feedback is applied to each other using two sets of circuits that are invertedly driven, so a desired output can be obtained with a simple configuration, and noise generation can be prevented. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of the present invention, FIGS. 2 to 4 are diagrams for explaining the same, and FIG. 5 is a diagram for explaining a conventional technique. +l) f3) is the terminal, (4a) (4b) is the changeover switch, (6a) (6b) is the capacitor, (7a)
(7b) is an inverter amplifier, (8a) (8b
) (9a) (9b) is an on/off switch. Same as Hidemori Matsukuma Figure 1 Time Night Figure 2 f Chew A! East! lJ Figure 5

Claims (1)

[Claims] A signal potential terminal and a reference potential terminal are connected to one ends of the first and second capacitors, respectively, through first and second changeover switches that are switched in opposite phases to each other, The other ends of the two capacitors are connected to the inputs of the first and second inverter amplifiers, respectively, and the input and output of the first and second inverter amplifiers are connected through the first and second on/off switches, respectively. and the outputs of the first and second inverter amplifiers are connected to the inputs of the inverter amplifiers on opposite sides of each other through third and fourth on/off switches, respectively, and the first and second on/off switches and the above A chopper type comparator in which the third and fourth intermittent switches are driven in opposite phases.