JPS62231499A - Sample holding circuit - Google Patents

Abstract

PURPOSE:To constitute the titled sample holding circuit with high accuracy by components having an accuracy which is not too high by selecting a high gain for components constituting an inverting circuit. CONSTITUTION:The 1st switching means SW1 is turned on at sampling and turned off at holding by switching control and the 2nd switching means SW2 is turned on at least at the start of sampling and turned off at holding by switching control, and the 3rd switching means SW3 is turned off at sampling and turned on at holding by switching control. An output voltage Vout has a value obtained by adding Vin-Vtp (prescribed voltage) to the input voltage Vi of the inverting circuit INV, and when the gain of the inverting circuit INV is considerably higher than the unity, the output voltage is expressed as Voutapprox.=Vin. Thus, in selecting a large gain for the inverting circuit INV, the accuracy of the sample holding circuit is increased even when components have not so much high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION The sample and hold circuit of the present invention will be explained according to the following items.

A. Industrial field of application B0 Overview of the invention C1 Prior art [Figs. 6 and 7] D9 Problems to be solved by the invention E0 Means for solving the problems F0 Effects G. Examples [First Figures to Figures 5] a. One embodiment [Figures 1 to 3] a-11 Circuit configuration [Figures 1 and 2] a-20 Circuit operation [Figure 3] b. Other implementations Example [Fig. 4, Fig. 5] Effect of H. JA Akira (A. Field of Industrial Application) The present invention relates to a novel sample-and-hold circuit.

(B. Summary of the Invention) The present invention provides a sample-and-hold circuit that operates at high speed without the occurrence of element variations, offsets due to temperature characteristics, or 1/f noise without using unnecessary high-performance elements. To make it so.

a hold capacitor, an inverting circuit that receives an input signal via the hold capacitor, a first switching means that is turned on during sampling to allow charging of the hold capacitor by the input signal, and a first switching means that is turned on during sampling to input and output the inverting circuit. a second switching means that connects the terminal of the hold capacitor on the inverting circuit side to a predetermined potential by short-circuiting between the two switching means; It is characterized in that it has a third switching means for connecting.

(C, prior art) [Figures 6 and 7] FIG. 6(A) shows a sample and hold circuit.

CB) and those shown in FIGS. 7(A) and (B). In the case shown in FIG. 6, as shown in (A), the input voltage Vin is applied to the hold capacitor C via the switching circuit sw, and the capacitor C
The output is taken out via a voltage floor consisting of a buffer operational amplifier Amp. As shown in FIG. 3B, the switching circuit sw is turned on and off by the pulse φ, so that sampling and holding are performed alternately.

In addition, what is shown in FIG. 7 is a P-channel MO3FETQP and an N-channel MO3FET as shown in FIG.
Connect Qn in parallel.

Switching pulse φ is applied to MOSFETQn, MO5F
A pulse φ obtained by inverting the switching pulse φ is applied to ETQp to turn on and off the parallel circuits of Qp and Qn, thereby alternately performing sampling and holding.

(D. Problem that the invention attempts to solve) By the way, the 6th problem
The sample and hold circuit shown in figure (A) is a MOS
When the circuit is configured with an IC, linearity is achieved as a buffer operational amplifier.

It is difficult to obtain products with excellent performance regarding DC offset, etc.
Therefore, it is extremely difficult to obtain a high-precision MOS sample-and-hold circuit that outputs the same voltage as the sampled input voltage as an output voltage, and although its high speed is sufficient for audio applications, it is insufficient for video applications. .

Further, in a sample hold circuit as shown in FIG. 7(A), the input voltage Vin becomes the so-called power supply voltage, and
The switching pulses that drive MOSFETQP and Qn have a rise time td and a fall time td that cannot be ignored, as shown in the same figure (B), so MOSFETQ
The time required for p and Qn to switch from on to off or from on to off changes depending on the magnitude of the input voltage Vin. Therefore, depending on the magnitude of the input voltage Vin, M
The response speeds of the O5FETs Qp and Qn are different, resulting in jitter in the sampling timing.

The present invention was made to solve the above-mentioned problems.
It is an object of the present invention to provide a sample-and-hold circuit that does not generate /f noise, has no sampling jitter, and operates with high precision and high speed without using any high-performance elements.

(E. Means for Solving the Problems) In order to solve the above problems, the sample and hold circuit of the present invention includes a hold capacitor, an inverting circuit that receives an input signal via the hold capacitor, and a circuit that is turned on at the time of sampling. A first switching means that allows the hold capacitor to be charged by an input signal, and a second switching means that is turned on during sampling to short-circuit between the input and output of the inverting circuit to set the terminal of the hold capacitor on the inverting circuit side to a predetermined potential. The device is characterized in that it has a third switching means that is turned on during hold to connect the output side of the inverting circuit to the terminal of the hold capacitor on the opposite side of the inverting circuit.

(F. Effect) In the sample-and-hold circuit of the present invention, at the time of sampling, the capacitor is charged by the voltage Vin-Vtp, which is the difference between the input voltage (denoted as vin) and the above-mentioned predetermined voltage (denoted as vtp). During hold, the difference between the voltage on the input side of the 1-inverting circuit (denoted as Vi) and the above-mentioned predetermined voltage Vtp is amplified by the inverting circuit (the gain is designated as Ginv), and the output voltage (denoted as V out) is the output voltage (denoted as V out) and the above-mentioned predetermined voltage Vtp. This state occurs as a difference from the predetermined voltage Vtp. The output voltage V out is the sum of the input voltage VE of the inversion circuit and the terminal voltage of the capacitor, ie, Vin-Vtp.

Therefore, the following two equations hold true.

−Ginv (V t −Vtp) =Vout −
VtpV t + (Vin-Vtp) = Vout The following equation is established from the above two equations.

1+G inv 1+G invSo, Gi
If nv, that is, the gain of the inverting circuit, is considerably larger than 1, Vout>Vin. Therefore, the accuracy of the sample-and-hold circuit of the present invention does not depend on the accuracy of the elements constituting the inverting circuit, but simply depends on the gain. The hold circuit can be constructed from elements that do not allow for very high precision.

Furthermore, the level of the terminal on the inverting circuit side of the capacitor when sampling is fixed at the above-mentioned predetermined potential, the sample value is determined when the second switching means is turned off, and the sample timing changes depending on the magnitude of the input voltage. There is no fear that this will occur, so sampling sickness can be eliminated.

(G. Embodiment) [FIGS. 1 to 5] The sample and hold circuit of the present invention will be described in detail below according to the embodiment shown in the accompanying drawings.

(a. One Embodiment) [FIGS. 1 to 3] FIGS. 1 to 3 are for explaining an example of implementation of the sample and hold circuit of the present invention.

(a-1, circuit configuration) [Figures 1 and 2] Figure 1 is a circuit diagram. 5 In the figure, SWl is inserted between the input terminal to which the input voltage Vin is input and one end of the capacitor C. In this switching circuit, switching is controlled by a switching pulse φ1. The other end of the switching circuit SW1 is connected to the input terminal of the inverter INV, and the output terminal of the inverter INV directly serves as the output terminal of this sample and hold circuit. A switching circuit SW2 is connected between the output terminal and the input terminal of the inverter INV, and a switching circuit SW3 is connected between the connection point between the capacitor C and the switching circuit SWl and the output terminal of the inverter INV. The above switching circuit SW
2 is switched by the switching pulse φ2, and the switching circuit SW3 receives the switching pulse φ3.
Switching is controlled by

Figure 2 shows the circuit configuration of the inverter INV.
Qp is a P-channel AzMOSFET, Qn is an N-channel MO5FET, and the two MOSFETs QP,
Qn are connected in series with each other and commonly receive the same voltage Vin as an input voltage. Then, the connection point becomes an output terminal in an on state.

(a-2, circuit operation) [Figure 3] Figure 3 is a time chart, and each switching circuit 5wt
-5W3 switching pulses are shown.

During sampling, switching circuits SW1 and SW2 are turned on, and switching circuit SW3 is turned off. At this time, the two MOSFETs Qp and Q in the on state are
The connection point (output terminal) with MOSFET n and its input side are short-circuited by switching circuit SW3, and as a result, the voltage at the inverter side terminal of capacitor C is equal to that of the two MOSFETs Qp and Qn. The turning voltage Vtp (approximately 1/2 Vdd) is determined by the ratio. Therefore, the capacitor C is connected to the input voltage Vin and the turning voltage Vt.
It is charged with the voltage Vin-Vtp, which is the difference between p and p. Incidentally, the electric charge Qs charged to the capacitor C by this charging is expressed by the following equation.

Qs=(Vin-Vtp)C Note that in this equation, C is the capacitance of the capacitor C.

During hold, the switching circuits SWI and SW2 are turned off, and the switching circuit SW is turned on. Then, a circuit is formed in which the output terminal of the inverter INV is connected to the opposite terminal of the capacitor C, that is, a loop is formed by the capacitor C and the inverter INV. As a result, the following two equations hold true.

−Ginv (V i −Vtp) =Vout −
VtpV i + (Vin-Vtp) = Vout where vi is the voltage on the input side of the inverter INV, and Gin is the gain of the inverter INV.

As a result, the following equation holds true.

When Gin is very large (considerably larger than 1), it can be said that V out is equal to Vin. Therefore, if you select an inverter INV with a large gain Gin, the MO
Even if elements such as SFETs do not have very high precision, the precision of the sample and hold circuit can be increased.

As long as SW2 is not turned off before the switching circuit SWI, that is, if SW2 is turned off before the input voltage Vin applied to the capacitor C is turned off by the switching circuit SW1, the capacitor C is charged. Since the charge ff1Q to be generated is determined when the switching circuit SW2 is turned off, the sample value is determined at the timing when SW2 is turned off. Therefore, unlike the sample and hold circuit shown in FIG. 7, there is no fear that the sample timing will shift depending on the magnitude of the input voltage.

Note that before the switching circuit SWI is turned off.

In order to turn off the switching circuit SW2, the off timing of the switching circuit SW2 may be set in advance by a time t before the off timing of the switching circuit SWI, as shown by the two-dot chain line in FIG.

(b, Other Embodiments) [Figures 4 and 5] Figure 4 shows another embodiment of the sample and hold circuit of the present invention, and Figure ff15 is a time chart explaining the operation of the sample and hold circuit. .

This sample-and-hold circuit is different from the sample-and-hold circuit shown in FIG. The switching circuit SW3 is connected so that the output voltage is taken out from the buffer operational amplifier OF.
Therefore, the output voltage of the buffer operational amplifier OP is fed back to the connection point between the capacitor C1 and the switching circuit SWI instead of the output voltage of the inverter INV, and,
The difference is that a switching circuit SW4 is added between the input terminal of the buffer operational amplifier oP and the input terminal of the sample and hold circuit (terminal on the side opposite to the capacitor C1 of the switching circuit SWI), but other points are the same. There is.

The switching circuit SW4 is the switching circuit S
Switching is controlled using the same switching pulse φ4 as the switching pulse φ1 that controls switching of WI.

This sample and hold circuit compensates for the lack of accuracy of the sample and hold circuit due to insufficient amplification of the inverter INV by providing an operational amplifier OP for Bazza on the output side of the sample and hold circuit shown in Figure 1. In this respect, the sample-and-hold circuit shown in FIG. 1 can have better performance.

In each of the above embodiments, the circuits were constructed using complementary MO3ICs, but the sample-and-hold circuit of the present invention can also be applied to circuits constructed using bipolar transistors.

(H, Effects of the Invention) As is clear from the above description, in the sample and hold circuit of the present invention, a hold capacitor j- is inserted in the path through which the signal input to the 1-inverting circuit passes, and the input of the hold capacitor is A first switching means is connected to the side, a second switching means is connected between the input terminal and the output terminal of the inverting circuit, and a connection point between the first switching means and the hold capacitor is connected to the inverting circuit. , a third switching means is connected between the output side of the inverting circuit, and the first switching means is controlled to be in an on state during sampling and an off state during hold;
Switching control is performed such that the second switching means is turned on at least when sampling starts and remains off during hold, and the third switching means is turned off during sampling and turned on during hold. It is characterized by being controlled by switching.

Therefore, in the sample-and-hold circuit of the present invention, at the time of sampling, the capacitor is connected to the voltage Vin-Vt which is the difference between the input voltage (denoted as Vin) and the above-mentioned predetermined voltage (denoted as Vtp).
It is charged by p. When holding, the difference between the input voltage (Vt) of the inverting circuit and the predetermined voltage Vtp is amplified by the inverting circuit (the gain is Ginv).
The difference between the output voltage (referred to as Vout) and the predetermined voltage Vtp appears. and,
The output voltage V out is the sum of the input voltage Vi of the inversion circuit and the terminal voltage of the capacitor, ie, Vin-Vtp.

Therefore, two equations of first order are established.

−Ginv (V t −Vtp) =Vout −
VtpV i + (Vin-Vtp) =Vout The following equation is established from the above two equations.

Therefore, if Ginv, that is, the gain of the inverting circuit, is considerably larger than 1, then Vouta+Vin. Therefore, the accuracy of the sample-and-hold circuit of the present invention does not depend on the accuracy of the elements constituting the inverting circuit, but only on the gain.As long as an inverting circuit with a high gain is selected, very high-precision sample-and-hold can be achieved. The circuit can be constructed with elements that do not have very high precision.

Furthermore, the level of the terminal on the inverting circuit side of the capacitor when sampling is fixed at the above-mentioned predetermined potential, the sample value is determined when the second switching means is turned off, and the sample timing changes depending on the magnitude of the input voltage. There is no fear that it will happen.

[Brief explanation of drawings]

1 to 3 are for explaining an example of the implementation of the sample and hold circuit of the present invention. FIG. 1 is an overall circuit diagram, FIG. 2 is an inverter circuit diagram, and FIG. 3 is a time chart. 4 and 5 are for explaining other embodiments of the sample and hold circuit of the present invention, and FIG. 4 is a circuit diagram,
Figure 5 is a time chart, Figure 6 (A) and (B) are the first
Figure 7 (A) is a circuit diagram, Figure 7 (B) is a time chart, and Figures 7 (A) and (B) are for explaining a conventional example.
(A) is a circuit diagram, and (CB) is a waveform diagram of a switching pulse. Description of symbols INV@φ・Inverting circuit, CΦ・Hold capacitance, C1・Hold capacitance, SWl・・First switching means, SW2・・Second switching means. SW3...Third switching means amount Applicant: Yuji Komatsu, Patent Attorney, Sony Corporation !G diagram time chart (B) '1 Explanatory diagram of the conventional design of PJ1 Figure 6. φ circuit diagram (,4) Switching q' hull waveform diagram CB> A light diagram of the second conventional configuration Figure 7

Claims (1)

[Claims] (1) A hold capacitor is inserted in the path through which the signal input to the inverting circuit passes, and a first switching means is connected to the input side of the hold capacitor, and between the input terminal and the output terminal of the inverting circuit. A second switching means is connected to the first switching means, a third switching means is connected between the connection point between the first switching means and the hold capacitor and the output side of the inverting circuit, and the first switching means is connected to the output side of the inverting circuit. The switching means is controlled to be on during sampling and off during hold, and the second switching means is controlled to be on at least when sampling starts, and kept off during hold. A sample-and-hold circuit characterized in that the third switching means is controlled to switch so that it is in an off state when sampling and is in an on state when holding.