JPS6251008B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a comparison circuit that can compare both input signals and output a comparison result even when the level difference between the input signals is small.

Conventional comparator circuits have low gain, and therefore the two signals A and B to be compared, as shown in FIG.
In a comparator circuit given a comparator, it is necessary to connect three or more stages of comparators I ₁ , I ₂ . It is not always possible to output a signal level of "1" or "0" that represents the comparison result, and there is a possibility that the output will be at an intermediate voltage level between the two, causing a loss of operational reliability. .

The present invention eliminates the drawbacks of the conventional circuit described above, provides a circuit configuration suitable for LSI implementation, and provides a comparison circuit capable of outputting highly reliable comparison results even in the case of minute signal level differences. Next, the present invention will be explained in detail using the figures.

FIG. 2 shows a comparator circuit according to the present invention, in which signals to be compared are applied to input terminal A and input terminal B, and if the comparison result is V _A > V _B for input signal V _A and input signal V _B. For example, if the output “0” is V _A < V _B , the output “1” is the output terminal OUT.
is derived.

Although this embodiment will be described with reference to a configuration using N-channel MOS transistors, it can also be configured in exactly the same way with P-channel MOS or CMOS. The input signal V _A at the terminal A is applied to the capacitor C ₀ via the first switching transistor Q 1 , and the input signal V _B at the terminal _B is also applied to the capacitor C _{0 via the second switching transistor Q 2 .}
given to. To the gate of the first switching _{transistor Q1} , a pulse signal _φA shown in the timing chart of _FIG . is an inverted pulse signal
_A is given to control the switching action.
A first inverter INV ₁ consisting of transistors Q ₅ and Q ₆ is connected to the other electrode side of the capacitor C ₀ , and a second inverter INV ₂ consisting of transistors Q ₇ and Q ₈ is connected to the first inverter INV ₁ . It is connected. The output of the first inverter INV ₁ is applied to the input terminal of the second inverter INV ₂ and fed back to the input terminal of the first inverter INV ₁ via _the third switching transistor Q ₃ . The output is fed back to the input terminal of the first inverter _INV1 via the fourth switching transistor _Q4 . The gate of the third switching transistor _Q3 is connected to the pulse signal _φA.
is applied to the gate of the fourth switching transistor _Q4 to control the switching operation, and the gate of the fourth switching transistor _Q4 is provided with _the voltage shown in FIG. As shown in the timing chart, a pulse signal '_A' whose width at the "0" level is equal to or longer than _the inverted pulse signal _A is applied to control the switching operation. Then above
The operation of a comparison circuit having a MOS configuration will be explained.

First, MOSICs configured on the same semiconductor substrate
(or LSI), the electrical characteristics of two inverter circuits of the same shape located very close to each other on a semiconductor substrate can be treated as being almost the same. Therefore, the transistors Q5 and _Q5 shown in FIG.
The inverter INV ₁ consisting of Q ₆ and the inverter INV ₂ consisting of transistors Q ₇ and Q ₈ are located very close to each other and are designed to have the same shape, so the input/output characteristics of the inverters are equal.

Now, when pulse signals φ _A , _A , and ′ _A are applied to the respective switching transistors Q ₁ to Q ₄ at the timing shown in FIG. 3, when the pulse signal φ _A becomes logical “1”, the first Switching transistor Q ₁ conducts and the input signal voltage V _A volts is transmitted to the N ₁ point of capacitor C ₀ . On the other hand, the third switching transistor _Q3 also becomes conductive, and the first
The ₂ input terminals N and ₃ output terminals N of inverter INV ₁ are
The voltage V at a point P on the input/output curve of the inverter shown in FIG. 4 where the input voltage and output voltage are equal is ₀ volts. At this time, since the characteristics of the first inverter _INV1 and the second inverter _INV2 are equal, the voltage at the output terminal _N4 of the second inverter _INV2 also becomes _V0 volts. Next, when the pulse signal φ _A is set to "0" and the inverted pulse signal _A is set to "1", the voltage at the _N1 point becomes the input voltage of the input terminal V _B volts. At this time the capacity
Assuming that C ₀ is designed to be sufficiently large compared to other storage capacities in the semiconductor circuit, N ₂
The voltage at the point will be V ₀ -(V _A -V _B ) volts.

Next, the comparison operation will be explained using FIG. 5. In the same figure, since the electrical characteristics of the first inverter INV ₁ and the second inverter INV ₂ can be treated as being equal, the curve E shown as a solid line represents the first inverter INV 1 with the input V _IN1 on the X axis and the output V _OUT1 on the Y axis. Inverter INV ₁
The curve F shown by the broken line shows the input/output characteristics of the second line, where the Y axis is the input V _IN2 and _the
The input/output characteristics of inverter INV ₂ are shown. For example, if there is a relationship of V _A > V _B between the input signal V _A and the input signal V _B , the voltage V ₀ - (V _A - V _B ) volts at the above _N2 points in FIG. V ₀ volts to △V
V changes by = |V _A −V _B | becomes ₁ volt.
The output of the first inverter INV ₁ corresponding to the input voltage V ₁ becomes the output V ₂ corresponding to the point P' on the curve E. Also, this first inverter INV ₁ output V ₂ volts is equal to the second inverter INV ₂ input voltage, so from curve F the output of the second inverter INV ₂ is
V becomes ₃ volts. As a result, for a change in input voltage of ΔV, a change in volts (V ₀ −V ₃ ) larger than ΔV can be obtained from the input/output characteristics of the inverter. Next, the fourth switching transistor
Since Q ₄ becomes conductive at the same time as or slightly delayed from the cut-off operation of the third switching transistor Q ₃ , the potential of N ₄ , that is, V ₃ volts, becomes the fourth switching transistor.
The signal is transmitted to the input gate _N2 of the first inverter _INV1 through the switching transistor _Q4 . As a result, as is clear from Fig. 5, the first inverter
The output N ₃ points of INV ₁ almost reach the applied voltage V _D volts, and therefore the output N ₄ points of the second inverter INV ₂ reach
Reach GND.

In addition, if there is a relationship of V _A < V _B between the input signal V _A and the input signal V _B , the amount of change in the signal △V appears in the + direction from V ₀ volts, and the input/output characteristics shown in Figure 5. From the curve diagram, the output of the first inverter INV ₁ will be V' ₂ volts, and the output of the second inverter INV ₂ will be V' ₃ volts. As a result, when the pulse signal ' _A of the fourth switching transistor becomes "1", the second
A signal reaching approximately V _D volts is output from the output _N4 of the inverter INV ₂ . As shown above, input signal V
For _A and V _B , the minute level difference △V = |V _A
If V _A > V _B for −V _B |, the output is “0”
However, if V _A <V _B , an output "1" can be obtained.

The comparison circuit according to the present invention can be used not only for simply comparing two input signal levels, but also as an AD converter, for example. That is, as shown in FIG. 6, in the comparator circuit G according to the present invention, an analog signal is applied to an input terminal _A0 , and a reference signal that provides a level for digitization is inputted to the other input terminal _B0 . The reference signal can be generated by a conventionally known circuit, but for example, the applied voltage is divided by a resistor and a signal having a desired level is derived from each stage and used as the reference signal. A comparison is made between both input signals and the input analog signal is converted to digital at the level of the reference signal.

As described above, according to the present invention, it is possible to configure a comparison circuit with an extremely small number of circuit elements, eliminate the drawbacks of conventional circuits, and obtain a circuit configuration suitable for LSI implementation. Furthermore, even when the difference between the levels of the input signals to be compared is small, the circuit can use the input/output characteristics of the inverter to compare the difference as a clear difference, and the comparison accuracy can be significantly improved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional circuit, Fig. 2 is a circuit diagram of an embodiment according to the present invention, Fig. 3 is a waveform diagram of a pulse signal supplied to the circuit of the same embodiment, and Fig. 4 is an input/output diagram of an inverter. FIG. 5 is an input/output characteristic curve diagram for explaining the operation of the present invention, and FIG. 6 is a block diagram showing an application example of the present invention. Q ₁ to _{Q 8} : P channel MOS transistor,
INV ₁ , INV ₂ : Inverter, φ _A , _A , ′ _A : Pulse signal, C ₀ : Capacitor, A, B: Input terminal, OUT: Output terminal.

Claims (1)

[Claims] 1. A first switching element that receives a pulse signal to control conduction of a first compared signal, and a second switching element that receives an inverted signal of the pulse signal and controls conduction of a second compared signal. , a first inverter connected to the first switching element and the second switching element via a capacitor;
a second inverter connected to the first inverter; and a third inverter provided in a path for returning the output of the first inverter to the input end and to which the pulse signal is applied.
a switching element; and a fourth switching element, which is provided in a path for returning the output of the second inverter to the input end of the first inverter and conducts at the same time or after the interruption of the third switching element; A comparator circuit that compares the levels of the second compared signal and the second compared signal to form an output.