JPH0450634B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a switched capacitor integrator (hereinafter referred to as
It is abbreviated as SC integrator. ), especially its clock circuit.

[Technical background of the invention]

Generally, a switched capacitor integrator used in electronic filters, speech recognition circuits, speech synthesis circuits, etc. is constructed as shown in FIG. That is, 1 is a switched capacitor circuit (hereinafter,
It is abbreviated as SC circuit. ), 2 is an operational amplifier whose non-inverting input terminal (+) is grounded, C _f is an integrating capacitor, C _L is a load capacitor, and 3 is a clock circuit. The SC circuit 1 includes first and second CMOS switches (transmission gates) S ₁ and S ₂ connected in series, and third and fourth CMOS switches connected in series.
CMOS switch S ₃ , S ₄ and the above CMOS switch
It consists of a capacitor C connected between the mutual connection point of S ₁ and S ₂ and the mutual connection point of CMOS switches S ₃ and S ₄ , with one end of the third CMOS switch S ₃ serving as the input node 4. An input signal is applied, and the first and fourth
One end of each of the CMOS switches S ₁ and S ₄ is grounded, and one end of the second CMOS switch S ₂ serves as an output node 5 and is connected to the inverting input end (-) of the operational amplifier 2. The second and third CMOS switches S ₂ and S ₃ are connected to the first phase clock pulse pair (φ _p1 ,
The first and _fourth CMOS switches S ₁ and S ₄ are driven by the second phase clock pulse pair (φ _p2 ,
φ _o2 ). As is well known, the operation of the SC circuit 1 is as follows:
A current flows between them in accordance with the potential difference, the size of the capacitance C, and the clock pulse frequency (switch frequency), and is equivalent to a circuit in which a resistor is connected between the input and output nodes.

Furthermore, as is well known, the input/output characteristics of the Miller integrator consisting _of the SC circuit 1, the operational amplifier 2, and the integrating capacitor C _f shown in FIG. It is a function of the switch frequency of the circuit 1, and in particular, it is a linear expression of the switch frequency. Therefore, the integration time constant can be changed in proportion to the switch frequency, and if the mirror integrator described above is used as a filter component in a switched capacitor filter (SCF), the filtering frequency can be changed in proportion to the switch frequency. It becomes possible to change the

Note that the clock circuit 3 is generally a second clock circuit.
As shown in Figure a or Figure 2b, the clock input φ is taken out as it is as the clock output φ, and the φ input is inverted by a one-stage CMOS inverter _I1 to take out the inverted clock output, or the clock input φ is taken out as the clock output φ. The clock output φ is taken out through the CMOS inverters I ₂ and I ₃ in one stage, and the φ input is inverted by the CMOS inverter I ₁ in one stage to take out an inverted clock output.

When a clock circuit as shown in FIGS. 2a and 2b is used, the clock output pair φ has a phase difference equivalent to one CMOS inverter stage due to the difference in the number of gate stages in each signal path.

[Problems with the background art] By the way, the two-phase clock pair required in the SC circuit, that is, (φ ₁ , ₁ ) (φ _p1 , φ _o1 in Figure 1)
The inventor has found that when the phase difference between and (φ ₂ , ₂ ) (φ _p2 , φ _o2 in FIG. 1) has a predetermined relationship, an offset voltage is generated at the output of the SC integrator. When this offset voltage occurs, as will be described in detail later, it is as if a voltage source is inserted in series with the equivalent resistance of the SC circuit between the inverting input terminal (-) and the output terminal of the operational amplifier in the SC integrator. , a part of the output signal is affected by a limiter and its dynamic range becomes smaller, or in the case of a low-pass filter, the DC input (for example 1.0V)
A phenomenon occurs in which an offset voltage (for example, 0.1V) is added as an output error.

Next, with reference to the SC integrator in FIG. 3 and the timing diagrams in FIGS. 4 and 5, the above (φ ₁ , ₁ ), (φ ₂ ,
The relationship between the phase difference of φ ₂ ) and the offset voltage will be explained in detail. In the circuit of FIG. ₃ , _{the same} parts as in the circuit of FIG _. P-channel transistor in one switch _S2 , typically one of _S3
The gate-source mirror capacitance of P ₂ is CMP ₃ , the gate-drain mirror capacitance is CMP ₄ , the gate-drain mirror capacitance of N-channel transistor N ₂ is CMN ₃ , the gate-source mirror capacitance is
CMN ₄ represents the mirror capacitance between the gate and drain of _the P channel transistor P ₁ in one of the CMOS switches S ₁ and S ₄ driven by the second phase clock φ ₂ and ₂ .
CMP ₁ , gate-source mirror capacitance as CMP ₂ ,
The gate-source mirror capacitance of the N-channel transistor N ₁ is represented by CMN ₁ and the gate-drain mirror capacitance is represented by CMN ₂ , and the input node 4 is connected to the output terminal of the operational amplifier 2. Note that the mirror capacitances CMP ₁ to CMP ₄ and CMN ₁ to CMN ₄ are
It is smaller than the capacitance C of the SC circuit.

Now, as shown in Figure 4, the phase difference relationship between (φ ₁ , ₁ ) and (φ ₂ , ₂ ) above is such that if ₁ lags behind φ ₁ and similarly ₂ lags behind φ ₂ , then the offset No voltage is generated. The operation in this case will be described below in the order of periods .about. in FIG. 4. Note that the mirror capacitances CMP ₁ and CMN ₁ are ignored because they merely inject charge into the ground, and the clock amplitude is expressed as V _c .

During the period, both transistors N ₁ and P ₁ are in the on state, so the first and second CMOS
The charge at the connection point a of the switches S ₁ and S ₂ is discharged to ground.

During the period, φ ₂ becomes L (low level) and the transistor N ₁ is turned off. At this time,
-CMN ₂・V _c through Miller capacitance CMN ₂ at point a
is injected, but since transistor _P1 is still on, the above charge is discharged to ground.

During the period, ₂ becomes H (high level) and the transistor _P1 is turned off. At this time,
A charge of CMP·V _c is injected into point a through the mirror capacitance CMP ₂ . And each transistor P ₁ ,
Since N ₁ , P ₂ , and N ₂ are in the off state, the charge at point a is stored as is.

During the period, _φ1 becomes H and the transistor
_N2 turns on. At this time, a charge of CMN ₃ ·V _c is injected into point a through Miller capacitance CMN ₃ , and at the same time, the inverting input terminal of operational amplifier 2 (here
Let it be expressed as the IN point. ) to mirror capacity CMN ₄
A charge of CMN ₄ ·V _c is injected through. And since transistor _N2 is on, a
and the IN point are connected, and since the IN point is at ground potential due to the nature of operational amplifier 2, the charge at the point a (CMP ₂ · V _c + CMN ₃ · V _c ) is further injected into the IN point. Ru.

In the period of , becomes L and the transistor
_P2 turns on. At this time, charges of -CMP ₃ ·V _c and -CMP ₄ ·V _c are injected into point a and point IN through mirror capacitances CMP ₃ and CMP ₄ , respectively.
Since transistors N ₂ and P ₂ are each in an on state, point a and point IN are connected,
The above charges are respectively injected into the IN point. Therefore, the charge injected into the IN point so far is ~
(CMP ₂・V _c +CMN ₃・V _c +
CMN ₄・V _c ) and (−CMP ₃・V _c
−CMP ₄・V _c ).

During the period, φ ₁ becomes L and the transistor
_N2 is turned off. At this time, charges of _{-CMN3.V c and -CMN 4.V c are injected} into point a and point IN through mirror capacitances CMN ₃ and CMN ₄ , respectively. Since the transistor _P2 is in the on state, the above charges are respectively injected to the IN point.
Therefore, the charge injected into the IN point so far is equal to the sum of the charges during the period of (−
CMN ₃・V _c −CMN ₄・V _c ),
CMP ₂・V _c −CMP ₃・V _c −CMN ₄・V _C.

During the period, ₁ becomes H and the transistor
P ₂ is turned off. At this time, the mirror capacitors CMP ₃ and CMP ₄ are connected to point a and IN point respectively.
Charges CMP ₃ ·V _C and CMP ₄ ·V _C are injected.
The total charge injected into the IN point is CMP ₂・V _c −
CMP ₃・V _c −CMP ₄・V _c +CMP ₄・V _c =CMP ₂・
V _c −CMP ₃・V _c . And the transistor
P ₁ and P ₂ are the same size, and the mirror capacitance CMP ₂ ,
If CMP ₃ is equal, then CMP ₂・V _c −CMP ₃・
V _c =0, meaning that no charge was injected into the IN point. Furthermore, since each transistor P ₁ , N ₁ , P ₂ , N ₂ is in an off state, the charge at point a is stored as is.

During the period, _φ2 becomes H and the transistor
_N1 turns on. At this time, a charge of CMN ₂ ·V _c is injected into point a through the mirror capacitance CMN ₂ . Since the transistor _N1 is in the on state, the charge at point a that has been stored during the period is discharged to the ground.

In this way, (φ ₁ , ₁ ) as shown in Figure 4,
In the case of a phase difference relationship of (φ ₂ , ₂ ), no charge is accumulated at the IN point in each clock operation with a cycle of period ˜, so no offset voltage is generated.

On the other hand, as shown in Figure 5, the phase difference relationship between (φ ₁ , ₁ ) and (φ ₂ , ₂ ) is such that ₁ lags behind φ ₁ ,
Conversely, if φ ₂ lags behind ₂ , an offset voltage will occur. The operation in this case is explained in the fifth section.
The periods will be described below in the order of periods .

During the period , both transistors N ₁ and P ₁ are in the on state, so the charge at point a is discharged to the ground.

During the period, ₂ becomes H and the transistor
P ₁ is turned off. At this time, the mirror capacitance at point a
A charge of CMP ₂ ·V _c is injected through CMP ₂ , but since the transistor N ₁ is still on, the above charge is discharged to ground.

In the period , φ ₂ becomes L and the transistor
N ₁ is turned off. At this time, a charge of -CMN ₂ ·V _c is injected into point a through the mirror capacitance CMN ₂ . And each transistor P ₁ , N ₁ , P ₂ ,
Since N ₂ is in the off state, the charge at point a is stored as is.

During the period, _φ1 becomes H and the transistor
_N2 turns on. At this time, Miller capacitors CMN ₃ and CMN ₄ are connected to point a and IN point, respectively.
Charges CMN ₃ ·V _c and CMN ₄ ·V _c are injected.
And since transistor _N2 is in the on state,
Point a and point IN are connected, and the charge at point a (-CMN·V _c +CMN ₃ ·V _c ) is further injected into point IN.

In the period of , becomes L and the transistor
_P2 turns on. At this time, _charges of Vc of -CMP3 _{· Vc} and _-CMP4 are injected into point a and point IN through mirror capacitances _CMP3 and _CMP4 , respectively.
Since transistors N ₂ and P ₂ are each in an on state, point a and point IN are connected,
The above charges are respectively injected into the IN point. Therefore, the total charge injected into the IN point is −
CMN ₂・V _c +CMN ₃・V _c +CMN ₄・V _c −CMP ₃・
V _c −CMP ₄・V _C.

During the period, φ ₁ becomes L and the transistor
_N2 is turned off. At this time, charges of _{-CMN3.V c and -CMN 4.V c are injected} into point a and point IN through mirror capacitances CMN ₃ and CMN ₄ , respectively. Then, since the transistor _P2 is in the on state, the above charges are respectively injected to the IN point.
Therefore, the charge injected into IN so far is equal to the sum of charges during the period (−
CMN ₃・V _c −CMN ₄・V _c ),
−CMN ₂・V _c −CMP ₄・V _c −CMP ₄・V _c .

During the period, ₁ becomes H and the transistor
P ₃ is turned off. At this time, through the mirror capacitors CMP ₃ and CMP ₄ corresponding to point a and IN point,
Charges CMP ₃ ·V _c and CMP ₄ ·V _c are injected.
The total charge injected into the IN point is −CMN ₂・V _c −
CMP ₃・V _c −CMP ₄・V _c +CMP ₄・V _c =−
CMN ₂・V _c −CMP ₃・V _c . Further, since each transistor P ₁ , N ₁ , P ₂ , N ₂ is in an off state, the charge at point a is stored as is.

During the period, ₂ becomes L and the transistor
_P1 turns on. At this time, a charge of -CMP ₂ ·V _c is injected into point a through the mirror capacitance CMP ₂ , but since transistor P ₁ is in the on state, it is discharged to the ground together with the charge at point a that had been stored during the period. Ru.

In this way, (φ ₁ , ₁ ) as shown in Figure 5,
When the phase difference relationship is (φ ₂ , ₂ ), for each clock operation whose cycle is ~ period, the IN point has the above-mentioned (−CMN ₂ · V _c −
A charge of CMP ₃ ·V _c ) is injected, and this can be considered as a current. Therefore, in Figure 3
In the SC integrator, if we consider the SC circuit section to be equivalent to a resistor, the inverting input terminal (-) of operational amplifier 2
and the output terminal, the above equivalent resistance and integrating capacitance C
A return circuit exists in which the occurs.

FIG. 6 shows the results of a CAD simulation performed using a simulation circuit in which the input node 4 of the SC integrator is connected to the output terminal of the operational amplifier 2 as shown in FIG. Here, the horizontal axis shows the phase difference (phase lead, phase lag) of φ ₂ with respect to clock ₂ , the vertical axis shows the offset voltage, and characteristic A is the phase difference of φ ₁ from clock ₁ by a certain amount ( In this example, 100 ns), characteristic B is when the phase difference between clocks φ ₁ and ₁ is zero, and characteristic C is when the phase of φ ₁ is behind clock ₁ by a certain amount (100 ns in this example). handle.

From Figure 6, the phase difference of (φ ₁ , ₁ ) and (φ ₂ , ₂ )
When the phase difference is in the same direction, that is, phase ₁ lags phase φ ₁ and phase ₂ lags phase φ ₂ , or phase ₁ leads phase φ ₁ ,
It can be seen that the offset voltage is small when the φ ₂ phase leads the φ ₂ phase.

However, contrary to the above, when the phase difference of (φ ₁ , ₁ ) and the phase difference of (φ ₂ , ₂ ) are in opposite directions, that is, phase ₁ lags phase φ ₁ and phase ₂ is When the relationship is such that the _φ2 phase is ahead of the φ2 phase or _{the 1st} phase is ahead of the _φ1 phase and _{the 2nd} phase is behind the _φ2 phase, the offset voltage is large and a phase difference of ( _φ2 , ₂ ) of 10 ns occurs. It can be seen that a significant offset occurs even if the

The phase difference between φ ₂ and ₂ in a conventional clock circuit is caused by only one stage of CMOS inverter, and is generally less than 10 ns. However, due to the delay due to CR in the wiring from the clock circuit to the SC circuit, the phase difference of φ in the SC circuit is
It may be about 10ns, and in some cases SC
The phase difference of φ in the circuit may be reversed from the phase difference in the clock circuit. In this way, in the conventional SC integrator, (φ ₁ ,
₁ ) It is not determined whether the phase difference relationship between (φ ₂ , ₂ ) will be in the same direction or in opposite directions, and if they are in opposite directions, a large offset voltage will occur even if the phase difference shifts by only 10 ns. It was hot.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and
By specifying the phase difference relationship between the two-phase clock pair applied to the switched capacitor circuit, the operating order of each transistor in the switched capacitor circuit can be specified, and the switched capacitor integrator has a small offset voltage. It provides:

[Summary of the invention]

That is, in the present invention, a switched capacitor circuit is connected between an input node and an inverting input terminal of an operational amplifier, an integrating capacitor is connected between an output terminal and an inverting input terminal of the operational amplifier, and the switch・
The capacitor circuit is a switched capacitor integrator consisting of two CMOS switches driven by a first phase clock pair, two CMOS switches driven by a second phase clock pair, and one capacitor. A clock circuit that supplies a pair of clock outputs to each CMOS switch is configured to provide a clock output pair to each CMOS switch.
In a CMOS switch, the P channel transistor is on, the N channel transistor is on, and the P channel transistor is on.
The clock circuit and the switched circuit are arranged so that the operating order is such that the N-channel transistor is off, the N-channel transistor is off, or the N-channel transistor is on, the P-channel transistor is on, the N-channel transistor is off, and the P-channel transistor is off. This is characterized in that the phase difference relationship between the pair of clock outputs is set in consideration of the delay due to the wiring between the clock output and the capacitor circuit. And the clock circuit is
The phase difference within the clock output pair can be determined by using a capacitor, a combination of a capacitor and a resistor, or a capacitor, a resistor, and a MOS.
Combination with inverter or multi-stage MOS
This is set by a delay means consisting of an inverter.

[Embodiments of the invention]

Hereinafter, one implementation order of the present invention will be explained in detail with reference to the drawings. The clock circuit shown in FIG.
The phase difference relationship between the two-phase clock pairs (φ ₁ , ₁ ) and (φ ₂ , ₂ ) required in the SC integrator as described above with reference to the figure is in the same direction as described above. For each clock output pair (hereinafter, typically φ,
It is expressed as ) is configured so that the phase difference between φ and φ can be set sufficiently so that it will not be reversed even if there is a delay due to the CR of the wiring described above. That is, for example, when delaying the phase difference of the output compared to the φ output, the φ input is taken out as it is as the φ output, and the φ input is
After inversion by the CMOS inverter I, the output is taken out with a sufficient delay provided by the capacitor _C1 connected between the output terminal and the ground terminal.
Therefore, as a clock circuit output, φ ₁ is delayed by 20 ns, for example, and φ ₂ is delayed by _{20 ns} .
By delaying by 20 ns, the phase difference between (φ ₁ , ₁ ) and (φ ₂ ,
₂ ) The relationship with the phase difference is maintained in the same direction regardless of the delay due to wiring. As a result, the operation order of each transistor in the SC circuit 1 of FIG. 1 is as described above with reference to FIG. 4: N-channel transistor is on, P-channel transistor is on, N-channel transistor is off,
P channel transistor is turned off. In addition,
If ₁ is advanced from φ ₁ and ₂ is advanced from φ ₂ , the operating order of each transistor is P channel transistor on, N channel transistor on, P channel transistor off, N channel transistor off. become. Therefore, as is clear from FIG. 6, the offset becomes extremely small.

Note that the delay amount due to the above capacitance C ₁ is equal to this capacitance
It is determined by the on-resistance and time constant of the on-side transistor of C ₁ and CMOS inverter I ₁ .

As mentioned above, the delay means for providing the required phase difference between the clock output pair φ is the capacitance described above.
It is not limited to C ₁ and can be modified in various ways. That is, FIG. 9 shows
The CMOS inverter I ₁ and the capacitor C ₁ in FIG. 8 are connected in another stage in cascade to take out the φ output, and the φ input is inverted by the CMOS inverter I ₂ in one stage to take out the output. Figure 10 shows
A resistor R ₁ is inserted between the CMOS inverter I ₁ and the capacitor C shown in FIG. 8, and the time constant can be greatly deviated without increasing the capacitor C ₁ unnecessarily. Figure 11 shows the resistance R and capacitance C ₁ in Figure 10.
Another set is connected in cascade. Further, in FIG. 12, a resistor R ₂ and a capacitor C ₂ are connected to the input side of a CMOS inverter I ₁ . 1st
FIG. 3 shows another set of resistor R ₂ and capacitor C ₂ of FIG. 12 connected in cascade. In Figure 14, another set of CMOS inverter I ₁ , resistor R ₁ and capacitor C ₁ of Figure 10 is connected in cascade to take out the φ output, and the φ input is inverted by one stage CMOS inverter I ₂ to generate power. It was designed to be taken out.

In this way, any number of stages of C or CR may be used so that a required phase difference is generated between the φ output and the output on either the input side or the output side of the CMOS inverter. In this case, the capacitor C may be a MOS gate capacitor.

Furthermore, for the purpose of waveform shaping and improving driving ability,
As shown in FIGS. 15 to 21, buffer circuits B at desired stages may be inserted into the φ output signal path and the output signal path, respectively. The circuits shown in FIGS. 15 to 21 are obtained by adding a buffer circuit B to the circuits shown in FIGS. 8 to 14.

Here, as an example, the phase difference between the clock output pair φ in the circuit shown in FIG. 17 will be calculated. capacity
C ₁ = 1pF, resistor R ₁ = 20kΩ, CMOS inverter I ₁
It is assumed that the on-resistance of the buffer inverter I is 10 kΩ, and the input threshold voltage of the buffer inverter I is 1/2 of its power supply voltage V _DD . The system from the φ input node to the input node of the buffer inverter I is considered to be linear, and the response of the output voltage V to the V _DD input (high level voltage of the clock input φ) is as follows. t: time R = sum of resistance R ₁ and on-resistance of CMOS inverter I ₁ (= 30kΩ) Since buffer inverter I is considered to be inverted when output voltage V reaches 1/2V _DD , -t/CR=ln1/2 t=CR・ln1/2≒1×10 ^-12 ×3×10 ⁴ ×0.7≒20ns.

Further, as the delay means, as in the clock circuit shown in FIG. 22 or FIG. 23, a CMOC inverter _I1 of three or more odd stages is used to generate an output from the φ input, and the φ input is directly converted to φ. It may also be taken out as output. in this case,
If the delay amount due to one stage of CMOS inverter is 10 ns, the phase difference between the clock output pair (φ) will be 30 ns or 50 ns.Furthermore, as in the clock circuit shown in FIG.
The output system and the output system each have one stage or multiple stages (second
A buffer circuit B consisting of buffer inverters I (two stages in the case of FIG. 5) may be inserted. In this case, it goes without saying that the difference in the number of inverter stages between the φ output system and the output system must be an odd number in order to obtain the clock output pair φ.

〔Effect of the invention〕

As described above, according to the SC integrator of the present invention,
Even if there is a delay due to the CR of the wiring from the clock circuit to the gate of each transistor in the SC circuit,
Since the clock circuit's clock output pair φ is made to have a phase difference greater than the delay amount, the SC
Each transistor in the circuit can be operated in a predetermined order and the offset voltage can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a switched capacitor integrator, and FIGS. 2a and 2b are circuit diagrams showing conventional examples of the clock circuit for the integrator shown in FIG.
FIG. 3 is a circuit diagram shown to explain the detailed operation of the integrator shown in FIG. 1, FIGS. 4 and 5 are timing diagrams showing different operation examples from FIG.
FIG. 7 is a circuit diagram showing the simulation circuit when the simulation result of FIG. 6 is obtained, and FIGS.・Circuit diagrams showing different embodiments of clock circuits used in capacitor integrators. 1... Switched capacitor circuit, 2... Operational amplifier, 3... Clock circuit, N ₁ , N ₂ , P ₁ ,
P ₂ ...MOS transistor, I, I ₁ , I ₂ ... Inverter, C ₁ , C ₂ ... Capacity, R ₁ , R ₂ ... Resistor, B ...
Batsuhua circuit.

Claims (1)

[Claims] 1. A switched capacitor circuit is connected between the input node and the inverting input terminal of the operational amplifier, an integrating capacitor is connected between the output terminal and the inverting input terminal of the operational amplifier, and the above-mentioned A switched capacitor circuit consists of two clocks driven by the first phase clock pair.
In a switched capacitor integrator consisting of two CMOS switches and one capacitor driven by a CMOS switch and a second-phase clock pair, a clock circuit that supplies a clock output pair to each of the CMOS switches is configured as follows. In CMOS switch, P channel transistor is on, N
The operating order is such that the N-channel transistor is on, the P-channel transistor is off, and the N-channel transistor is off, or the operating order is that the N-channel transistor is on, the P-channel transistor is on, the N-channel transistor is off, and the P-channel transistor is off. , a switched capacitor integrator characterized in that a phase difference relationship between a pair of clock outputs is set in consideration of a delay due to wiring between a clock circuit and a switched capacitor circuit. 2. The clock circuit is characterized in that the phase difference between the clock output pairs is set by a delay means consisting of a capacitor, a combination of a capacitor and a resistor, a combination of a capacitor, a resistor, and a MOS inverter, or a plurality of stages of MOS inverters. A switched capacitor integrator according to claim 1.