JPS6354012A - Difference circuit using switched capacitor - Google Patents

Abstract

PURPOSE:To output a difference voltage at one and same time continuously with simple constitution by holding the difference voltage via the 1st and 2nd capacitors controlled by clocks whose phases are deviated to each other and not overlapped. CONSTITUTION:With a clock phi1 at an H level, switches 3, 4 are turned on and the 1st capacitor 11 is charged in response to the difference of input voltages V1, V2 at one and same time. When the clock phi1 goes to an L level, the switches 3, 4 are turned off, a difference voltage is sampled by a capacitor C1, and when the clock phi2 not overlapped with the clock phi1 goes to H, switches 5, 6 are turned on and one terminal of the capacitor C1 is connected to a zero level power supply 16. Then the difference voltage with respect to the zero level of the capacitor C1 charges the 2nd capacitor C2 whose one terminal is connected to ground in terms of AC via the switch 5, the clock phi2 goes to L and held even after the switch 5 is turned off and the difference voltage is extracted continuously from an output terminal 18 via a buffer amplifier 17 with simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a switched capacitor circuit, and more particularly to a switched capacitor difference circuit suitable for a difference circuit that outputs a signal proportional to the difference between two input voltages.

[Conventional technology]

Conventionally, as a difference circuit using a switched capacitor circuit that outputs a voltage proportional to the difference between two input voltages, the i.
IEEE Transactions on Scientists and Systems (1978), page 492 and Figure 3 therein (IEEE, Trans.

C1rcuits and 5ysteo+s, CA
S 25, 7 (1978) pp492. Fig,
3).

[Problem that the invention seeks to solve]

However, the above-mentioned difference circuit outputs a difference between two voltages shifted in time, rather than a difference between two input voltages at the same point in time, since the output voltage returns to a zero level in a clock cycle and cannot be taken out continuously. Another disadvantage is that it requires a high-gain operational amplifier, which increases the circuit scale.

Therefore, an object of the present invention is to provide a difference circuit that can take out an output voltage continuously, can output the difference between two input voltages at the same time, and can be configured only with a switch and a capacitor, or a buffer amplifier and a switch. .

[Means for solving problems]

The present invention achieves the above object by providing a switch that applies two input voltages to both ends of a first capacitor using a first clock pulse, and a second clock pulse whose phase is shifted so as not to overlap with the first clock pulse. Achieved by providing a switch that connects one terminal of the first capacitor to a voltage source defined as a zero level by a clock pulse, and a switch that connects the other terminal to a second capacitor that is AC grounded. are doing.

[Effect]

In the difference circuit of the present invention, the two input voltages are separated from the first capacitor by the same clock (first clock), so the difference voltage between the two input voltages at the same time is sampled on the first capacitor. The difference voltage is charged to the second capacitor by the second clock and the second
Since the second capacitor holds the output even when there is no clock, the output can be obtained continuously.As an amplifier, if the load consumes current, a buffer amplifier is only needed to supply current. be.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure shows the configuration of one embodiment, and the switch in FIG. 1 corresponds to the waveforms 201 and 202 of the time chart in FIG.
The period during which the switch is on (
In FIG. 2, the high level period) is controlled by either clock pulses φ1 or φ2 that do not overlap.

In FIG. 1, the input terminal 1 has an input voltage v on the addition side.
1 is applied, and input voltage v2 on the subtraction side is applied to input terminal 2. Input terminal 1 and input terminal 2 are
They are respectively connected to different terminals of a first capacitor (a-capacitor, capacitance C1) 11 by switches 3 and 4 controlled by a clock pulse φ1 (hereinafter abbreviated as φ). (The switch is a field effect transistor, for example, similar to a common switched capacitor circuit.

It can be configured with NMOS transistors, PMOS transistors, CMOS transistors, etc. of MO9 integrated circuits. )
The terminal of the capacitor 11 on the switch 3 side is.

The second capacitor (
It is connected to one terminal of a holding capacitor (capacitor Cz) 12 and the input of a buffer amplifier 17.

The other terminal of the holding capacitor 12 is AC grounded. Also, for the holding capacitor 12.

The input capacitance of the buffer amplifier 17 itself can also be used. The buffer amplifier 17 is an amplifier with a very large input resistance, and its output 18 is the output of the difference circuit. If the input resistance of the load of the difference circuit is large enough.

It is also possible to omit the buffer amplifier 17 and use the terminal of the holding capacitor 12 as an output. For example, as shown in FIG. 1, the buffer amplifier 17 has a gate as an input, a drain as a power source, and a source as a current source 2o.
A source follower consisting of a field effect transistor 19 connected to and used as an output can be used. The terminal of the sampling capacitor 11 on the switch 4 side is connected to a power supply (zero level) 16 with a voltage defined as zero level by a switch LO controlled by φ2.

explained above. Switches 3 to 6 and capacitors 11 and 12
The difference circuit is basically configured as follows. That is,
While φl is at a high level, the sampling capacitor 11 is charged with the difference between the two input voltages by switches 3 and 4, and is sampled at the moment when φl changes to a low level. Sampling is performed with the same clock φ1 for the two inputs, so
The difference between the two input voltages at the same time will be sampled. Next, when φ2 becomes high level, the differential voltage charged in the sampling capacitor 11 is charged into the holding capacitor 12 by the switch 5 with the zero level 16 as a reference by the switch 6. The voltage (v3) charged in the holding capacitor 12 is
Even when φ2 becomes low level and the switch φ2 is turned off, it is held, and a differential voltage can be continuously obtained from the output terminal 8. Note that the differential voltage charged in the sampling capacitor 11 and the holding capacitor 12 due to the connection between the latter is attenuated due to the loading effect of the latter.

If the input voltage is constant, a large number of repetitions of the clock pulse will result in a voltage at the terminals of the holding capacitor 12 that is equal to the differential voltage of the input voltages.

The parts of FIG. 1 not explained above are switches 3 and 4.
This is to eliminate errors caused by the parasitic capacitor (capacitance Cpz) 13 with respect to the ground of the wiring connecting these and the capacitor 11.

That is, the capacitance approximately equal to the parasitic capacitor 13 is set to cp
One terminal of the cancellation capacitor 14 having x is connected to the input terminal 2 by a switch 7 controlled by φ2, and to the zero level 1G by a switch 9 controlled by φ2. The other terminal of the capacitor 14 is connected to the zero level 16 by a switch 8 controlled by φ2, and to the holding capacitor 12 by a switch 10 controlled by φ2. Switches 8 and 1 are connected to the terminals of the capacitor 14 on the switch 10 and 8 sides.
0 and a parasitic capacitor (capacitance Cpδ) 15 with respect to the ground of the wiring connecting them and the capacitor 14.

Here, regarding the whole of FIG. 1, the voltage v at input terminals 1 and 2
1, VZ, and the voltage v8 of the holding capacitor will be analyzed using 2 conversion. In this analysis, it is assumed that the AC ground is equal to the voltage of the voltage source 16, which is defined as zero level (the DC voltage at the non-switched terminal of the capacitor is
(as it does not affect other voltages). In order to explain this analysis, in FIG. 1, the charge accumulated in the electrode of the capacitor connected to the holding capacitor 12 when φ2 is at a high level is shown as the Q of each capacitor.

The total sum QT of the above charges including the charge of the holding capacitor 12
is, QT=C1(z-"Vt-Z-IV2)+Czz-"V
a+ Cps z-”V knee Cps z-”Vz+
Cps z −' 0=Ct (z−'Vt−z−”V
z)+Czz-'Va+Cpzz-"Vt-Cpxz-
'Vz - (1) 0th order φ2 becomes high level, and even if capacitors 11, 13, 14.15 are all connected to holding capacitor 12, the total charge remains QT, so φ2 becomes high level. The voltage Vδ of the holding capacitor when the sum of the connected capacitances is (C1+C
z+Cpx+Cpx+Cps), so (C1+C
z+Cpx+Cpx+Cps)Vs=Qding -(2)
That is, (C10C2+CP!+CPZ+CP3)v21=Ct
(z-'Vz-2-'V2)+Czz-'Va 10PI
Z-"Vl-Cpzz-"Vx. From this, ...(3) Here, Cpz=Cpz, that is, the parasitic capacitor 13
If the capacitance of the canceling capacitor 14 is made equal to the capacitance of the canceling capacitor 14,
(3) Equation is.

Therefore, the voltage of the holding capacitor 12 is the voltage of the input terminals 1 and 2.
It can be seen that it is proportional to the difference in voltage. Therefore, a voltage proportional to the difference between the voltages of input terminals 1 and 2 is also obtained at output terminal 8. If the voltages at input terminals 1 and 2 are DC, the ratio of Va and (Vz Vz) is.

Assuming z-1 to be 1, it follows from (4) that the parasitic capacitors 14 and 1 due to switches and wiring
If the capacitance of the sampling capacitor 11 is made sufficiently smaller than the capacitance of the sampling capacitor 11, the ratio of v3 and (Vl-Vl) can be made approximately 1. On the other hand, when the difference in voltage between input terminals 1 and 2 is inverted every clock cycle, z-1 is set to -1. In this case, it can be seen that the absolute value of the ratio is smaller than (6) (the negative sign in equation (7) indicates a signal delay due to switching and does not indicate signal reversal). shows that this difference circuit has a frequency characteristic in which the gain decreases in the high range. This high frequency drop can be reduced by making the capacitance C2 of the holding capacitor 12 smaller than the capacitance C1 of the sampling capacitor 11 from equation (7). Usually, by reducing Cz within a range that does not interfere with signal retention, this reduction in high frequencies can be reduced to a value that does not cause any problems in practice.

In addition, the cancellation capacitor 14 and the switch 7.8゜9.10
The relationship between v8 and Vl when not using Vl is as follows in equation (3) when Cpx and Cps are set to zero, and the Vl component is added to Va in addition to the difference signal.

However, by making the capacitance Cs of the sampling capacitor 11 sufficiently larger than the capacitance CPI of the parasitic capacitor 13, it can be put to practical use in many cases.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to configure a difference circuit that can continuously obtain an output proportional to the difference between two input voltages at the same time, using only switches and capacitors, or only them and a buffer amplifier. It is effective in improving the performance of differential circuits and reducing circuit scale.

The difference circuit improved by the present invention is useful, for example, for improving the performance and cost of a comb-shaped filter.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, and FIG.
3 is a time chart for explaining the waveform of a clock used in the embodiment shown in the figure. 1.2...Input terminal, 3-10...Switch, 11
・15...Capacitor, 16...Zero level power supply, 1
7. Buffer amplifier, 18... Output terminal, 19... Field effect 1 transistor, 20... Current source, 201, 202
... = Lock pulse waveform.

Claims (1)

[Claims] 1. The two input voltages are set to the first by the first clock pulse.
a switch applied to both ends of the capacitor, and a voltage power supply that defines one terminal of the first capacitor as a zero level by a second clock pulse whose phase is shifted so as not to overlap with the first clock pulse; 1. A switched capacitor difference circuit comprising: a switch connected to a second capacitor; and a switch whose other terminal is connected to a second capacitor grounded in an alternating current manner. 2. The first clock pulse sets the two input voltages to the first
a switch applied to both ends of the capacitor, and a voltage power supply that defines one terminal of the first capacitor as a zero level by a second clock pulse whose phase is shifted so as not to overlap with the first clock pulse; and a switch that connects the other terminal to a second capacitor that is AC grounded, the parasitic capacitor is connected to the ground connected to the terminal of the first capacitor that is connected to the second capacitor. A third capacitor whose capacitance is approximated is provided, and the first clock pulse causes one terminal of the third capacitor to be connected to one terminal of the first capacitor which is not connected to the second capacitor of the two input voltages. A switch is provided to connect the voltage connected to the terminal of the third capacitor and a switch to connect the other terminal to the voltage of the zero level power source, and a second clock pulse connects one terminal of the third capacitor to the voltage of the zero level power source. 1. A switched capacitor difference circuit comprising a switch for connecting to a power source and a switch for connecting the other terminal to the second capacitor.