JP3037502B2 - Switched capacitor sample and hold delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to communication, signal processing, measurement,
The present invention relates to a switched capacitor sample and hold delay circuit used in a control system.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration of a conventional switched capacitor (hereinafter abbreviated as SC) sample and hold delay circuit, and FIG. 4 shows switch driving clocks φ ₁ , φ of this circuit.
₂ shows a timing chart, a waveform of the input voltage Vi, and a waveform of the output voltage Vo. In FIG. 4, t is time, Ts is a sampling period, and n is an arbitrary integer. 3, 101 is an input terminal to which an input signal is applied, 102 and 103 the clock phi ₁ shown in FIG. 4 is turned at the time of the on switch, 104 denotes an input voltage Vi and output voltage through the switch 102, 103 capacitance C of the capacitor for charging a voltage Vi-Vo of the difference between Vo, 105, 106 is a clock phi ₂ becomes conductive at the time of on, the electric charge C, which has been charged in the capacitor 104 (Vi-Vo) Switch for discharging, 107
Is an operational amplifier for taking the discharge charge from the capacitor 104 into the integrating capacitor 108 and generating the final output voltage Vo. 108 takes in the discharge voltage C (Vi−Vo) from the capacitor 104 when the clock φ ₂ is on. A capacitor 109 for canceling the output voltage Vo that has been charged so far and newly charging the input voltage Vi one-half sample period earlier, and an output terminal 109 for detecting the output voltage of the operational amplifier 107.

Next, the operation of the above conventional example will be described.
In FIG. 4, time t = (n) when clock φ ₁ is on
-1) In Ts, the capacitor 104 shown in FIG.
The charge of (Vi (n−1) −Vo (n−1)) is charged. Next time t = {n- (1 clock phi ₂ is on
/ 2) At {Ts, the electric charge of the capacitor 104 is discharged to the capacitor 108, and the electric charge of the capacitor 108 is CVo {n- (1/2)} = CVo (n-1) + C @ Vi (n-1)- Vo (n-1) = CVi (n-1) (1), and the output voltage Vo {n- (1/2)} is Vo {n- (1/2)} = Vi (n- 1) (2) As a result, a delay of 1/2 sample period (Ts / 2) is obtained as shown in FIG.
_Since the charge does not flow into the capacitor 108 during periods other than the period when ₂ is on, the output voltage Vo is held.

As described above, even in the above-described conventional SC sample-hold delay circuit, a sample-hold delay of 1/2 sample period can be obtained, and a long time delay can be realized by cascading this circuit.

[0005]

However, in the above-mentioned conventional SC sample-and-hold delay circuit, only a delay of 1/2 sample period can be obtained. There is a problem that the number of stages to be used increases, the number of operational amplifiers used increases, and the circuit scale and power consumption increase.

The present invention is to solve such a conventional problem. In the configuration using one operational amplifier, it is possible to obtain a delay of one sample period which is twice as long as that of the conventional one, and to provide a long time. It is an object of the present invention to provide an excellent SC sample and hold delay circuit that can reduce the number of stages required for cascade connection when realizing a delay and reduce the circuit scale and power consumption.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides first and second clocks controlled by first and second clocks which are equal to a sampling frequency and do not overlap each other.
Are turned on at the time when the clocks are turned on.
And a second switch, and a voltage Vi of a difference between the input voltage Vi and the output voltage Vo through the first and second switches.
-A first capacitor having a capacitance value of 2C to be charged with Vo;
A second capacitor having a capacitance value of 2C for discharging a charged charge to an integration capacitor of an operational amplifier to be described later through a third switch which is turned on when the first clock is turned on;
When the second clock is turned on, the second clock is turned on, and a series connection state of a ground point, a first capacitor, a second capacitor, and a ground point is formed, and ± C (Vi is applied to each of the first and second capacitors. -Vo), and the discharge charge C (V) from the second capacitor when the first clock is turned on again.
i-Vo), cancels the output voltage Vo of the operational amplifier that has been charged up to now, and newly integrates a third capacitor having a capacitance value C as an integrating capacitor for charging the input voltage Vi one sample period earlier. And an operational amplifier for outputting the voltage charged in the third capacitor.

[0008]

Therefore, according to the present invention, the voltage of the difference between the input voltage Vi and the output voltage Vo is taken into the first capacitor when the first clock is on, and this voltage is taken when the second clock is on. The electric charge charged in the first capacitor is
Rather than discharging to the integrating capacitor relating to the output as in the prior art, at this point, the signal is once transferred to the second capacitor, and again when the first clock is turned on, the second capacitor is charged. By transferring the charge to the integrating capacitor relating to the output, the input signal can be taken and the signal can be output after one sample period, and the sample and hold delay of one sample period which is twice the conventional delay amount. In order to realize a long delay, a desired amount of delay is realized by cascading a smaller number of stages than cascading conventional sample-and-hold delay circuits,
This has the effect of reducing the circuit scale and power consumption.

[0009]

FIG. 1 shows the configuration of an SC sample and hold delay circuit according to an embodiment of the present invention. FIG. 2 shows the first and second switch driving clocks φ _{1 which} are equal to the sampling frequency and do not overlap each other in this circuit. and a timing chart of phi ₂ shows the waveform of the waveform and the output voltage Vo of the input voltage Vi. However, in FIG. 2, t is time, Ts is a sampling period, and n is an arbitrary integer.
In FIG. 1, reference numeral 1 denotes an input terminal to which an input signal is applied;
And 3 the first and second switches where the first clock phi ₁ shown in FIG. 2 is turned at the time of ON, the 4 first
And a capacitance value 2 for charging a voltage Vi-Vo of a difference between the input voltage Vi and the output voltage Vo through the second switches 2 and 3.
The first capacitor 5 of C is a second capacitor of 2C having a capacitance value of 2C which discharges the charge charged through the third switch 6 which becomes conductive when the first clock φ ₁ is turned on and becomes 0. , 7 and 8 become conductive when the second clock φ ₂ is turned on, and the ground point, the first capacitor 4,
A series connection state in the form of a second capacitor 5 and a ground point is created, and ± 1
C (Vi-Vo) fourth and fifth switches for charging the charge of, 9 again first clock phi ₁ is discharged electric charge from the second capacitor 5 at the time of the on-C (Vi-V
o) and the operational amplifier 10 that has been charged up to now
The third capacitor 10 having a capacitance value C, which is an integrating capacitor for charging the input voltage Vi one sample period earlier, and the output voltage Vo of the third capacitor 9 is output. Is an output terminal for detecting the output voltage Vo of the operational amplifier 10.

Next, the operation of the above embodiment will be described based on FIG. 1 and with reference to FIG. In FIG. 2, time t = (n−1) Ts when the first clock φ ₁ is on.
Then, the first capacitor 4 shown in FIG.
(N−1) −Vo (n−1)} is charged.
Further, the charge of the second capacitor 5 is discharged to be 0.
Further, the third capacitor 9 is charged with an electric charge of CVo (n-1). Then at time t = {n- (1/2)} Ts second clock phi ₂ is turned on, the first and second capacitors 4 and 5 become series connection of the two capacitors 4, 5 Charge transfer occurs between the first capacitor 4 and C ｛Vi (n−1) −Vo (n
−1)}, and the second capacitor 5 is charged with −C {Vi (n−1) −Vo (n−1)}. On the other hand, since no charge flows into the third capacitor 9 at this time, CVo (n-1) is held as it is, and Vo (n-1) is held as the output voltage. Then, at time t = nTs when the first clock φ ₁ is turned on again, the charge of the second capacitor 5 is discharged to the third capacitor 9, and the charge of the third capacitor 9 is CVo (n) = CVo (n-1) + C {Vi (n-1) -Vo (n-1)} = CVi (n-1) (3), and the output voltage Vo (n) is Vo (n) = Vi (n-1) (4) As a result, as shown in FIG. 2, a delay of one sample period (Ts) is obtained. As mentioned above, the first
In other periods the clock phi ₁ is on, there is no inflow of charges into the third capacitor 9, the output voltage Vo is held.

As described above, according to the above-described embodiment, since the transfer of electric charge from the input to the output is performed sequentially using the two capacitors 4 and 5 unlike the related art, the amount of delay is twice that of the related art. Is obtained for one sample period. As a result, when a long-time delay is realized, a desired number of delays can be obtained by cascading a smaller number of stages than in the conventional sample-and-hold circuit, and the circuit scale and power consumption can be reduced. It has the effect of.

[0012]

As is apparent from the above embodiment, the present invention realizes a delay of one sample period which is twice the delay amount of the conventional SC sample hold delay circuit even with a configuration using one operational amplifier. As a result, even when a long delay is realized, a desired amount of delay can be obtained only by cascading a smaller number of stages than the conventional SC sample-and-hold delay circuit, and the circuit scale and the power consumption can be reduced. This has the effect that it can be achieved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a switched-capacitor sample-hold delay circuit according to one embodiment of the present invention.

FIG. 2 is a timing chart of a switch driving clock and a waveform diagram of an input voltage and an output voltage of the circuit.

FIG. 3 is a circuit diagram of a conventional switched capacitor sample and hold delay circuit.

FIG. 4 is a timing chart of a switch driving clock and a waveform diagram of an input voltage and an output voltage of the circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input terminal 2 1st switch 3 2nd switch 4 1st capacitor 5 2nd capacitor 6 3rd switch 7 4th switch 8 5th switch 9 3rd capacitor 10 Operational amplifier 11 Output terminal

Claims (1)

(57) [Claims] A first clock controlled by a first and a second clock which are equal to a sampling frequency and do not overlap each other;
Are turned on at the time when the clocks are turned on.
And a second switch, and a voltage Vi of a difference between the input voltage Vi and the output voltage Vo through the first and second switches.
-A first capacitor having a capacitance value of 2C to be charged with Vo;
A second capacitor having a capacitance value of 2C for discharging a charged charge to an integration capacitor of an operational amplifier to be described later through a third switch which is turned on when the first clock is turned on;
When the second clock is turned on, the second clock is turned on, and a series connection state is formed in the form of a ground point, a first capacitor, a second capacitor, and a ground point, and ± C (Vi -Vo), and the discharge charge C (V) from the second capacitor when the first clock is turned on again.
i-Vo), cancels the output voltage Vo of the operational amplifier which has been charged up to now, and newly integrates a third capacitor having a capacitance value C which is an integrating capacitor for charging the input voltage Vi one sample period earlier. And an operational amplifier for outputting a voltage charged in the third capacitor.