JPH03250911A - Switched capacitor integrator - Google Patents

Abstract

PURPOSE:To reduce noise to the utmost by forming a switched capacitor integrator of a switch, a capacitor and a differential amplifier. CONSTITUTION:When an input signal VIN is inputted to an input terminal 1 and a clock phi1 reaches a high level and a clock phi2 reaches a low level, switches 4, 6 are turned on, switches 5, 7 are turned off and a changer (VIN.C12) is stored in a capacitor 12, and both electrodes of a capacitor 13 are connected via ground 17. When the clock phi1 reaches a low level and the clock phi2 reaches a high level, the charges (VIN.C12) stored in the capacitor 12 is integrated by a capacitor 14 and a charger (VIN.C13) is stored in one electrode of the capacitor 13 and a charge (-VIN.C13) appears in the other electrode and the charge is integrated by a capacitor 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a switched capacitor integrator having the function of converting an unbalanced signal into a balanced signal.

[Background Art] A switched capacitor integrator is an essential circuit for realizing a circuit such as a switched capacitor filter.

Furthermore, fully differential switched capacitor circuits are important circuits for realizing various circuits with low noise. However, when implementing a large-scale switched capacitor circuit, if all circuits are made into fully differential circuits, the circuit scale will increase. For this reason, only the portion with high noise sensitivity may be formed with a fully differential circuit. In this case, a circuit is required to convert the unbalanced signal into a balanced signal.

FIG. 5(a) is a circuit diagram showing a conventional switched capacitor integrator equipped with an unbalanced/balanced conversion circuit.

Input terminal 71 is connected to one electrode of capacitor 82 via switch 74. The other electrode of this capacitor 82 is connected to the fully differential operational amplifier 8 via a switch 77.
It is connected to the non-inverting input terminal of 6. Further, a switch 7 is connected between the one electrode of the capacitor 82 and the ground 88.
5 is inserted, and a switch 76 is inserted between the other electrode of the capacitor 82 and ground 88.

The input terminal 71 is also connected to the input end of an inverting amplifier 87, and the output end of the inverting amplifier 87 is connected to one electrode of a capacitor 83 via a switch 78. The other electrode of this capacitor 83 is connected to the inverting input terminal of a fully differential operational amplifier 86 via a switch 81. Further, a switch 79 is interposed between the one electrode of the capacitor 83 and the ground 88, and a switch 80 is interposed between the other electrode of the capacitor 83 and the ground 88.

The inverting output terminal of the fully differential operational amplifier 86 is connected to the output terminal 72, and the non-inverting output terminal is connected to the output terminal 73. Further, a capacitor 84 is inserted between the non-inverting input terminal and the inverting output terminal of this fully differential operational amplifier 86, and a capacitor 85 is inserted between the inverting input terminal and the non-inverting output terminal. has been done.

Note that the gain of the inverting amplifier 87 is 1. In general,
This inverting amplifier 87 also includes a switched capacitor circuit.

In addition, the switches 74, 76, 78 and 80 are connected to each other in FIG.
b) is driven by the clock φ, shown in FIG.
It turns on when the level is high and turns off when the level is low. Furthermore, switches 75, 77, 79 and 81 are
It is driven by a clock φ2 shown in FIG. 5(b), and is turned on when this clock φ2 is at a high level and turned off when it is at a low level. And these clocks φ1 and φ
2 are supplied to this circuit in mutually different phases.

FIG. 6 is a timing chart showing the operation of the conventional switched capacitor integrator mentioned above.

However, it is assumed that the input signal VIN has been sampled in advance.

First, the input signal V□8 is input to the input terminal 71. This input signal VIN is inverted by an inverting amplifier 87, and an inverting input signal VIN- is output from the inverting amplifier 87.

Next, when the clock φ□ goes high and the clock φ2 goes low, the switches 74.7B, 78 and 80
is turned on and switches 75, 77, 79 and 81 are turned off. Then, the input signal VIN is capacitor 8
2, and the inverted input signal VIN- is sampled by capacitor 83.

Then, clock φ1 goes low and clock φ2
is at a high level, switches 74, 78, 78 and 8
0 is turned off and switches 75, 77, 79 and 81 are turned on. Then, the input signal v! sampled by the capacitor 82! N is integrated by the capacitor 84, and the inverted input signal V, - sampled by the capacitor 83 is integrated by the capacitor 85.

The output terminal 72 receives a non-inverted output signal V. UT+ is output, and the output terminal 73 receives an inverted output signal V. UA is output.

By repeating such operations in synchronization with the clocks φ and φ2, the input signal VIN is continuously integrated. In this case, the differential output of the fully differential operational amplifier 88 is the non-inverted output signal V. The difference between U7 and the inverted output signal VOUT-, that is, (V out+) - (V out-). As a result, common-mode noises such as loop-around from the power supply are mutually canceled out. Therefore, this switched capacitor integrator inherently has a very low noise level.

[Problems to be Solved by the Invention] However, the conventional switched capacitor integrator described above has an operational amplifier (inverting amplifier 87) between the input terminal 1 and the input terminal of the fully differential operational amplifier 860. Therefore, there is a drawback that the noise generated in this operational amplifier destroys the symmetry of the signal, and the noise is transmitted to the differential output of the fully differential operational amplifier.

FIG. 7 is a timing chart showing the operation of the conventional switched capacitor integrator when the output of the inverting amplifier 87 contains noise. However, the solid line shows the state where there is no noise, and the broken line shows the state where noise is superimposed on the output of the inverting amplifier 87. When noise is superimposed on the output of the inverting amplifier 87, the capacitor 83 samples the inverted input signal VXN- on which the noise is superimposed, and therefore the inverted output signal VoUy- of the fully differential operational amplifier 86 contains aliasing noise. occurs. Therefore, it cannot be said that the conventional switched capacitor integrator is sufficiently effective in performing fully differential amplification.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a switched capacitor integrator with lower noise than conventional ones.

[Means for Solving the Problems] A switched capacitor integrator according to the present invention is a switched capacitor integrator driven by a first clock and a second clock having mutually different phases. , a second capacitor, a fully differential amplifier,
a first switch inserted between the first electrode of the first capacitor and a signal input terminal; and a second switch inserted between the first electrode of the first capacitor and a signal ground.
a third switch inserted between the second electrode of the first capacitor and the signal ground; and a non-inverting switch of the second electrode of the first capacitor and the fully differential amplifier. a fourth switch inserted between the input end;
a fifth switch inserted between the first electrode of the second capacitor and the signal input terminal; and a fifth switch inserted between the first electrode of the second capacitor and the signal ground. a sixth switch, a seventh switch inserted between the second electrode of the second capacitor and the signal ground, and a seventh switch inserted between the second electrode of the second capacitor and the fully differential amplifier; an eighth switch inserted between the inverting input terminal and the third capacitor interposed between the non-inverting input terminal and the inverting output terminal of the fully differential amplifier; a fourth capacitor interposed between the inverting input terminal and the non-inverting output terminal of the amplifier, the first switch;
the third switch, the sixth switch and the seventh switch
The switch is controlled by the first clock, and the second switch, the fourth switch, the fifth switch, and the eighth switch are controlled by the second clock. .

[Function] In the present invention, first, when the first clock becomes high level, the first switch inserted between the signal input terminal and the first electrode of the first capacitor and the first capacitor A third electrode inserted between the second electrode and the signal ground
switch is turned on. This causes the input signal to be
sampled by the capacitor. At this time, the fifth switch inserted between the signal input terminal and the first electrode of the second capacitor is off, and the fifth switch inserted between the electrode of the second capacitor and the signal ground is turned off. Both the sixth and seventh switches are turned on. That is, the first and second electrodes of the second capacitor are electrically connected to each other via the signal ground, and the potentials of the first and second electrodes are the same.

Then, when the first clock goes low and the second clock goes high, the first and third switches are turned off and the second and fourth switches are turned on,
The signal sampled on the first capacitor is transferred to the third capacitor.
is integrated by the capacitor. As a result, a non-inverted output signal obtained by integrating the input signal is outputted to the inverted output terminal of the fully differential amplifier.

Meanwhile, at the same time, a fifth switch is inserted between the signal input terminal and the first electrode of the second capacitor, and a fifth switch is inserted between the second electrode of the second capacitor and the fully differential amplifier. The eighth switch inserted between the second capacitor and the signal ground is turned on, and the sixth switch and seventh switch inserted between the second capacitor and the signal ground are turned off. Therefore, charge is accumulated in the first electrode of the second capacitor due to the input signal, and a charge having the opposite polarity to this charge appears at the second electrode of the second capacitor. This charge is then integrated by the fourth capacitor. As a result, an inverted output signal obtained by integrating the input signal is outputted to the non-inverted output terminal of the fully differential amplifier.

The switched capacitor integrator according to the invention operates in this manner. In this case, since there is no operational amplifier between the signal input terminal and the input terminal of the fully differential amplifier, the two signals input to the non-inverting input terminal and the inverting input terminal of the fully differential amplifier Excellent symmetry. This significantly reduces the noise contained in the fully differentially amplified signal.

[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1(a) is a circuit diagram showing a switched capacitor integrator according to a first embodiment of the present invention.

A switch 4 is inserted between the input terminal 1 and one electrode of the capacitor 12. And this capacitor 1
The other electrode of 2 is connected to a non-inverting input terminal of a fully differential operational amplifier 16 via a switch 7. Further, a switch 5 is inserted between the one electrode of the capacitor 12 and the ground 17, and a switch 5 is inserted between the other electrode and the ground 17.
A switch e is inserted between the switch 7 and the switch 7.

Furthermore, a switch 8 is inserted between the input terminal 1 and one electrode of the capacitor 13, and the other electrode of the capacitor 13 is connected to the fully differential amplifier 1θ via the switch 11.
is connected to the inverting input terminal of A switch 9 is connected between the one electrode of the capacitor 13 and the ground 17, and a switch 10 is connected between the other electrode and the ground 17.

Furthermore, a capacitor 14 is connected between the non-inverting input terminal and the inverting output terminal of the fully differential amplifier 16, and a capacitor 15 is connected between the inverting input terminal and the non-inverting output terminal.
is inserted. The inverting output terminal of the fully differential operational amplifier 1θ is connected to the a-power terminal 2, and the non-inverting output terminal is connected to the output terminal 3.

The switches 4, 8, 9 and 10 are driven by the clock φ1 shown in FIG. 1(b) as in the conventional case.
Turns on when 1 is high level.

Further, the switches 5, 7, 8 and 11 are driven by the clock φ2, and are turned on when the clock φ2 is at a high level.

Next, the operation of the switched capacitor integrator according to this embodiment will be explained. However, in the following explanation, each capacitance value of capacitors 12, 13, 14 and 15 is referred to as C1.
2, C13, c, 4 and c, .

FIG. 2 is a timing chart showing the operation of the switched capacitor integrator according to this embodiment.

It is assumed that the input signal has been sampled in advance.

First, input signal VIN is input to input terminal 1, clock φ becomes high level, and clock φ2 becomes low level, switches 4 and 8 are turned on, switches 5 and 7 are turned off, and the capacitor is turned off. 12 (VIN”C-2)
charge is accumulated. On the other hand, since switches 9 and 10 are also turned on, both electrodes of capacitor 13 are connected via ground 17. That is, the charge on the capacitor 13 is cleared.

Next, when the clock φ becomes a low level and the clock φ2 becomes a high level, switches 4 and 6 are turned off and switches 5 and 7 are turned on, so that the charge accumulated in the capacitor 12 (VXN C) is capacitor 14
It is integrated by On the other hand, switches 9 and 10 are turned off and switches 8 and 11 are turned on, so a charge of (VIN@013) is accumulated in one electrode of the capacitor 13, and at the same time, the charge of (- Vxs・Cyu.

) appears, and this charge is integrated by the capacitor 15.

As a result, the input signal VIN (C14
/C□2) non-inverted output signal V O
UT+ is output, and input signal VIN is output to output terminal 3 (
- the inverted output signal V integrated with a gain of CII5/G1G). UT- is output.

In this embodiment, since there is no operational amplifier between the input terminal 1 and the non-inverting input terminal and the inverting input terminal of the fully differential operational amplifier 16, the non-inverting input terminal and the inverting input terminal of the fully differential operational amplifier 16 are not provided. The symmetry of the signals input at the ends is extremely good. Therefore, the output signal has very little noise.

Note that the output signal V in FIG. uTth and V. UT- is the capacitance value CI2 of capacitors 12, 13, 14 and 15,
This is a waveform when C13, C14, and C15 are all equal.

Further, in this embodiment, the switches 4 to 11 are all constituted by N-channel MO8) transistors. Therefore, the clocks φ and φ2 are input to the gates of these MOS transistors, and both ends of each switch correspond to the source and drain of the transistor, respectively. Thereby, the circuit of this embodiment can be realized as an MO8 integrated circuit on a semiconductor substrate.

FIG. 3(a) is a circuit diagram showing a switched capacitor integrator according to a second embodiment of the present invention.

In FIG. 3(a), symbols N1 to N8 all indicate N-channel MOS transistors, and symbols P1 to P8 indicate P-channel MOS transistors.

The difference between this embodiment and the first embodiment is that the switch is 0M
The reason is that it is composed of O8.

For example, 1 by 0MO8 consisting of N-channel MOS transistor N1 [and P-channel MO8] transistor P1.
This switch corresponds to switch 4 in FIG. 1(a). Similarly, 0MO8 consisting of transistors N2 and P2, 0MO8 consisting of transistors N3 and P3, 0MO8 consisting of transistors N4 and P4,) 0MO8 consisting of transistors N5 and P5, 1) 0MO8 consisting of transistors N6 and P6,
081) CMO8i consisting of transistors N7 and Pl and 0MO8 consisting of transistors N8 and P8 are switches 5.6.7.8.8.10 and 1 of FIG. 1(a), respectively.
It corresponds to 1. Also, capacitor 32.33.34
and 35 are the capacitors 12, 13, . . . in FIG. 1(a), respectively.
14 and 15, and the fully differential operational amplifier 36 corresponds to the fully differential operational amplifier 16 in FIG. 1(a). Furthermore,
The input terminal 21 and the output terminals 22 and 23 are respectively shown in FIG.
) corresponds to input terminal 1 and output terminals 2 and 3.

In this embodiment, since the switch is composed of 0MO8, as shown in FIG. 3(b), the control signals are clock φ1, an inverted clock φ1 of this clock φ1, a clock φ2 and an inverted clock of this clock φ2. φ2 is required. The clock φ1 is applied to N channel MOS transistors Nl, N3 . N8. N7, and the inverted clock φ1 is input to the P-channel MO8) transistors Pi, P3 . P8. It is input to P7. In addition, clock φ2 is applied to N-channel MO8) transistors N2, N4 .
N5. N8, and the inverted clock φ2 is input to the P-channel MO8I-transistor P2. P4゜P5. It is input to P8.

Also in this embodiment, since there is no operational amplifier between the input terminal 21 and the non-inverting input terminal and the inverting input terminal of the fully differential operational amplifier 36, noise is extremely low (input signal V
When IN is input to input terminal 21, output signals Voters and V are output to output terminals 22 and 23, respectively. LJT- is output. In this embodiment, since each switch is constituted by 0MO8, it is possible to obtain an effect that the dynamic range can correspond to a signal with a larger dynamic range than in the first embodiment.

FIG. 4 is a circuit diagram showing a third embodiment in which the present invention is applied to a first-order low-pass filter. The circuit of this example has the first
Between the non-inverting input terminal and the inverting output terminal and between the inverting input terminal and the non-inverting output terminal of the fully differential operational amplifier of the integrator configured similarly to the switched capacitor integrator shown in Figure (a). Each of these is constructed by adding a switched capacitor.

That is, switches 44.45.48.47.48.49.
50 and 51 are switches 4.6.6 in FIG. 1(a), respectively.
．． Compatible with 7.8.9.10 and 11. In addition, capacitors 60, 61, 82 and 83 are shown in FIG. 1 (a), respectively.
), the fully differential operational amplifier 68 corresponds to the fully differential operational amplifier 1 in FIG. 1(a).
6, and the input terminal 41 and output terminals 42 and 43 correspond to the input terminal 1 and output terminals 2 and 3 in FIG. 1(a), respectively. Each of these switches, each capacitor, and the fully differential operational amplifier 66 constitute a switched capacitor integrator.

The non-inverting input terminal of the fully differential operational amplifier 66 is connected to one electrode of a capacitor 64 via a switch 52, and the other electrode of this capacitor 64 is connected to the fully differential operational amplifier via a switch 55. It is connected to the inverting output terminal of 66. Further, a switch 53 is interposed between the one electrode of the capacitor 64 and the ground 67, and a switch 54 is interposed between the other electrode of the capacitor 64 and the ground 67. Further, the inverting input terminal of the fully differential operational amplifier 66 is connected to one electrode of a capacitor 65 via a switch 56.
The other electrode of 5 is connected to the non-inverting output terminal of a fully differential operational amplifier 66 via a switch 59. Furthermore, a switch 57 is inserted between the one electrode of the capacitor 65 and the ground 67, and a switch 58 is inserted between the other electrode of the capacitor 65 and the ground 67. .

These switches 53, 54, 57 and 58, like the switches 44.4B, 49 and 50 of the integrator part, are driven by the clock φ. Also, switch 52.5
5.56 and 59 are switches 45.47 in the integrator section
．． Like 48 and 51, it is driven by clock φ2.

In the low-pass filter according to this embodiment, the cutoff frequency is determined by the frequencies of externally supplied clocks φ1 and φ2. In this case, since no operational amplifier is interposed between the input terminal and the non-inverting input terminal and the inverting input terminal of the fully differential operational amplifier, noise is extremely low.

[Effects of the Invention] As explained above, according to the present invention, the switched capacitor integrator is constituted by a switch, a capacitor, and one fully differential amplifier, and the signal input terminal and the input of the fully differential amplifier are connected to each other. Since there is no operational amplifier between the two ends, the symmetry of the signals input to the fully differential amplifier is extremely excellent. Therefore, the switched capacitor integrator according to the present invention has extremely low noise.

[Brief explanation of drawings]

FIG. 1(a) is a circuit diagram showing a switched capacitor integrator according to the first embodiment of the present invention, FIG. 1(b) is a waveform diagram showing its clock, and FIG. 2 is a diagram showing its operation. FIG. 3(a) is a circuit diagram showing a switched capacitor integrator according to the second embodiment of the present invention, FIG. 3(b) is a waveform diagram showing its clock, and FIG. is a circuit diagram showing a third embodiment in which the present invention is applied to a first-order low-pass filter; FIG. 5(a) is a circuit diagram showing a conventional switched capacitor integrator equipped with an unbalanced/balanced conversion circuit; FIG. 5(b) is a waveform diagram showing the same clock, FIG. 6 is a timing chart showing the operation, and FIG. 7 is the same operation when the output of the inverting amplifier contains noise. It is a timing chart figure shown. 1.21.41,71; input terminal, 2,3,22.23
, 42, 43. 72, 73: Output terminal, 4 to 11.4
4 to 59.74 to 81; switch, 12 to 15,
32 to 35. E30 to 65.82 to 85; Capacitor, 16.3B, 6e, se; Fully differential operational amplifier, 1
7, 37, 87° 88; ground, 87; inverting amplifier

Claims (1)

[Claims] (1) In a switched capacitor integrator driven by a first clock and a second clock having mutually different phases, the first capacitor, the second capacitor, the fully differential amplifier, and the first a first switch inserted between a first electrode of a capacitor and a signal input terminal; a second switch inserted between the first electrode of the first capacitor and a signal ground; a third switch interposed between the second electrode of the first capacitor and the signal ground; and a third switch inserted between the second electrode of the first capacitor and the non-inverting input terminal of the fully differential amplifier. The fourth interposed between
a fifth switch inserted between the first electrode of the second capacitor and the signal input terminal, and between the first electrode of the second capacitor and the signal ground. a sixth switch inserted between the second electrode of the second capacitor and the signal ground; and a seventh switch inserted between the second electrode of the second capacitor and the signal ground;
an eighth switch inserted between the electrode and the inverting input end of the fully differential amplifier; and a third switch inserted between the non-inverting input end and the inverting output end of the fully differential amplifier. and a fourth capacitor inserted between the inverting input terminal and the non-inverting output terminal of the fully differential amplifier, the first switch, the third switch, and the fourth capacitor. 6 switch and the seventh switch are controlled by the first clock, the second switch, the fourth switch,
The fifth switch and the eighth switch are connected to the second switch.
A switched capacitor integrator characterized in that it is controlled by a clock.