JP2009044379A - Switched capacitor integrator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switched capacitor integrator assuring smooth, stable, and high-speed operation with a low power source voltage. <P>SOLUTION: A pair of input capacitors 16a-16b are used and connected with an operational amplifier 17 having a feedback capacitor 18 via an input switch formed of switches 12a-12c in the input side and an output switch 15 in the output side. In addition, a first switch 13a is connected between the input side of the input capacitor 16a and the ground, a second switch 13b between the input side of the input capacitor 16b and the potential V<SB>DD</SB>, and a third switch between the output side of the input capacitors 16a-16b and the reference potential of the operational amplifier 17. Charges of the input capacitors 16a-16b are shifted to the feedback capacitor 18 for integration by alternately turning on and off the switches 13a-13b and 14 and the switches 12a-12c and 15. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an integrator, and in particular, charges a capacitor by sampling (hereinafter referred to as sampling) an analog signal voltage such as an analog audio signal, thereby storing the corresponding charge in the capacitor based on Coulomb's law. The present invention relates to a switched capacitor integrator that is applied to a ΔΣ analog-to-digital converter (ADC) or the like that converts the electric charge stored in the capacitor into a digital signal by integrating.

  An ADC that converts an analog signal into a corresponding digital signal or a signal sampling circuit uses an integrator that samples an input analog signal and outputs an integrated value of the sampled signal voltage (that is, a sample voltage). Such an integrator is generally composed of a switching circuit, a capacitor, and an operational amplifier (or operational amplifier).

  With reference to FIG. 3, the configuration and operation of a typical conventional switched capacitor integrator (hereinafter sometimes simply referred to as an integrator) will be briefly described. The integrator 30 includes an input terminal 31, electronic switches (hereinafter simply referred to as switches) 32-35, an input capacitor 36, an operational amplifier 37, a feedback capacitor 38, and an output terminal 39.

  In the integrator 30, the input terminal 31 is connected to one end (input end) of the input capacitor 36 via the switch 32 and connected to the ground (SG: signal ground) via the switch 33. The other end (output end) of the input capacitor 36 is grounded via the switch 34 and connected to the inverting input end (−) of the operational amplifier 37 via the switch 35. The non-inverting input terminal (+) of the operational amplifier 37 is grounded, and the output terminal is connected to the output terminal 39 and to the inverting input terminal via the feedback capacitor 38. A switch control signal φ1 of the first phase is input to the switch 32 and the switch 34, and a switch control signal φ2 of the second phase (which is shifted from the first phase by a half cycle phase) is input to the switch 33 and the switch 35. Has been.

  Next, the overall operation of the integrator 30 will be described. First, the switch control signal φ1 is input to the input terminal 31 during the signal sampling operation for turning on the switches 32 and 34 (the other switch control signal φ2 keeps the corresponding switches 33 and 35 off). The input capacitor 36 is charged by the analog signal (Vin). The electric charge stored in the input capacitor 36 is substantially the product (Vin * Cin) of the input voltage Vin and the capacitance Cin of the input capacitor 36. Next, when the switch control signal φ2 turns on the switches 33 and 35, the inverting input terminal (−) of the operational amplifier 37 is substantially the same potential as the non-inverting input terminal (+), that is, the virtual ground. The charge of the input capacitor 36 is completely transferred to the feedback capacitor 38, and an output voltage (Vout) obtained by dividing the charge by the capacitance of the feedback capacitor 38 is output to the output terminal 39.

However, the integrator 30 shown in FIG. 3 ideally turns on and off the electronic switches that constitute the switches 32 to 35, generally MOS transistors, and in particular, in order to make the on-resistance sufficiently low, The voltage (V _DD ) needs to be increased, and the demand for lowering the voltage cannot be satisfied.

Various efforts have been made to satisfy the demand for lower voltage. One of these is “0.6V, 82dB ΔΣ Audio ADC Using Switched RC Integrator” (A 0.6V 82-dB Delta-Sigma Audio ADC Using Switched RC-Integrator) operating at 0.6V. (For example, refer nonpatent literature 1). The ADC for audio signals capable of operating at a low voltage is configured as shown in FIGS. 4 (A) and 4 (B).
IEEE Journal of Solid-State Circuits, Vol. 40, No. 12, December 2005pp.2358-2407

  First, the low voltage integrator 40 shown in FIG. 4A includes an input terminal 41, switches 42 to 45, an input capacitor 46, an operational amplifier 47, a feedback capacitor 48, and an output terminal 49, in addition to the input capacitor 46. The additional capacitor 50 has one end connected to the output side and the switches 52 and 53 connected to the other end.

Input terminal 41 is connected to an input terminal of the input capacitor 46 through the switch 42, is connected to a potential source V _SS via the switch 43. The output terminal of the input capacitor 46 is connected to the reference potential source Vref through the switch 44, and is connected to the inverting input terminal of the operational amplifier 47 through the switch 45, and further through the additional capacitor 50 and the switch 52 described above. V _SS is connected to V _DD via switch 53. The non-inverting input terminal (+) of the operational amplifier 47 is connected to the reference potential source Vref, and the output terminal is connected to the output terminal 49 and to the inverting input terminal (−) via the feedback capacitor 48. Here, one switch control signal φ1 is input to the control terminals of the switches 42, 44 and 52, and a switch control signal φ2 which is shifted from the switch control signal φ1 by a half cycle phase is input to the switches 43 and 45. The switch 53 is supplied with a switch control signal (/ φ2) having a phase opposite to that of the switch control signal φ2.

The operation of the integrator 40 will be described. First, during the signal sampling operation, the switch control signal φ1 turns on the switches 44 and 52, charges the input capacitor 46 with the potential difference between the input signal Vin of the input terminal 41 and the reference potential Vref, and sets the additional capacitor 50 to V _SS. And a reference potential Vref. Next, when the switch control signal φ2 (and / φ2) turns on the switches 43, 45, and 53, the charge of the input capacitor 46 is moved to the feedback capacitor 48 and the charge of the additional capacitor 50 and the switch 53 are turned on. As a result, the charge due to the potential difference between V _DD and Vref charged in the additional capacitor 50 is moved to the feedback capacitor 48. An output voltage based on the moved charges is output to the output terminal 49 of the operational amplifier 47.

  On the other hand, the integrator 60 reduced in voltage shown in FIG. 4B includes an input terminal 61, a pair of resistors 70a-70b, switches 63a, 63b, 64 and 65, a pair of input capacitors 66a-66b, and an operational amplifier 67. A feedback capacitor 68 and an output terminal 69 are included.

In the integrator 60 whose voltage has been lowered, the input terminal 61 is connected to one end of each of the resistors 70a to 70b, and the other end is connected to the input end of each of the input capacitors 66a to 66b. The common connection point of the resistors 70a and input capacitor 66a is connected to _{V SS} through a switch 63a. The common connection point of the resistor 70b and the input capacitor 66b is connected to V _DD via the switch 63b. The output terminals of the input capacitors 66 a-66 b are connected to the reference potential source Vref through the switch 64 and are connected to the inverting input terminal of the operational amplifier 67 through the switch 65. A reference potential source Vref is connected to the non-inverting input terminal (+) of the operational amplifier 67, and the output terminal is connected to the output terminal 69 and to the inverting input terminal via the feedback capacitor 68. The first switch control signal φ1 is input to the switch 64, the switch control signal φ2 having a half cycle phase different from that of the first switch control signal φ1 is input to the switches 63a and 65, and the switch 63b receives this switch control signal φ1. A switch control signal (/ φ2) having a phase opposite to that of the switch control signal φ2 is input.

  Next, the operation of the integrator 60 shown in FIG. 4B will be described. First, when the switch control signal φ1 turns on the switch 64, the input signal voltage Vin at the input terminal 61 charges the input capacitors 66a and 66b with the potential difference between the input signal voltage Vin and the reference potential Vref via the resistors 70a and 70b, respectively. To do. Next, the switches 63 a and 63 b are turned on by the switch control signals φ 2 and / φ and the switch 65 is also turned on, and the charge charges of the input capacitors 66 a and 66 b are transferred to the feedback capacitor 68 connected to the operational amplifier 67. Then, an output voltage Vout corresponding to the moved charges is output from an output terminal 69 connected to the output terminal of the operational amplifier 67.

  Each of the conventional integrators as described above has problems to be solved. That is, the typical integrator 30 as shown in FIG. 3 has a high operating power supply voltage of the switch as described above, and cannot be operated stably and smoothly at a low voltage (for example, about 1 V). Further, the integrator 40 as shown in FIG. 4A can be operated at a low voltage, but noise due to the capacitor 50 increases and a large substrate area is required to obtain a predetermined capacitance (capacitance). Therefore, it is difficult to reduce the size of the IC (integrated circuit). Further, the integrator 60 as shown in FIG. 4B can operate at a low voltage, but charges the input capacitor 66 through the resistor 70 during the sampling operation of the input signal. However, there is a problem in that waveform distortion occurs in a signal sampled with a limited number of signals, and not only a high-speed sampling operation cannot be performed but also thermal noise (noise) due to resistance.

  The present invention has been made in view of the above-described problems of the prior art, and has as its main object to provide a switched capacitor integrator that operates at a low voltage and at high speed and stably.

  In order to achieve the above-described object, the switched capacitor integrator according to the present invention employs the following characteristic configuration.

(1) An input capacitor, an input switch connected to the input side thereof, an output switch connected to the output side of the input capacitor, an operational amplifier whose output side is connected to the input end, and an input end and an output end of the operational amplifier A switched-capacitor integrator including a feedback capacitor connected between the input capacitor and the input capacitor is composed of a pair of input capacitors connected in common on the output side, and the input switch is paired with an input terminal to which an input signal is input. A pair of switches each connected to the input side of the input capacitor and three switches connected between the input ends of the pair of input capacitors, each having the input of one input capacitor of the pair of input capacitors A first switch connected between the first side and the ground, the input side of the other input capacitor of the pair of input capacitors and the V _DD voltage And a second switch connected between the sources and a third switch connected between the output side of the pair of input capacitors and the reference potential of the input terminal of the operational amplifier, the first to third switches, the input switch, The output switch is alternately turned on and off.

  (2) The switched capacitor integrator according to (1), wherein the pair of input capacitors have a capacitance (capacitance) equal to each other.

  (3) The first switch, the third switch and the output switch are formed by n-channel MOS transistors, the second switch is formed by a p-channel MOS transistor, and the input switch is formed by a complementary MOS transistor. (1) or (2 Switched capacitor integrator as described in).

  (4) The operational amplifier is a differential operational amplifier in which a feedback capacitor is connected between the input and output terminals, and the circuit comprising the pair of input capacitors, input / output switches, and first to third switches according to (1). A switched-capacitor integrator that is connected to each input terminal of a differential operational amplifier and is a fully differential type that integrates differential input signals.

  The switched-capacitor integrator according to the present invention that employs the characteristic configuration as described above has the following specific effects. That is, it is possible to realize a switched capacitor integrator that operates smoothly and stably with a low power supply voltage of, for example, about 1V. Since the signal is sampled through the switch with low on-resistance even at low power supply voltage, the charging speed is not limited by the CR time constant consisting of the on-resistance of the switch and the input capacitor, and it is possible to perform sampling operation at high speed is there. Also, since the pair of input capacitors are connected in parallel, the capacitance of each capacitor may be half that of a conventional input capacitor (using one input capacitor), and does not impair the miniaturization of the IC. Furthermore, since no resistor is connected in front of the input capacitor, performance degradation due to thermal noise due to this resistor does not occur.

  Hereinafter, the configuration and operation of a preferred embodiment of the switched capacitor integrator according to the present invention will be described in detail with reference to the accompanying drawings.

  First, FIG. 1 is a circuit diagram showing in partial block form the configuration of a first embodiment of a switched capacitance integrator (hereinafter also simply referred to as an integrator) according to the present invention. The integrator 10 includes an input terminal 11, electronic switches (hereinafter simply referred to as switches) 12a to 12c, 13a, 13b, 14 and 15, an operational amplifier 17, and a pair of input capacitors having the same capacitance (capacitance). 16a-16b, a feedback capacitor 18 and an output terminal 19.

The input terminal 11 is a terminal to which the input signal voltage in is input, and is connected to the input terminals of the input capacitors 16a and 16b via the switches 12a and 12b, respectively. The input terminal of the input capacitor 16a is connected to the ground (GND) through the switch 13a, and the input terminal of the other input capacitor 16b is connected to V _DD through the switch 13b. Further, another switch 12c is connected between the input terminals of the pair of input capacitors 16a and 16b.

  On the other hand, the output terminals of the pair of input capacitors 16a and 16b described above are connected in common and connected to the reference potential source Vref through the switch 14 and to the inverting input terminal (−) of the operational amplifier 17 through the switch 15. Has been. The non-inverting input terminal (+) of the operational amplifier 17 is connected to the above-described reference potential source Vref, and the output terminal thereof is connected to the output terminal 19 and is connected to the inverting input terminal via the feedback capacitor 18.

  In the integrator 10 described above, the switch control signal φ1 of the first phase is input to the switches 13a and 14, and the inverted signal / φ1 of the switch control signal φ1 of the first phase is input to the switch 13b. The switches 12a to 12c and 15 are supplied with a switch control signal φ2 having a second phase which is shifted from the above-described first phase switch control signal φ1 by a half cycle phase.

  In the integrator 10, the switches 12a to 12c are CMOS (complementary MOS) transistor switches, the switches 13a, 14 and 15 are nMOS (n channel MOS) transistor switches, and the switch 13b is a pMOS (p channel MOS) transistor switch. Is preferred.

Next, the operation of the integrator 10 shown in FIG. 1 will be described. The input signal voltage Vin input to the input terminal 11 is such that the center voltage V _COM is half V _DD , that is, V _DD / 2. First, the switches 13a, 13b and 14 are turned on by the switch control signal φ1. Therefore, the input capacitor 16a is charged by the potential difference between the ground potential GND and the reference potential Vref connected to the lower ends of the switches 13a and 14, respectively. On the other hand, the input capacitor 16b is charged by the potential difference between the power supply potential V _DD and the reference potential Vref.

  When the switches 12a to 12c and 15 are turned on by the switch control signal φ2 after the half cycle, the input terminals of the pair of input capacitors 16a and 16b are short-circuited by the switch 12c, and the input capacitors 16a and 16b are connected in parallel. Therefore, a part of the charge of the input capacitor 16b is transferred to the input capacitor 16a, the charge charges of both the input capacitors 16a and 16b are made equal, and the input capacitors 16a and 16b are charged with the input signal voltage Vin via the switches 12a and 12b. To do. Then, the charge charges of the input capacitors 16 a and 16 b are moved to the feedback capacitor 18 by the operation of the operational amplifier 17. As is well known to those skilled in the art, the potential of the inverting input terminal (−) of the operational amplifier 17 is maintained equal to the reference potential Vref applied to the non-inverting input terminal (+). Then, an output voltage Vout corresponding to the charge transferred to the feedback capacitor 18 is output from the output terminal 19.

  Note that, as described above, the input capacitors 16a and 16b are connected in parallel when transferring the charged signal charge. The integrator 10 of the present invention uses a pair (two) of input capacitors 16a and 16b having equal capacitance, but when these capacitors 16a and 16b are connected in parallel, the combined capacitance is doubled. Therefore, the capacitances of the capacitors 16a and 16b may be, for example, half the capacitance of the input capacitor 36 of the conventional integrator 30 shown in FIG. 3, and do not occupy a large area on the IC substrate, so that the size of the IC can be reduced. There is no loss of conversion.

  Hereinafter, the turning on of the switches 13a, 13b and 14 by the switch control signal φ1 and the turning on of the switches 12a to 12c and 15 by the switch control signal φ2 are repeated every half cycle of the switch control signal. Then, instantaneous values at different time points of the input signal voltage Vin are sequentially sampled and held in the feedback capacitor 18. Here, the frequency of the on / off repeated operation of these switches will be described. For example, an audio signal having a bandwidth of 20 kHz is used as an analog input signal, and this integrator is used in a ΔΣ analog-digital converter (ADC) that converts the audio signal into a corresponding digital signal, thereby obtaining a digital signal having a sampling rate fs = 48 kHz. Assume a case. In this case, assuming that the oversampling ratio (OSR) of the ΔΣ ADC is 64, for example, these switches are repeatedly turned on and off at a frequency of 48 kHz × 64 = 3,072 MHz.

Next, a second embodiment of the integrator according to the present invention will be described with reference to FIG. The integrator 20 is an integrator having a fully differential configuration, and is substantially a differential whose center potential is V _COM (= V _DD / 2) using a pair of integrators 10 shown in FIG. (Or complementary) type input signals are sampled by the sampling circuits SAp and SAn, respectively, and input to a pair of input terminals of the differential type operational amplifier 17. A pair of output terminals of the differential operational amplifier 17 are output terminals 19a and 19b that output differential (antiphase) output signals Voutp and Voutn, respectively, and 1 connected to the input terminal from these output terminals. A pair of feedback capacitors 18a and 18b is included. Charges due to the input signals sampled by the respective sampling circuits 22a and 22b are transferred to the feedback capacitors 18a and 18b, and corresponding differential output voltages are output.

  The preferred embodiment of the switched capacitor integrator according to the present invention has been described in detail above. However, it should be noted that such examples are merely illustrative of the invention and do not limit the invention in any way. Those skilled in the art will readily understand that various modifications and changes can be made in accordance with a specific application without departing from the gist and spirit of the present invention.

1 is a circuit diagram showing a configuration of a first embodiment of a switched capacitor integrator according to the present invention; FIG. It is a circuit diagram which shows the structure of 2nd Example of the switched capacitor integrator by this invention. It is a circuit diagram of the conventional typical switched capacitor integrator. The basic circuit diagram of the conventional switched capacitor integrator by which voltage reduction was carried out is shown, (A) is a 1st example, (B) is a 2nd example.

Explanation of symbols

10, 20 Switched Capacitor Integrator 11 Input Terminals 12a-12c Input Switch 13a First Switch 13b Second Switch 14 Third Switch 15 Output Switch 16a, 16b Input Capacitor 17 Op Amp 18 Feedback Capacitor 19 Output Terminals φ1, φ2 Switch Control Signal

Claims (4)

An input capacitor connected to the input side of the input capacitor, an output switch connected to the output side of the input capacitor, an operational amplifier with the output side of the output switch connected to the input end, the input end of the operational amplifier, and In a switched capacitor integrator including a feedback capacitor connected between the outputs,
The input capacitor is composed of a pair of input capacitors whose outputs are commonly connected, and the input switch is a pair of switches connected to an input terminal to which an input signal is input and an input side of the pair of input capacitors, respectively. And three switches connected between the input end sides of the pair of input capacitors,
A first switch connected between the input side of one input capacitor of the pair of input capacitors and the ground, and a second switch connected between the input side of the other input capacitor of the pair of input capacitors and the VDD power supply And a third switch connected between a reference potential of an output side of the pair of input capacitors and an input end of the operational amplifier,
A switched capacitor integrator, wherein the first to third switches, the input switch, and the output switch are alternately turned on and off.   The switched capacitor integrator according to claim 1, wherein the pair of input capacitors have capacitances equal to each other.   2. The first switch, the third switch, and the output switch are formed by n-channel MOS transistors, the second switch is formed by a p-channel MOS transistor, and the input switches are formed by complementary MOS transistors. The switched capacitor integrator according to 2. 2. The circuit comprising a pair of input capacitors, the input / output switches, and the first to third switches according to claim 1, wherein each of the operational amplifiers is a differential operational amplifier in which a feedback capacitor is connected between input and output terminals. Are connected to the respective input terminals of the differential operational amplifier, and each of them is of a fully differential type that integrates a differential input signal.

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