JP2008060978A - Switched capacitor circuit, correlation double sampling circuit, and electronic device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SCA circuit which can perform a broadband sampling operation or the like in the SCA circuit which performs autozero. <P>SOLUTION: An SCA circuit has M+N amplifying circuits comprising M preamplifiers and N operational amplifiers, where the first stage is made a single preamplifier of the preamplifiers, the subsequent stage is made a single operational amplifier of the operational amplifiers, the rest of the preamplifiers and the operational amplifiers are mixed and arranged in an arbitrary order, M+N-1 capacitors C<SB>C</SB>for connecting input/output terminal of the M+N amplifying circuits mutually connected in series, a single capacitor C<SB>S</SB>arranged through a switch SW2 between a differential input terminal and a terminal V<SB>IN</SB>at the first stage, a single capacitor C<SB>F</SB>arranged through a switch SW3 between a differential input terminal and a signal output terminal V<SB>OUT</SB>of the preamplifier at the first stage, a set of M switches SW1A and switches SW1B, or a set of a parallel connection of switches SW1B and capacitors C<SB>COMP</SB>, which are N in total are provided. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a switched capacitor circuit, a correlated double sampling circuit, and an electronic device using the same, and more particularly to a switched capacitor amplifier circuit that performs auto-zero, a correlated double sampling circuit, and an electronic device using the same. It is.

  A switched capacitor amplifier circuit (hereinafter referred to as “SCA circuit”) that performs auto-zero is used in an image sensor module, an analog front end of an audio signal processing system, and the like.

  Here, the auto-zero refers to removing low-frequency noise generated from an operational amplifier circuit constituting the SCA circuit or low-frequency noise included in the image sensor signal. The SCA circuit technique for performing this auto-zero is described in detail in Non-Patent Document 1.

  Non-Patent Document 4 describes an example in which this SCA circuit technology is applied to an image sensor CDS circuit.

  Here, an example of a conventional general SCA circuit will be described with reference to FIGS.

  11 and 12 are circuit diagrams showing configurations of the SCA circuit 100 and the SCA circuit 110, which are examples of conventional general SCA circuits.

  First, the configuration of the SCA circuit 100 will be described with reference to FIG. As shown in FIG. 11, the SCA circuit 100 includes an operational amplifier circuit AMP1, a plurality of terminals, a plurality of switches, and a plurality of capacitors.

The SCA circuit 100 is provided with three switches SW101, SW102, and SW103 as switches. The SCA circuit 100 includes two capacitors C _S 104 and C _F 105 as capacitors.

In addition, V _IN 107, V _OUT 108, and V _REF 109 in FIG. 11 are an input terminal, an output terminal, and a reference voltage terminal (hereinafter referred to as V _IN 107, V _OUT 108, and V _REF 109) of the SCA circuit 100, respectively. , Each of which represents an input voltage, an output voltage, and a reference voltage).

  Next, the operation of the SCA circuit 100 will be described with reference to FIG.

The SCA circuit 100 has two operation phases, a sampling phase (hereinafter referred to as “PHASE-S”) and a hold phase (hereinafter referred to as “PHASE-H”).
FIG. 11 shows the connection of the switches of the SCA circuit 100 in PHASE-S.

First, in PHASE-S, the electric charge corresponding to the input signal input from the input terminal V _IN 107 is sampled in the capacitor C _S 104. At the same time, charges corresponding to the reference voltage signal at the reference voltage terminal V _REF 109 are stored in C _F 105.

Next, in PHASE-H, the electric charge according to the input signal sampled in the C _S 104 is transferred to the capacitor C _F 105, and at the same time, the output signal corresponding to the transferred electric charge is output from the output terminal V _OUT 108. Is output.

Also it shows in Fig. 11 the input offset voltage and 1 / f noise of AMP1 circuit in the SCA circuits 100 as a voltage source _{V OS.} Here, it is assumed that the AMP1 circuit is ideal.

Then, if the law of charge conservation is applied between PHASE-S and PHASE-H, the following equation is established. In addition, the number attached | subjected to each parameter was abbreviate | omitted (hereinafter, the same description is abbreviate | omitted).
(V _IN −V _OS ) · C _S + (V _REF −V _OS ) · C _F = (− V _OS ) · C _S + (V _OUT −V _OS ) · C _F
Here, the voltage V _IN is a voltage of an input signal corresponding to the charge sampled by the capacitor C _S 105 of the SCA circuit 100 in PHASE-S, and the voltage V _OUT is an output voltage of the SCA circuit 100 in PHASE-H. Indicates. When the above equation is arranged, the following equation is obtained.
V _OUT = (C _S / C _F ) · V _IN + V _REF
Thus, it can be seen that the voltage source V _OS does not affect the output voltage V _OUT of the SCA circuit 100. Therefore, it can be seen that the input offset voltage and 1 / f noise of the AMP1 circuit in the SCA circuit 100 can be reduced.

  Next, thermal noise of the SCA circuit 100 will be considered. The transconductance of the AMP1 circuit in the SCA circuit 100 is gm, and the input conversion noise of the AMP1 circuit is

And

  Here, k is a Boltzmann constant, T is an absolute temperature, and γ is a constant determined by the transistors constituting the AMP1 circuit.

  In the AMP1 circuit in the SCA circuit 100, three types of noise are generated. The first is kTC noise caused by the on resistance of the switches SW101, SW102, and SW103.

  Next, the second is noise (hereinafter referred to as “auto-zero noise”) of the AMP1 circuit sampled during the auto-zero operation of PHASE-S.

  Finally, the third is noise (hereinafter referred to as “hold noise”) of the AMP1 circuit that is output to the output terminal during PHASE-H.

Table 1 shows input conversion values of these three noises to the input terminal V _IN 107. Table 1 shows the theoretical value of noise of the SCA circuit 100 and its approximate value. When the amplification factor of the SCA circuit 100 is large, the input signal to be input may be small. When this small input signal is input, low input conversion noise is required in the SCA circuit 100. The

Therefore, in Table 1, it is assumed that the amplification factor G between the input and output of the SCA circuit 100 is G = C _S / C _F >> 1, and the constant γ determined by the transistors constituting the AMP1 circuit is γ = 1. Led.

F is a feedback factor and is expressed as F = C _F / (C _S + C _F ).

From Table 1, when the amplification factor of the SCA circuit 100 is sufficiently large (G is about 6) and the capacitive load C _L 106 is large, the kTC noise is almost equal to the auto zero noise. The hold noise of the SCA circuit 100 is sufficiently smaller than kTC noise and auto zero noise.

  Therefore, in the SCA circuit 100, the noise performance is determined by the kTC noise and the auto zero noise.

Next, another example of a conventional SCA circuit is shown. FIG. 12 is a circuit diagram showing a configuration of this conventional SCA circuit 110. As shown in FIG. The SCA circuits 110, and one capacitor _C S 113, and two switches SW 111, and SW 112, comprised of one amplifier circuit AMP2 Prefecture.

  The amplification factor of the AMP1 circuit in the SCA circuit 100 is ideally infinite, whereas the amplification factor of the AMP2 circuit in the SCA circuit 110 is larger than 1 and smaller than 20.

  Next, the operation of the SCA circuit 110 will be described with reference to FIG.

  In the SCA circuit 110, there are two operation phases: a reset phase and an amplification phase.

In the reset phase, the input terminal V _IN 114 of the AMP2 circuit in the SCA circuit 110 is cut off, and the output terminal V _OUT 115 is connected to the ground level. On the other hand, in the amplification phase, the non-inverting input terminal of the AMP2 circuit is connected to the input terminal V _IN 114, and at the same time, the output terminal V _OUT 115 is cut off from the ground level.

In the reset phase, the output voltage of the AMP2 circuit is V _{OUT−AMP2−RESET} = −A ₂ · V _OS .
Here, the amplification factor of the AMP2 circuit and _{A 2.}

The output voltage of the AMP2 circuit in the amplification phase is V _{OUT−AMP2−AMP} = (V _IN −V _OS ) · A ₂
It becomes. Therefore, from these two equations, the output voltage at the output terminal V _OUT 115 becomes the following equation.
V _OUT = V _IN · A ₂
From this equation, the output voltage of the SCA circuits 110 voltage source _{V OS} is found that no influence.

  Therefore, the SCA circuit 110 can reduce the input offset voltage and low frequency noise of the AMP2 circuit.

Further, since the SCA circuit 110 is not a feedback circuit, it can operate at high speed. In the SCA circuit 110, the input impedance of the next stage connected to the output terminal V _OUT 115 needs to be high impedance (see FIG. 22 (a) of Non-Patent Document 1). For this reason, the SCA circuit 110 is not often used for an image sensor CDS circuit or the like. On the other hand, the SCA circuit 110 is generally often used for an image sensor CDS circuit or the like (see Non-Patent Document 4).
CCEnz and Gabor C. Temes, `` Circuit Techniques for Reducing the Effects of Op-Amp Imperfections '' (USA), Proceedings of the IEEE), Vol. 84, No. 11, November 1996, p. 1595 Figure 28 on page 20, 1600, etc. Katsu Nakamura and 12 others, `` A CMOS Analog Front-End Chip-Set for Mega Pixel Camcorders '', IEEE International Solid-State Circuits Conference 2000 I.Mehr, 5 others, `` An integrated mixed-signal front-end for broadband modems '', Symposium VLSI Circuits, June 2002, p.38-41 US Pat. No. 6,433,632

However, in the conventional SCA circuit 100, when realizing a switched capacitor circuit with low noise, it is necessary to increase the capacitances of the capacitors C _S 104 and C _F 105, which has the following problems. ing.

First, in the sampling phase PHASE-S, one terminal of the capacitor C _S 104 is connected to the input terminal V _IN 107. Further, the other terminal of the capacitor C _S 104 is connected to the inverting input terminal and the output terminal V _OUT 108 of the AMP1 circuit.

Assuming that the output impedance of the circuit connected to the previous stage of the SCA circuit 100 for driving the SCA circuit 100 (the circuit connected to the terminal V _IN 107) is sufficiently small to be negligible, the capacitor C _S 104 is applied. The band BW _{PH-S with} respect to the voltage is given by the following equation.

  However, the on-resistance of the switches SW102 and SW103 is ignored here. This is because the transconductance gm of the AMP1 circuit has a greater influence on the band limitation of the SCA circuit 100 than the on-resistance.

  A typical configuration of the operational amplifier circuit AMP1 (hereinafter referred to as “AMP1 circuit”) will be described with reference to FIG.

  FIG. 13 is a circuit diagram showing the configuration of the AMP1 circuit in the SCA circuit 100 of FIG.

  As an example of a typical configuration of the AMP1 circuit, a single-stage operational amplifier circuit is used as shown in FIG. The AMP1 circuit is composed of five transistors.

  Next, the function of each transistor will be described. The transistors M121P and M121M are a pair of transistors that convert the input differential signals VINP and VINM into differential currents.

  The grounded transistor M1C is a transistor that functions as a constant current source (also referred to as a tail current source) for supplying a constant current. The transistors M122P and M122M are active load transistors configured by so-called current mirror circuits, and are used to convert the differential current converted by the transistors M121P and M121M into a single-ended current for output. is there.

  Here, gm in the above equation 2 is the transconductance of M121P or M121M that is the pair of transistors in FIG.

  When the SCA circuit 100 samples an input signal, it is necessary to increase the transconductance gm of the AMP1 circuit. Therefore, there is a problem that power consumption increases in order to realize high-speed sampling of the SCA circuit 100.

On the other hand, in the hold phase PHASE-H, the band BW _{PH-H with} respect to the voltage of the output terminal V _OUT 108 is as follows.

Here, _{C L} is the next stage of the sampling capacitor or the like connected to the output terminal _V OUT 108 in the hold phase.

Then, in the configuration of the SCA circuit 100, if the capacitive load C _L 106 is sufficiently small, BW _PH-S <BW _PH-H . Therefore, there arises a problem that the band BW _PH-S limits the band of the SCA circuit 100.

On the other hand, since the SCA circuit 110 is not a feedback circuit, it can operate at a high speed, and as a result, a wide band sampling can be performed. However, as described above, in the SCA circuit 110, the input impedance of the next stage connected to the output terminal V _OUT 115 needs to be high impedance, but a circuit having a high impedance is actually arranged. At this time, there is a problem that gain degradation occurs in the output section of the SCA circuit 110.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to perform wideband sampling and operation in a switched capacitor circuit that performs auto zero including an amplifier circuit, a plurality of switches, and a capacitor. It is an object of the present invention to provide a switched capacitor circuit that can be performed and an electronic device using the same.

  In order to solve the above problems, a switched capacitor circuit according to the present invention is provided with M (M is 1 or more) amplifier circuit preamplifiers having a differential input terminal between a signal input terminal and a signal output terminal; N amplifiers (N is 1 or more) having operational input terminals are connected in series. Among the plurality of amplifier circuits, an amplifier circuit preamplifier is arranged as the first stage amplifier circuit. An amplification circuit operational amplifier is arranged as a stage amplification circuit, and M + N−1 input / output capacitors for connecting the input / output terminals of the M + N amplification circuits connected in series with each other; A sampling capacitor for sampling an input signal, disposed between the differential input terminal of the amplifier circuit preamplifier and the signal input terminal, and the amplifier circuit preamplifier of the first stage A transfer charge capacitor disposed between the differential input terminal and the signal output terminal; M differential input short-circuit switches for short-circuiting the two differential input terminals of each of the amplifier circuit preamplifiers; This is a configuration having N input / output short-circuit switches for short-circuiting the inverting input terminal of the amplifier circuit operational amplifier and the output terminal of the amplifier circuit operational amplifier.

  According to the above configuration, in the switched capacitor circuit of the present invention, the M differential input short-circuit switches and the N input / output short-circuit switches are short-circuited in the sampling phase in which charge sampling is performed according to the input signal. As a result, a portion constituted by M (M is 1 or more) amplifier circuit preamplifiers, N (N is 1 or more) amplifier circuit operational amplifiers, and M + N−1 input / output capacitors is the input in the sampling phase. It becomes irrelevant to signal sampling. The capacitor between the input and output samples low frequency noise of the amplifier circuit preamplifier and the amplifier circuit operational amplifier.

  Therefore, in the switched capacitor circuit of the present invention, the circuit for sampling the electric charge according to the input signal can be constituted by only the differential input short circuit switch and the sampling capacitor of the first stage amplifier preamplifier which is a passive element.

  Therefore, it is possible to realize a switched capacitor amplifier circuit that performs wide-band sampling and auto-zero.

  Note that switching elements such as MOS transistors can be suitably used for the various switches in the switched capacitor amplifier circuit (the same description is omitted hereinafter).

  In addition to the above configuration, the switched capacitor circuit according to the present invention further includes a capacitor biased to a certain voltage in any one or more of the N input / output short-circuit switches. It is preferable that they are connected in series.

  According to the above configuration, the bias voltage between the input and output terminals of each amplifier operational amplifier can be independently set to a desired value.

  Further, the switched capacitor circuit of the present invention includes an amplifier circuit preamplifier having a differential input terminal and an amplifier circuit operational amplifier having a differential input terminal connected in series between a signal input terminal and a signal output terminal. And a differential input short circuit for short-circuiting the two differential input terminals of the amplifier circuit preamplifier, and an input / output capacitor connecting the output terminal of the amplifier circuit preamplifier and the input terminal of the amplifier circuit operational amplifier. The switch includes a switch and an input / output short-circuit switch for short-circuiting the inverting input terminal of the amplifier circuit operational amplifier and the output terminal of the amplifier circuit operational amplifier.

  According to the above configuration, the switched capacitor circuit has the amplifier circuit preamplifier and the amplifier circuit operational amplifier connected in series via the input / output capacitor. Therefore, the amplification factor of the entire switched capacitor circuit can be increased while reducing the amplification factor of the first stage amplifier circuit preamplifier. The switched capacitor circuit short-circuits the differential input short-circuit switch for short-circuiting the two differential input terminals of the amplifier circuit preamplifier and the inverting input terminal of the amplifier circuit operational amplifier and the output terminal of the amplifier circuit operational amplifier. And an input / output short-circuit switch. Therefore, the auto zero operation can be performed by operating the differential input short-circuit switch and the input / output short-circuit switch.

  Therefore, the circuit configuration is simpler and the design is easier than the configuration in which N or M is 2 or more. In addition, in this way, the switched capacitor circuit that performs the auto-zero operation can be used in a comparator or the like that does not need to form a feedback circuit. At this time, high-speed reset and signal tracking are possible. Therefore, it is possible to operate in a wide band.

  In the switched capacitor circuit of the present invention, in addition to the above configuration, it is preferable that a capacitor biased to a certain voltage is further connected in series to the input / output short-circuit switch.

  According to the above configuration, the bias voltage between the input and output terminals of each amplifier operational amplifier can be independently set to a desired value.

  In addition to the above configuration, the switched capacitor circuit of the present invention is preferably an amplifier circuit in which the preamplifier has an input differential pair and an amplification factor between input and output is larger than 1 and smaller than 20.

  According to the above configuration, the preamplifier is an amplifier circuit having an input differential pair, and an amplification factor between input and output is larger than 1 and smaller than 20.

  Therefore, since the amplification factor between the input and output of the preamplifier is small, it is possible not to saturate the voltage at the output terminal even if the two differential input terminals in the first stage preamplifier circuit are short-circuited.

  In the switched capacitor circuit of the present invention, in addition to the above configuration, the amplifier circuit operational amplifier preferably has a voltage input signal and a current output signal.

  According to the above configuration, the switched capacitor circuit of the present invention can be applied to a circuit that obtains a current signal from a voltage signal.

  In addition to the above configuration, the switched capacitor circuit of the present invention includes, as operation phases, a first phase that performs an auto-zero operation and a second phase that amplifies an input signal of the switched capacitor circuit. The sampling capacitor samples the input signal in the first phase, and the charge transfer capacitor preferably transfers the sampled charge to the first sampling capacitor in the second phase.

  According to the above configuration, in a switched capacitor circuit having two operation phases based on a plurality of switch operations, it is possible to configure an input signal sampling circuit with only passive elements in a specific operation phase.

  Therefore, broadband sampling can be performed in a specific phase.

In addition to the above configuration, the switched capacitor circuit of the present invention includes, as operation phases, a first phase for performing an auto zero operation and a second phase for amplifying an input signal of the switched capacitor circuit. In the first phase, the first capacitor is disposed between the input terminal of the amplifier circuit preamplifier and the signal input terminal, and samples the input signal. In the second phase, the input terminal of the amplifier circuit preamplifier. And an output terminal of an amplifier circuit operational amplifier arranged at the end of the series connection, and a charge transfer capacitor for transferring the sampled charge to the first capacitor. The switched capacitor circuit according to claim 3 or 4.
It is preferable.

  According to the above configuration, in the switched capacitor circuit having the first capacitor for sampling the charge and having a plurality of operation phases, the input signal sampling circuit is configured by only the passive element in the specific operation phase. It is possible.

  Therefore, it is possible to provide a switched capacitor circuit capable of performing broadband sampling in a specific operation phase.

  In addition to the above configuration, the switched capacitor circuit of the present invention includes M (M is 1 or more) first amplifier circuits and N (N is N) between the signal input terminal and the signal output terminal. M + N−1 inputs / outputs for connecting the input / output terminals of the M + N amplifier circuits connected in series to each other. A sampling capacitor for sampling an input signal, and an input of the first-stage amplifier circuit, disposed between the input terminal of the first-stage amplifier circuit and the signal input terminal among the M + N amplifier circuits A transfer charge capacitor disposed between the terminal and the signal output terminal, and N input / output short-circuit switches for short-circuiting the input terminal of each amplifier circuit and the output terminal of the amplifier circuit. is there.

  According to the above configuration, the switched capacitor circuit of the present invention can be applied to various types of amplifier circuits.

  The correlated double sampling circuit of the present invention is a correlated double sampling circuit having a configuration in which an amplifier circuit preamplifier having a differential input terminal and an amplifier circuit operational amplifier having a differential input terminal are connected in series. An input / output capacitor disposed between the output terminal of the amplifier circuit preamplifier and the input terminal of the amplifier circuit operational amplifier, and a differential input short-circuit switch for short-circuiting the two differential input terminals of the amplifier circuit preamplifier And an input / output short-circuit switch for short-circuiting the inverting input terminal of the amplifier circuit operational amplifier and the output terminal of the amplifier circuit operational amplifier, and without a switch between the input terminal and the signal input terminal of the amplifier circuit preamplifier. And a sampling capacitor directly connected.

  According to the above configuration, the input / output capacitor disposed between the output terminal of the preamplifier and the input terminal of the operational amplifier, and the differential input short-circuit switch for short-circuiting the two differential input terminals of the preamplifier And an input / output short-circuit switch for short-circuiting the inverting input terminal of the operational amplifier and the output terminal of the operational amplifier. Therefore, by operating these switches, auto-zero operation can be realized.

Further, by adopting a two-stage configuration of the amplifier circuit preamplifier and the amplifier circuit operational amplifier, even when the amplification factor of the correlated double sampling circuit is increased, the hold phase (holds the sampled charge) with only a slight increase in power consumption. Therefore, it is possible to perform a sampling operation capable of following an abrupt change of the image sensor at a high speed while realizing auto-zero operation and correlated double sampling. A double sampling circuit can be provided.

  In the correlated double sampling circuit of the present invention, in addition to the above configuration, it is preferable that a capacitor biased to a certain voltage is further connected in series to the input / output short-circuit switch.

  According to the above configuration, the bias voltage between the input and output terminals of each amplifier operational amplifier can be independently set to a desired value.

  In addition to the above configuration, the correlated double sampling circuit of the present invention is provided with an inter-output-terminal switch between the output terminal of the operational amplifier and the output terminal of the correlated double sampling circuit, and is shut off during auto-zero operation. It is preferable to be characterized by this.

  According to the above configuration, the switch between the output terminals is arranged between the output terminal of the operational amplifier and the output terminal of the correlated double sampling circuit, and is shut off during the auto zero operation.

  Therefore, a phenomenon in which the auto-zero operation is disturbed depending on the input / output signal due to a shift in operation timing between a circuit other than the correlated double sampling circuit including the correlated double sampling circuit as a component and the correlated double sampling circuit. Can be avoided.

The present invention is not limited to the circuit having the above structure, and can be widely applied to general electronic devices.

  As described above, the switched capacitor circuit that performs auto-zero according to the present invention can include a sampling circuit for an input signal only with passive elements. Therefore, there is an effect that broadband sampling can be performed.

  The switched capacitor circuit of the present invention can increase the amplification factor in the switched capacitor circuit that does not constitute a feedback circuit. In addition, there is an effect that the amplification factor of the entire circuit can be increased while enabling operation in a wide band.

[Embodiment 1]
An embodiment of the present invention will be described with reference to FIGS.

  First, based on FIG. 1, the structure of the SCA circuit 10 in this Embodiment is demonstrated.

  FIG. 1 is a circuit diagram showing a configuration of the SCA circuit 10. As shown in FIG. 1, the SCA circuit 10 includes an amplifier circuit PRE-AMP1, an operational amplifier circuit OPAMP1, a plurality of switches, and a plurality of capacitors.

  The SCA circuit 10 includes two amplifier circuits PRE-AMP1 having an amplification factor (DC gain) at a low frequency and a zero frequency of greater than 1 and less than 20, and an operational amplifier circuit OPAMP1 having a sufficiently large DC gain. It has two amplifier circuits.

The SCA circuit 10 includes five switches SW1A, SW2, SW1B, SW3, and SW5. The SW1A is a switch for short-circuiting / cutting off the non-inverting input terminal of the amplifier circuit PRE-AMP1 and the ground level. The SW2 is a switch for connecting the one terminal of the capacitor C _S to the ground level or the input terminal V _IN. The SW1B is a switch for short-circuiting / blocking the inverting input terminal and the output terminal of the OPAMP1 circuit. The SW3 is a switch for connecting the output terminal of one terminal pin _{V REF} or OPAMP1 circuit reference voltage signal is supplied to the capacitor _{C F.} The SW5 is a switch for short-circuiting and disconnecting the output terminal of an external capacitive load C _L and the SCA circuits 10.

The SCA circuit 10 includes three capacitors C _S , C _C , and C _F. The capacitor _CS is a capacitor for sampling the electric charge according to the input signal. The capacitor _{C C} is a capacitor for connecting the inverted input terminal of the output terminal and the OPAMP1 circuit of the PRE-AMP1 circuit. The capacitor C _F is with sampling the charge corresponding to the reference voltage signal, a capacitor to receive a transfer of charge from the capacitor C _S.

  Next, the operation of the SCA circuit 10 will be described with reference to FIG. The SCA circuit 10 has a sampling phase PHASE-S and a hold phase PHASE-H as operation phases.

  First, the switch short-circuit / shut-off state in each phase will be described, and then the sampling operation will be described. The switch connection state in FIG. 1 indicates the state of the SCA circuit 10 in the sampling phase PHASE-S. In the hold phase PHASE-H of the SCA circuit 10, the switches SW1A and SW1B are cut off, the switches SW2 and SW3 are switched to the other terminal, and the switch SW5 is short-circuited.

Here, the capacitors C _S and C _{F of the} SCA circuit 10 sample the charge according to the input signal V _IN and the charge according to the reference voltage signal V _REF , and PRE-AMP1 which is an active element for the sampling operation. The circuit and the OPAMP1 circuit are not involved.

That is, the SCA circuit 10 is composed of only passive elements (capacitors C _S , C _F , switches SW1A, SW2, and SW3) whose input signal sampling circuit is configured in the sampling phase PHASE-S. The

  Then, the bandwidth at the sampling phase in this case of the SCA circuit 10 is

become that way. It can be seen that this equation does not include the transconductance gm. Here, the voltages applied to the capacitors C _S and C _F of the SCA circuit 10 asymptotically approach (settle) to a desired voltage value with a time constant represented by the BW _PH-S1 . Furthermore, as shown in FIG. 1, and the switches SW2 and SW3 of the SCA circuit 10 is ideal, the resistance value of the switch SW1A and with _{R SW.}

Accordingly, since the transconductance gm dependency of the band BW _PH-S1 of the SCA circuit 10 is eliminated, there is no band limitation as in the conventional SCA circuit 100 in the sampling phase PHASE-S. Further, since the SCA circuit 10 is composed of only passive elements, it can realize a sampling operation with a low power consumption and a wide band, and is not limited by a slew rate. The passive element is a circuit that does not require a direct current such as a capacitor, an inductor, and a resistor.

Next, based on FIG. 1, the auto-zero effect on low frequency noise of the PRE-AMP1 circuit and the OPAMP1 circuit will be considered. In PHASE-S, since NET1 is 0V, the output voltage of the PRE-AMP1 circuit is −V _OS1 × A1. Here, A1 is the DC gain of PRE-AMP1, which is usually larger than 1 and smaller than 20.

Further, SW1B short-circuits NET3 and output terminal VOUT, so that the voltage at NET3 becomes VOS2. Therefore, the voltage across the capacitor Cc is −A1 · V _OS1 −V _OS2
It becomes.

The charges accumulated in the capacitors C _S and C _F are C _S × VIN and C _F × VREF, respectively. In PHASE_H, if OPAMP1 is an ideal operational amplifier circuit, the output voltage is given by the following equation.
V _OUT−H = (C _S / C _F ) · V _IN + V _REF
Therefore, low frequency noise close to DC of PRE-AMP1 and OPAMP1 does not affect the output voltage. Here, the voltage sources VOS1 and VOS2 shown in FIG. 1 are modeled on mismatches between the transistors constituting PRE-AMP1 and OPAMP1 and 1 / f noise, respectively, and the voltage sources are actually arranged. Not.

  In the SCA circuit 10, the PRE-AMP1 circuit has one stage and the OPAMP1 circuit has one stage. FIG. 2 is a circuit diagram showing an SCA circuit 20 when an amplifier circuit is provided in a total of four stages of two PRE-AMP stages and two OPAMP stages as an example of such a multi-stage configuration.

  Next, the configuration of the SCA circuit 20 will be described with reference to FIG.

  The configuration other than that described in the present embodiment is the same as that of the SCA circuit 10 described above. For convenience of explanation, members having the same functions as those shown in the drawing of the SCA circuit 10 are given the same reference numerals, and explanation thereof is omitted.

  As shown in FIG. 2, the SCA circuit 20 includes an amplifier circuit PRE-AMP1, an amplifier circuit PRE-AMP2, an operational amplifier circuit OPAMP1, an operational amplifier circuit OPAMP2, a plurality of switches, and a capacitor.

  The SCA circuit 20 includes an amplifier circuit PRE-AMP1 and an amplifier circuit PRE-AMP2 having a DC gain of about 1 to 20, and an operational amplifier circuit OPAMP1 and an operational amplifier circuit OPAMP2 having sufficiently large DC gains as amplifier circuits. It has two amplifier circuits.

  The SCA circuit 20 includes seven switches SW1A1, SW1A2, SW2, SW1B1, SW1B2, SW3, and SW5.

  The SW1A1 and SW1A2 are switches for short-circuiting / cutting off the non-inverting input terminal of the PRE-AMP1 circuit and the PRE-AMP2 circuit and the ground level.

  The SW1B and SW1B2 are switches for short-circuiting / cutting off the inverting input terminal and the output terminal of the OPAMP1 circuit and the OPAMP2 circuit.

  Other switches are the same as those of the SCA circuit 10 described above.

The SCA circuit 10 includes six capacitors C _S , C _CC1 , C _CC2 , C _CC3 , C _F and C _COMP .

The capacitors C _CC1 , C _CC2 , and C _CC3 are capacitors for connecting the output terminals of the two PRE-AMP circuits and the inverting input terminals of the two OPAMP circuits, respectively.

The C _COMP is a phase compensation capacitor described below.

  Other capacitors are the same as in the case of the SCA circuit 10.

  Next, the operation of the SCA circuit 20 will be described with reference to FIG.

  First, the switch short-circuit / shut-off state in each phase will be described, and then the sampling operation will be described.

  The switch connection state in FIG. 2 shows the state of the SCA circuit 20 in the sampling phase PHASE-S. In the hold phase PHASE-H of the SCA circuit 20, the switches SW1A1, SW1A2, SW1B1, and SW1B2 are cut off, the switches SW2 and SW3 are switched to the other terminal, and the switch SW5 is short-circuited.

Here, the capacitors C _S and C _{F of the} SCA circuit 20 sample the charge according to the input signal _VIN and the charge according to the reference voltage signal V _REF , and PRE-AMP1 which is an active element for the sampling operation. The circuit, PRE-AMP2 circuit, OPAMP1 circuit, and OPAMP2 circuit are not involved.

That is, the SCA circuit 20 is composed only of passive elements (capacitors C _S , C _F , switches SW1A, SW2, and SW3) in which the input signal sampling circuit configured by the sampling phase PHASE-S includes switches and capacitors. The

Then, the band BW _{PH-S2 in} the sampling phase in this case of the SCA circuit 20 is the same as the number 4 in the case of the SCA circuit 10.

Accordingly, since the transconductance gm dependency of the band BW _PH-S2 of the SCA circuit 20 is eliminated, there is no band limitation as in the conventional SCA circuit 100 in the sampling phase PHASE-S. Further, since the SCA circuit 20 is composed of only passive elements, it is possible to realize a sampling operation with a low power consumption and a wide band, and there is no limitation due to a slew rate.

  However, the SCA circuit 20 has a problem that stability is deteriorated because multi-stage amplifiers are connected in series in the hold phase PHASE-H.

Therefore, it is necessary to add a configuration for phase compensation as shown in FIG. In the SCA circuit 20, the amplification ratio is low and the PRE-AMP1 circuits and PRE-AMP2 circuit are connected in series via a capacitor _{C C1.}

On the other hand, in the SCA circuit 20, the amplification ratio is high (due to the application is generally has an amplification factor, such as 60 dB) the operational amplifier OPAMP1 and the OPAMP2 is connected in series through the capacitor _{C C3.} The capacitor _{C C2} is disposed between the PRE-AMP2 circuit and OPAMP1 circuit.

Here, as shown in FIG. 2, in the SCA circuit 20, a phase compensation capacitor C _comp and a phase compensation resistor R _comp are arranged in order to stabilize the feedback path in the hold phase PHASE-H.

  In the SCA circuit 20, since many amplifier circuits and / or operational amplifier circuits can be connected in series, the DC gain when the output terminal of the OPAMP2 circuit is viewed from the PRE-AMP1 circuit can be greatly increased. And a highly accurate SCA circuit can be realized.

  In the case of a plurality of PRE-AMP circuits and a plurality of OPAMP circuits, if the first stage is a PRE-AMP circuit and the last stage is an OPAMP circuit, the other orders may be changed.

  FIG. 3 is a circuit diagram showing an SCA circuit 30 as one example.

  The SCA circuit 30 is the same as the SCA circuit 10 and the SCA circuit 20 except that the arrangement of the four amplifier circuits is changed.

  The present invention is not limited to the SCA circuit that forms the feedback circuit in the hold phase, as shown in the second embodiment, and can be used in a comparator that does not need to form a feedback circuit. It is.

  Further, although the first embodiment has been described using a single-ended circuit for the sake of simplicity, the present invention is not limited to a single-ended circuit. When a highly accurate circuit is configured, a fully differential circuit is usually used. Embodiment 3 shows an example of an SCA circuit using a fully differential circuit.

  Note that a single-ended circuit is a circuit having one output terminal of a differential amplifier circuit, while a fully differential circuit is a circuit having two output terminals and symmetry.

[Embodiment 2]
Next, another embodiment of the present invention will be described with reference to FIG. Configurations other than those described in the present embodiment are the same as those in the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and explanation thereof is omitted.

  First, the configuration of a switched capacitor comparator (hereinafter referred to as “SCC circuit 40”) according to a second embodiment of the present invention will be described with reference to FIG.

  The SCC circuit 40 includes two operational amplifier circuits, two switches, one capacitor, and a comparator (comparison circuit) connected to the subsequent stage.

  The SCC circuit 40 includes an amplifier circuit PRE-AMP1 and an operational amplifier circuit PRE-AMP2 as amplifier circuits.

  The SCC circuit 40, as switches, shorts / cuts off the switch SW1A for short-circuiting / cutting off the differential input terminals of the circuit PRE-AMP1, and short-circuiting / cutting off the inverting input terminal and the non-inverting input terminal of the PRE-AMP2 circuit. SW1B.

Also, the SCC circuit 40, the capacitor, the capacitor _{C C} for connecting the inverting input terminal of the output terminal and the PRE-AMP2 circuit of the PRE-AMP1 circuit is provided.

  The non-inverting input terminal of the comparator COMP1 is connected to the output terminal side of the PRE-AMP2 circuit of the SCC circuit 40.

  Next, the operation of the SCC circuit 40 will be described with reference to FIG.

  The SCC circuit 40 has two operation phases, a reset phase (hereinafter referred to as “PHASE-R”) and an amplification phase (hereinafter referred to as “PHASE-A”).

  First, the switch short-circuit / shut-off state in each phase will be described, and then the amplification operation will be described.

  The connection state of the switches of the SCC circuit 40 shown in FIG. 4 indicates the state in PHASE-R. In PHASE-A of the SCC circuit 40, the switches SW1A and SW1B are cut off.

In PHASE-A in the SCC circuit 40, the input signal _VIN is amplified by two operational amplifiers PRE-AMP1 and PRE-AMP2.

Next, the amplified signal is output from the output terminal of the PRE-AMP2 circuit. The signal output from the PRE-AMP2 circuit is input to the non-inverting input terminal of the comparator COMP1, and the signal is compared with a reference voltage level (here, the ground level) to which the inverting input terminal of the comparator COMP1 is connected. The The result is output as a digital value from the output terminal _DOUT .

In PHASE-R, the output voltages of the PRE-AMP1 circuit and the PRE-AMP2 circuit are V _OUT1-R = A ₁ · V _OS1 and V _OUT2-R = A ₂ / (1 + A ₂ ) V _{OS2 to} V _OS2 .
Here, the amplification factor of the PRE-AMP1 circuit the amplification factor of _A 1, PRE-AMP2 circuit and _{A 2.} In PHASE-R, a charge corresponding to the voltage V _OUT1-R −V _OUT2-R is held between the capacitors Cc.

The output voltage of the PRE-AMP1 circuit in PHASE-A is V _OUT1-A = (V _IN + V _OS1 ) · A1
It becomes.

Therefore, from these two equations, the output voltage of the PRE-AMP2 circuit in PHASE-A can be expressed by the following equation: V _OUT2−A = A1 · A2 · V _IN
From this equation, it can be seen that the output voltage of the SCC circuit 40 is not affected by the current source V _OS1 and the current source V _OS2 .

  Therefore, the output voltage of the SCC circuit 40 is not easily affected by the offset voltage and low frequency noise of the PRE-AMP1 circuit and the PRE-AMP2 circuit.

By adopting such a configuration, the SCC circuit 40 does not have a feedback circuit on the input terminal _VIN side during PHASE-R, and can perform high-speed reset and signal tracking. Therefore, the SCC circuit 40 can operate in a wide band.

The configuration of the SCC circuit 40 is basically similar to the configuration of the conventional SCA circuit 110. Therefore, since the SCA circuit 110 does not have a feedback circuit on the input terminal _VIN side, high-speed resetting and signal tracking are possible.

  However, when the amplifier circuit is configured in multiple stages like the SCC circuit 40, the amplification factor A2 of the PRE-AMP2 circuit can be increased while the amplification factor A1 of the PRE-AMP1 circuit in the previous stage is reduced. Therefore, the amplification factor of the entire circuit of the SCC circuit 40 can be made larger than that of the conventional SCA circuit 110.

  Further, since the PRE-AMP2 circuit of the SCC circuit 40 is short-circuited between the input and output terminals, there is an advantage that the voltage of the output terminal is not saturated in the reset phase PHASE-R.

[Embodiment 3]
Still another embodiment of the present invention will be described with reference to FIGS. Configurations other than those described in the present embodiment are the same as those in the first and second embodiments. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 and 2 are given the same reference numerals, and descriptions thereof are omitted.

  FIG. 5 is a circuit diagram showing a CDS circuit 50 according to still another embodiment of the present invention. Here, the CDS circuit is a circuit that enables correlated double sampling.

  The CDS circuit 50 is an example in which the present invention is applied to a CDS circuit for a CCD (charge coupled device, the same applies hereinafter) image sensor.

  First, the configuration of the CDS circuit 50 will be described with reference to FIG.

  The CDS circuit 50 includes an amplifier circuit PRE-AMP1, an operational amplifier circuit OPAMP1, a plurality of switches, and a plurality of capacitors.

  Further, as shown in FIG. 5, the CDS circuit 50 is constituted by a fully differential circuit, and has a vertically symmetrical circuit configuration.

  Accordingly, only the upper side of the symmetrical CDS circuit 50 will be described here, and the description of the lower side will be omitted. Non-symmetric parts will be described below.

  Specifically, the amplifier circuit of the CDS circuit 50 includes a fully differential amplifier circuit PRE-AMP1 having a DC gain larger than 1 and smaller than 20, and a fully differential operational amplifier circuit OPAMP1 having a sufficiently large DC gain. It is composed of

  Since the CCD image sensor output is usually single-ended, the output is connected to one input terminal of the CDS circuit, and the other is connected to the ground level or the like. Therefore, the CDS circuit 50 converts the single-ended CDS image sensor output into a fully differential output.

The CDS circuit 50 includes five capacitors C _S , C _F , C _C , C _R , and C _L.

The capacitor _CS is a capacitor for sampling the output signal of the CCD image sensor.

The capacitor C _F is the capacitor charges the capacitor C _S is sampled is transported.

The capacitor _{C C} is a capacitor for connecting the inverted input terminal of the inverting output terminal and OPAMP1 circuit of the PRE-AMP1 circuit.

The capacitor _{C R} is provided between the inverting input terminal and the non-inverting output terminal of the OPAMP1 circuit, a reset capacitor of OPAMP1 circuit connected through the switch SW1B1 and SW1B2, described below.

The capacitor C _L is a load capacitor of the CDS circuit is a sampling capacitor which is arranged in the next stage of the CDS circuit 50.

In order to make the amplification factor of the CDS circuit 50 variable, for example, a variable capacitor in which _CF is composed of a plurality of capacitors and switches may be used.

  The CDS circuit 50 includes a total of 13 switches SW1A, SW1B1, SW1B2, SW2, SW3, SW4, and SW5, including symmetric and asymmetric ones.

  SW1A and SW2 are switches that conduct in PHASE-S.

The SW3, respectively one terminal of the capacitor _{C F} in PHASE-S and PHASE-H is a switch that connects the terminals _{V REFP} and _{V OUTP.}

The switch SW1B1 and SW1B2 is, PHASE-S and PHASE-H in the capacitor _{C R,} respectively terminals _V CMI both sides of the _{terminal, V CMO,} a switch connected to the output terminal of one terminal, and OPAMP1 circuit of the capacitor _{C C} is there.

The switch SW4 is a switch for connecting the non-inverting output terminal of OPAMP1 circuits in PHASE-H to the output terminal _{V OUTP.}

The switch SW5 is a switch for short-circuiting the output terminal _{V OUTP} and the next stage of the sampling capacitor _{C L} in one phase PHASE-H2.

  Next, examples of the PRE-AMP1 circuit and the OPAMP1 circuit in the CDS circuit 50 are shown in FIGS. 6 and 8, respectively.

  FIG. 6 is a circuit diagram showing a configuration of the PRE-AMP1 circuit in the CDS circuit. FIG. 8 is a circuit diagram showing the configuration of the OPAMP1 circuit in a general switched capacitor circuit.

  As shown in FIG. 6, in the PRE-AMP1 circuit of the CDS circuit 50, a PMOS differential pair (transistors M1P and M1M) and a PMOS (transistor M1C) which is a tail current source for supplying a constant current to the differential pair. And NMOS transistors (transistors M2M, M2P, M2CP, and M2CM) that are active loads of the differential pair.

Here, by changing the size of the active load NMOS of PRE-AMP1 shown in FIG. 6 according to the amplification factor G = C _S / C _F of the CDS circuit 50, the stability of the feedback loop during PHASE-H is improved. The trade-off with the bandwidth can be improved (see Non-Patent Document 2).

  The variable-size active load NMOS can be easily configured in the same manner as the slide “PGA Amplifier Design” of Non-Patent Document 2.

  As shown in FIG. 8, in the OPAMP1 circuit of the CDS circuit 50, an NMOS differential pair (transistors M3P and M3M) and an NMOS (transistor M3C) which is a tail current source for supplying a constant current to the differential pair. And PMOS transistors (transistors M4M and M4P) serving as active loads of the differential pair.

  Next, the operation of the CDS circuit 50 will be described with reference to FIG.

  The CDS circuit 50 has a sampling phase PHASE-S and a hold phase PHASE-H as operation phases.

  The switch connection state in FIG. 5 indicates the state in the sampling phase PHASE-S.

The CDS circuit 50, when the sampling phase PHASE-S, charges corresponding to the reset signal level of the PRE-AMP1 circuit and OPAMP1 circuit simultaneously CCD image sensor is performed auto zero operation of the sampling capacitor _{C S} is sampled.

Meanwhile, the CDS circuit 50, the hold phase PHASE-H, the difference between the pixel data signal level and the reset signal level of the CCD image sensor is output after being amplified output terminal _{V OUTP} and _{V OUTM.} Moreover, sampling the charges next stage capacitive load capacitor _{C L} of the CDS circuit 50 in accordance with the output signal _{V OUTP} and _{V OUTM.}

The CDS circuit 50 has a two-stage configuration of a PRE-AMP1 circuit and an OPAMP1 circuit, so that even when the amplification factor of the CDS circuit = C _S / C _F is increased, the PHASE − The bandwidth in H can be greatly improved (see Non-Patent Document 3).

  On the other hand, for the same reason as described in the first embodiment, in the CDS circuit 50, an input conversion offset voltage (DC offset) of the PRE-AMP1 circuit and the OPAMP1 circuit is ideally an active element constituting the amplifier circuit. Assuming that

The sampling circuit for sampling the charge corresponding to the CCD image sensor output signal of the CDS circuit 50 is constituted only by passive elements (capacitors _{C S} and the switch SW1A).

  Therefore, the CDS circuit 50 can reduce the time constant of the sampling circuit without increasing the power consumption by increasing the channel width of the MOSFET constituting the switch SW1A. The CDS circuit 50 can also sample the output signal that changes rapidly with high accuracy.

  Further, since the common mode voltage (voltage in the regions NET1P and NET1M on the input terminal side of the PRE-AMP1 circuit in FIG. 5) of the input terminal of the PRE-AMP1 circuit of the CDS circuit 50 can be lowered, it is small in the switch SW1A. A low-resistance switch with a transistor size can be realized.

  Further, regarding the kTC and thermal noise, the CDS circuit 50 can achieve the same level of noise reduction as compared with the case where the CDS circuit is constructed based on the conventional SCA circuit 100 of FIG.

Further, in the CDS circuit 50, and a switch SW4 provided between the output terminal of OPAMP1 circuit and the signal output terminal _{V OUTP} and _{V OUTM.}

  Hereinafter, the reason why the switch SW4 is provided will be described.

  First, in the analog front end for an image sensor, the CDS circuit 50 operates at a timing according to the output signal in order to efficiently sample charges according to the output signal of the CCD image sensor. The circuit operates at another timing.

Therefore, in the CDS circuit 50, just before the PRE-AMP1 circuit and OPAMP1 circuit terminates the auto-zero in the PHASE-S, there is a possibility that the capacitive load _{C L} is connected to the output terminal of OPAMP1 circuit.

  In the following, a shift in operation timing between the CDS circuit 50 and the circuits after the CDS circuit 50 will be described with reference to FIG.

  FIG. 9 is a timing chart showing the operation timing of the CCD output signal, PHASE-S, PHASE-H, and PHASE-H2 in the CDS circuit 50.

As shown in FIG. 9, the charge that depends on the voltage the CDS circuit 50 is amplified is accumulated in the PHASE-H immediately before the capacitor _{C L} when the PHASE-H2 has a low voltage. Usually, the operation timing of the CDS circuit is different from the operation timing of the switched capacitor circuit arranged in the subsequent stage, so PHASE-S and PHASE-H2 are simultaneously at a high voltage. At this time, if without the switch SW4, which is downstream of the sampling volume of the CDS circuit 50 _{C L} interferes with auto-zero operation of the CDS circuit 50.

  That is, a large distortion occurs in the output signal of the CDS circuit 50. In order to avoid this, the switch SW4 is provided in the CDS circuit 50.

The switch SW4 is in the feedback path comprising the PHASE-H PRE-AMP1 circuit, the capacitor _C C, OPAMP1 circuit and the capacitor _{C F,} is arranged immediately before the output terminal _{V OUTP} and _{V OUTM.} For this reason, the influence of the on-resistance distortion of the switch SW4 on the settling characteristics is small.

Further, in the CDS circuit 50 are short-circuited through a capacitor _{C R,} which is biased to a potential difference _(V CMO _{-V CMI)} with an inverting input terminal and the non-inverting output terminal of OPAMP1 circuit. This is because the common mode voltage of the input terminal and the output terminal of the OPAMP1 circuit of the CDS circuit 50 is different. When the common mode voltage of the input terminal and the output terminal of the OPAMP1 circuit of the CDS circuit 50 is the same, it is only necessary to short-circuit with a switch.

Further, in the CDS circuit 50, there is little charge is transferred from capacitor _{C C} between the PHASE-S and PHASE-H. Therefore, in the CDS circuit 50, the inverting and non-inverting output of OPAMP1 circuit be connected capacitor _{C R} to the OPAMP1 circuit side in PHASE-S is a value close to the voltage value of the output terminal _{V CMO.}

Next, the band characteristics of the CDS circuit 50 will be described. The resistance value between the switches SW1A and regions NET1P and NET1M through the SW2 and 2 · _{R SW,} the resistance value of the switch SW3 zero, the output impedance of the CCD sensor output driver to zero. If it does so, it will become the same result as the number 4 derived | led-out by the said Embodiment 1 after all.
That is, the band BW _PH-S3 = BW _PH-S1 .

Accordingly, as in the case of the first embodiment, the band BW _PH-S3 of the input signal sampling circuit in the PHASE-S of the CDS circuit 50 has no dependency on the transconductance gm of the PRE-AMP1 and the OPAMP1. In the sampling phase PHASE-S, the band limitation as described above is eliminated.

〔Example〕
Now, let us consider thermal noise in the SCA circuit 60 which is an example of the first and third embodiments.

  FIG. 10 is a circuit diagram showing a configuration of the SCA circuit 60.

  The SCA circuit 60 comprises the SCA circuit 10 shown in FIG. 1 as a fully differential circuit as shown in FIG. 5, and the PRE-AMP1 circuit of the SCA circuit 10 shown in FIG. 1 as a differential amplifier circuit shown in FIG. This corresponds to the case where the OPAMP1 circuit is constituted by the operational amplifier circuit of FIG.

  Therefore, the configuration of the SCA circuit 60 is basically the same as that of the SCA circuit 10 and will not be described in detail.

  As in the case of the conventional SCA circuit 100 described above, the SCA circuit 60 generates three types of thermal noise. That is, kTC noise, auto zero noise, and hold noise.

The input conversion values of these noises to the input terminal V _IN (V _INP −V _INM ) in the SCA circuit 60 are shown in Table 2 (actual values are obtained by doubling the values in Table 2; In order to simplify the comparison, the actual value is shown here as 1/2). Table 2 shows theoretical values of noise in the SCA circuit 60 and approximate values thereof. When the amplification factor of the SCA circuit 60 is large, it means that a desired input signal may be small. When the input signal is small, low input conversion noise of the SCA circuit 60 is required.

Therefore, in Table 2, an approximate value was derived on the assumption that the gain G = Cs / C _F >> 1 between the input and output of the SCA circuit 60 and the constant γ = 1.

  Where gm1 is the transconductance of transistors M1P and M1M in FIG. 7, gm2 is the transconductance of transistors M2P and M2M in FIG. 7, gm2c is the transconductance of transistors M2CP and M2CM in FIG. 7, and gm3 is the transistor M3P in FIG. M3M transconductance and gm4 represent the transconductances of the transistors M4P and M4M in FIG.

In the SCA circuit 60, when the amplification factor G is set to be large in the hold noise, the value of the transconductance ratio gm3 / gm2 is increased accordingly, so the constant γ OPAMP becomes a large value of 5 to 10 _. (When G is about 6). The hold noise is larger than the values in Table 1.

However, in the SCA circuit 60, since the term (gm2 / gm1) ² is included in the auto-zero noise equation, the auto-zero noise is smaller than the values in Table 1. Therefore, the total value of the auto zero noise, hold noise, and kTC noise in the SCA circuit 60 can be set to the same amount of noise as the conventional SCA circuit 100.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and the present invention can be obtained by appropriately combining technical means disclosed in different embodiments. Such embodiments are also included in the technical scope of the present invention.

  The present invention can be widely applied to a switched capacitor circuit that performs auto-zero and electronic devices using the same. Specifically, the present invention can also be applied to a correlated double sampling circuit used for an image sensor module, an analog front end of an audio signal processing system, and an electronic device using the same. In addition, any circuit that needs to perform broadband sampling may be used, and it can be widely applied to electronic devices including these circuits.

It is a circuit diagram which shows one Embodiment of the switched capacitor circuit in this invention. It is a circuit diagram which shows other embodiment of the switched capacitor circuit in this invention. It is a circuit diagram which shows other embodiment of the switched capacitor circuit in this invention. It is a circuit diagram which shows other embodiment of the switched capacitor circuit in this invention. It is a circuit diagram which shows one Embodiment of the CDS circuit in this invention. It is a circuit diagram which shows the structure of the differential amplifier circuit in the said CDS circuit. It is a circuit diagram which shows the structure of the differential amplifier circuit in the said switched capacitor circuit. It is a circuit diagram which shows the structure of the operational amplifier circuit in the said switched capacitor circuit. It is a timing chart figure about operation of the above-mentioned CDS circuit. It is a circuit diagram which shows the Example in this invention. It is a circuit diagram which shows an example of the conventional switched capacitor circuit. It is a circuit diagram which shows another example of the conventional switched capacitor circuit. It is a circuit diagram which shows the structure of the operational amplifier circuit in the said conventional switched capacitor circuit.

Explanation of symbols

10 SCA circuit (switched capacitor circuit)
20 SCA circuit (switched capacitor circuit)
30 SCA circuit (switched capacitor circuit)
40 SCC circuit (switched capacitor circuit)
50 CDS circuit (correlated double sampling circuit)
60 SCA circuit (switched capacitor circuit)
C _C capacitor (between input and output capacitor)
C _C1 capacitor (capacitor between input and output)
C _C2 capacitor (capacitor between input and output)
C _C3 capacitor (capacitor between input and output)
_CF capacitor (transfer charge capacitor)
_CL capacitor _CR capacitor (bias capacitor)
_CS capacitor (sampling capacitor)
C _COMP phase compensation capacitor (phase compensation capacitor)
M1C transistor M1M transistor M1P transistor M2CM transistor M2CP transistor M2P transistor M2M transistor M3M transistor M3P transistor M4M transistor M4P transistor OPAMP1 operational amplifier (amplifier operational amplifier)
OPAMP2 operational amplifier (amplifier operational amplifier)
PRE-AMP1 differential amplifier (amplifier preamplifier)
PRE-AMP2 differential amplifier (amplifier preamplifier)
R _COMP phase compensation resistor SW1A switch (differential input short-circuit switch)
SW1A1 switch (differential input short-circuit switch)
SW1A2 switch (differential input short-circuit switch)
SW1B switch (I / O short-circuit switch)
SW1B1 switch (I / O short-circuit switch)
SW1B2 switch (I / O short-circuit switch)
SW2 switch (signal input switch)
SW3 switch (output side switch)
SW4 switch (switch between output terminals)
SW5 switch V _CMI terminal V _IN input terminal or input voltage (signal input terminal)
V _OS1 voltage source V _OS2 voltage source V _OUT output terminal or output voltage (signal output terminal)
V _OUTM output terminal or output voltage (signal output terminal)
V _OUTP output terminal or output voltage (signal output terminal)
V _REF reference voltage terminal or reference voltage V _REFM reference voltage terminal or reference voltage V _REFP reference voltage terminal or reference voltage

Claims (14)

M (M is 1 or more) amplifier circuit preamplifiers having differential input terminals and N (N is 1 or more) amplifier circuit operational amplifiers having differential input terminals between a signal input terminal and a signal output terminal Are connected in series,
Among the plurality of amplifier circuits, an amplifier circuit preamplifier is disposed as the first stage amplifier circuit, and an amplifier circuit operational amplifier is disposed as the last stage amplifier circuit.
And M + N−1 input / output capacitors for connecting the input / output terminals of the M + N amplifier circuits connected in series to each other;
A sampling capacitor disposed between the differential input terminal of the amplifier circuit preamplifier and the signal input terminal for sampling an input signal;
A transfer charge capacitor disposed between the differential input terminal of the first stage amplifier circuit preamplifier and the signal output terminal;
M differential input short-circuit switches for short-circuiting the two differential input terminals of each amplifier circuit preamplifier;
A switched capacitor circuit having N input / output short-circuit switches for short-circuiting the inverting input terminal of each amplifier circuit operational amplifier and the output terminal of the amplifier circuit operational amplifier.   The capacitor biased to a certain voltage is further connected in series to any one or more of the input / output short-circuit switches of the N input / output short-circuit switches. Switched capacitor circuit. An amplifier circuit preamplifier having a differential input terminal and an amplifier circuit operational amplifier having a differential input terminal are connected in series between the signal input terminal and the signal output terminal,
An input-output capacitor connecting the output terminal of the amplifier circuit preamplifier and the input terminal of the amplifier circuit operational amplifier;
A differential input short-circuit switch for short-circuiting the two differential input terminals of the amplifier circuit preamplifier;
A switched capacitor circuit having an input / output short-circuit switch for short-circuiting an inverting input terminal of the amplifier circuit operational amplifier and an output terminal of the amplifier circuit operational amplifier.   4. The switched capacitor circuit according to claim 3, wherein a capacitor biased to a certain voltage is further connected in series to the input / output short-circuit switch.   5. The switched capacitor circuit according to claim 1, wherein the amplification circuit preamplifier is an amplification circuit in which an amplification factor between input and output is larger than 1 and smaller than 20. 5.   The switched capacitor circuit according to claim 1, wherein the amplifier circuit operational amplifier has an input signal as a voltage and an output signal as a current. As operation phases, there are a first phase for performing auto-zero operation, and a second phase for amplifying the input signal of the switched capacitor circuit,
The sampling capacitor performs sampling of the input signal in the first phase,
3. The switched capacitor circuit according to claim 1, wherein the charge transfer capacitor transfers the sampled charge to the first sampling capacitor in the second phase. As operation phases, there are a first phase for performing auto-zero operation, and a second phase for amplifying the input signal of the switched capacitor circuit,
In the first phase, the first capacitor is disposed between the input terminal of the amplifier circuit preamplifier and the signal input terminal and performs sampling of the input signal;
In the second phase, the charge that is sampled is transferred to the first capacitor while being arranged between the input terminal of the amplifier circuit preamplifier and the output terminal of the amplifier circuit operational amplifier arranged at the end of the series connection. 5. The switched capacitor circuit according to claim 3 or 4, further comprising a charge transfer capacitor. M (M is 1 or more) first amplifier circuits and N (N is 1 or more) second amplifier circuits are connected in series between the signal input terminal and the signal output terminal. With configuration,
M + N−1 input / output capacitors for connecting the input / output terminals of the M + N amplifier circuits connected in series to each other;
A sampling capacitor for sampling an input signal, disposed between the input terminal of the first stage amplifier circuit among the M + N amplifier circuits and the signal input terminal;
A transfer charge capacitor disposed between an input terminal of the first stage amplifier circuit and the signal output terminal;
A switched capacitor circuit having N input / output short-circuit switches for short-circuiting the input terminal of each amplifier circuit and the output terminal of the amplifier circuit. In a correlated double sampling circuit having a configuration in which an amplifier preamplifier having a differential input terminal and an amplifier operational amplifier having a differential input terminal are connected in series,
An input-output capacitor disposed between the output terminal of the amplifier circuit preamplifier and the input terminal of the amplifier circuit operational amplifier;
A differential input short-circuit switch for short-circuiting the two differential input terminals of the amplifier circuit preamplifier;
An input / output short-circuit switch for short-circuiting the inverting input terminal of the amplifier circuit operational amplifier and the output terminal of the amplifier circuit operational amplifier;
A correlated double sampling circuit comprising: a sampling capacitor directly connected between the input terminal of the amplifier circuit preamplifier and the signal input terminal without a switch.   11. The correlated double sampling circuit according to claim 10, wherein a capacitor biased to a certain voltage is further connected in series to the input / output short-circuit switch.   12. The correlated double sampling circuit according to claim 11, wherein a switch between output terminals is arranged between an output terminal of the amplifier circuit operational amplifier and an output terminal of the correlated double sampling circuit.   The electronic device using the switched capacitor circuit of any one of Claims 1-9.   The electronic device using the correlation double sampling circuit of any one of Claims 11-12.

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