TWI397258B - Operational amplifier - Google Patents
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- TWI397258B TWI397258B TW99118716A TW99118716A TWI397258B TW I397258 B TWI397258 B TW I397258B TW 99118716 A TW99118716 A TW 99118716A TW 99118716 A TW99118716 A TW 99118716A TW I397258 B TWI397258 B TW I397258B
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Description
本發明是有關於一種放大器，特別是指一種運算放大器。The present invention relates to an amplifier, and more particularly to an operational amplifier.
習知的一種管線式類比/數位轉換裝置以共享運算放大器的架構，將一輸入電壓轉換成一相對應的數位信號，來節省功率和面積的成本。A conventional pipeline analog/digital conversion device converts an input voltage into a corresponding digital signal in a shared operational amplifier architecture to save power and area costs.
但是上述類比/數位轉換裝置的缺點為：所共享運算放大器的輸入差動對的閘極電容因前一次的電荷注入，會留下殘值記憶效應，而降低整體的效能。However, the above analog/digital conversion device has the disadvantage that the gate capacitance of the input differential pair of the shared operational amplifier will leave a residual value memory effect due to the previous charge injection, and the overall performance is lowered.
如圖1所示，美國專利第6,759,898 B1號”dual input differential amplifier”提出一種避免殘值記憶效應的運算放大器。當控制信號phi1=1、phi2=0時，第一電路1遭致能以接收一對差動輸入信號inp1、inn1；而當控制信號phi1=0、phi2=1時，第二電路2遭致能以接收另一對差動輸入信號inp2、inn2。因為該二對輸入差動信號遭分開，所以彼此之間不會存在電荷共享，而達到解決殘值記憶效應的目的。As shown in FIG. 1, U.S. Patent No. 6,759,898 B1 "dual input differential amplifier" proposes an operational amplifier that avoids residual value memory effects. When the control signals phi1=1, phi2=0, the first circuit 1 is enabled to receive a pair of differential input signals inp1, inn1; and when the control signals phi1=0, phi2=1, the second circuit 2 is caused It is possible to receive another pair of differential input signals inp2, inn2. Because the two pairs of input differential signals are separated, there is no charge sharing between them, and the purpose of solving the residual memory effect is achieved.
但是上述運算放大器的缺點為：使用尾電流源200，將限制差動輸出信號的振幅，而降低電路可容忍雜訊的大小。However, the above operational amplifier has the disadvantage that the use of the tail current source 200 limits the amplitude of the differential output signal and reduces the size of the circuit that can tolerate noise.
因此，本發明之目的，即在提供一種避免限制差動輸出信號的振幅、增加可容忍雜訊及減少功率消耗的運算放大器。Accordingly, it is an object of the present invention to provide an operational amplifier that avoids limiting the amplitude of the differential output signal, increasing tolerable noise, and reducing power consumption.
該運算放大器，包含：一第一差動電路，電連接於地；一第二差動電路，電連接於一直流電壓和該第一差動電路之間；及一切換裝置，電連接該第一、二差動電路，且該切換裝置選擇性地使各差動電路操作於一差動模式；其中，當該第一差動電路操作於一差動模式，會根據一第一組差動電壓輸出一第一差動電流，且該第一、二差動電路更將起阻抗作用而根據該第一差動電流產生一組差動輸出電壓；當該第二差動電路操作於該差動模式，會根據一第二組差動電壓輸出一第二差動電流，且該第一、二差動電路更將起阻抗作用而根據該第二差動電流產生該組差動輸出電壓。The operational amplifier includes: a first differential circuit electrically connected to the ground; a second differential circuit electrically connected between the DC voltage and the first differential circuit; and a switching device electrically connected to the first One or two differential circuits, and the switching device selectively operates the differential circuits in a differential mode; wherein, when the first differential circuit operates in a differential mode, the differential is based on a first group The voltage outputs a first differential current, and the first and second differential circuits further act as an impedance to generate a set of differential output voltages according to the first differential current; when the second differential circuit operates at the difference In the active mode, a second differential current is output according to a second set of differential voltages, and the first and second differential circuits further function as impedances to generate the set of differential output voltages according to the second differential currents.
本發明之另一目的，即在提供另一種運算放大器。Another object of the invention is to provide another operational amplifier.
該運算放大器，包含：一直流偏壓電路，用於產生一呈直流的第一偏壓電流；一第一差動電路，耦接該直流偏壓電路；一第二差動電路，耦接該直流偏壓電路；一切換裝置，電連接該第一、二差動電路，且該切換裝置選擇性地使各差動電路操作於一差動模式；及一共模偏壓電路，電連接該切換裝置；其中，當該第一差動電路操作於一差動模式，會耦接該直流偏壓電路以接收該第一偏壓電流，並根據一第一組差動電壓輸出一第一差動電流，且該第一、二差動電路和該共模偏壓電路該更將起阻抗作用而根據該第一差動電流產生一組差動輸出電壓；當該第二差動電路操作於該差動模式，會耦接該直流偏壓電路以接收該第一偏壓電流，並根據一第二組差動電壓輸出一第二差動電流，且該第一、二差動電路和該共模偏壓電路該更將起阻抗作用而根據該第二差動電流產生該組差動輸出電壓；且該共模偏壓電路會根據一共模控制電壓將該組差動輸出電壓的平均值維持於一預設值。The operational amplifier includes: a DC bias circuit for generating a DC bias current; a first differential circuit coupled to the DC bias circuit; and a second differential circuit coupled Connected to the DC bias circuit; a switching device electrically connecting the first and second differential circuits, and the switching device selectively operates the differential circuits in a differential mode; and a common mode bias circuit, Electrically connecting the switching device; wherein when the first differential circuit operates in a differential mode, the DC bias circuit is coupled to receive the first bias current and is output according to a first set of differential voltages a first differential current, and the first and second differential circuits and the common mode bias circuit further act as an impedance to generate a set of differential output voltages according to the first differential current; The differential circuit operates in the differential mode, coupled to the DC bias circuit to receive the first bias current, and outputs a second differential current according to a second set of differential voltages, and the first The second differential circuit and the common mode bias circuit will further act as an impedance and according to the second difference The set of differential current output voltage is generated; and the common mode voltage bias circuit based on the average common mode voltage control of the set of differential output voltage is maintained at a predetermined value.
有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之三個較佳實施例的詳細說明中，將可清楚的呈現。The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of FIG.
<第一較佳實施例><First Preferred Embodiment>
如圖2所示，本發明運算放大器之第一較佳實施例，適用於接收一第一組差動電壓和一第二組差動電壓，並進行放大以輸出一組差動輸出電壓Vo+、Vo-。且該運算放大器包含：一第一差動電路A1、一第二差動電路A2、一切換裝置T，及一增益電路G。As shown in FIG. 2, a first preferred embodiment of the operational amplifier of the present invention is adapted to receive a first set of differential voltages and a second set of differential voltages, and to amplify to output a set of differential output voltages Vo+, Vo-. The operational amplifier includes a first differential circuit A1, a second differential circuit A2, a switching device T, and a gain circuit G.
該第一差動電路A1用於將所接收的電壓轉換成電流，且包括一第一電晶體NMOS1和一第二電晶體NMOS2，該第一、二電晶體NMOS1、2分別具有一閘極、一汲極和一電連接於地的源極。The first differential circuit A1 is configured to convert the received voltage into a current, and includes a first transistor NMOS1 and a second transistor NMOS2. The first and second transistors NMOS1 and 2 respectively have a gate. A drain and a source electrically connected to the ground.
該第二差動電路A2用於將所接收的電壓轉換成電流，且包括一第三電晶體PMOS3和一第四電晶體PMOS4，該第三、四電晶體PMOS3、4分別具有一閘極、一汲極和一電連接於一直流電壓VDD的源極。The second differential circuit A2 is configured to convert the received voltage into a current, and includes a third transistor PMOS3 and a fourth transistor PMOS4. The third and fourth transistors PMOS3 and 4 respectively have a gate. A drain and an electrical source are connected to the source of the DC voltage VDD.
該切換裝置T則用以切換地傳遞該第一組差動電壓或一第一偏壓電壓Vbn到第一、二電晶體NMOS1、2的閘極，並用以切換地傳遞該第二組差動電壓或一第二偏壓電壓Vbp到PMOS3、4的閘極。較佳地，本例的第一、二組差動電壓不相同，因此於圖式中分別以(Vin1+、Vin1-)、(Vin2+、Vin2-)表示。The switching device T is configured to switchably transmit the first set of differential voltages or a first bias voltage Vbn to the gates of the first and second transistors NMOS1 and 2, and to switch the second group of differentials. The voltage or a second bias voltage Vbp is applied to the gates of the PMOSs 3, 4. Preferably, the first and second sets of differential voltages of the present example are different, and therefore are represented by (Vin1+, Vin1-), (Vin2+, Vin2-) in the drawings.
值得注意的是，當該切換裝置傳遞第一組差動電壓到第一、二電晶體NMOS1、2的閘極時，會傳遞第二偏壓電壓Vbp到第三、四電晶體PMOS3、4的閘極。而當該切換裝置T傳遞第一偏壓電壓Vbn到第一、二電晶體NMOS1、2的閘極時，會傳遞第二組差動電壓到第三、四電晶體PMOS3、4的閘極。It should be noted that when the switching device transmits the first set of differential voltages to the gates of the first and second transistors NMOS1, 2, the second bias voltage Vbp is transmitted to the third and fourth transistors PMOS3, 4. Gate. When the switching device T transmits the first bias voltage Vbn to the gates of the first and second transistors NMOS1, 2, a second set of differential voltages is transmitted to the gates of the third and fourth transistors PMOS3, 4.
而各差動電路會因為收到的信號不同，而操作於一差動模式或一偏壓模式。詳細作動情形說明如下。Each differential circuit operates in a differential mode or a bias mode because the received signal is different. The detailed action situation is explained below.
參閱圖3，當第一、二電晶體NMOS1、2的閘極分別收到第一組差動電壓Vin1+、Vin1-，第一差動電路A1會操作於差動模式而藉由該第一、二電晶體NMOS1、2的汲極輸出一第一差動電流id1。此時，由於該第三、四電晶體PMOS3、4的閘極分別收到第二偏壓電壓Vbp，所以第二差動電路A2會操作於偏壓模式而藉由第三、四電晶體PMOS3、4的汲極輸出二偏壓電流Idc1。該第一、二差動電路A1、A2更將起阻抗作用而根據該第一差動電流id1產生該組差動輸出電壓Vo+、Vo-。Referring to FIG. 3, when the gates of the first and second transistors NMOS1 and 2 respectively receive the first set of differential voltages Vin1+ and Vin1-, the first differential circuit A1 operates in the differential mode by the first The drains of the two transistors NMOS1, 2 output a first differential current id1. At this time, since the gates of the third and fourth transistors PMOS3, 4 respectively receive the second bias voltage Vbp, the second differential circuit A2 operates in the bias mode by the third and fourth transistors PMOS3. The drain of 4 outputs two bias currents Idc1. The first and second differential circuits A1 and A2 further function as impedances to generate the set of differential output voltages Vo+ and Vo− according to the first differential current id1.
參閱圖4，反之，當第一、二電晶體NMOS1、2的閘極分別收到第一偏壓電壓Vbn，第一差動電路A1會操作於偏壓模式而藉由該第一、二電晶體NMOS1、2的汲極產生二偏壓電流Idc2。此時，由於第三、四電晶體PMOS3、4的閘極分別接收該第二組差動電壓Vin2+、Vin2-，所以第二差動電路A2會操作於差動模式而藉由第三、四電晶體PMOS3、4的汲極輸出該第二差動電流id2。該第一、二差動電路A1、A2更將起阻抗作用而根據該第二差動電流id2產生該組差動輸出電壓Vo+、Vo-。Referring to FIG. 4, on the contrary, when the gates of the first and second transistors NMOS1 and 2 respectively receive the first bias voltage Vbn, the first differential circuit A1 operates in the bias mode by the first and second powers. The drains of the crystals NMOS1, 2 generate two bias currents Idc2. At this time, since the gates of the third and fourth transistors PMOS3, 4 respectively receive the second set of differential voltages Vin2+, Vin2-, the second differential circuit A2 operates in the differential mode by the third and fourth The drains of the transistors PMOS3, 4 output the second differential current id2. The first and second differential circuits A1, A2 further function as impedances to generate the set of differential output voltages Vo+, Vo- based on the second differential current id2.
回歸參閱圖2，詳細來說，該切換裝置T包括電連接第一差動電路A1的二個第一開關S1和二個第二開關S2，且包括電連接第二差動電路A2的二個第一開關S1和二個第二開關S2。每一開關皆具有一第一端、一第二端和一控制端，且各控制端受控制使相關的第一端和第二端於導通與不導通之間切換。Referring back to FIG. 2, in detail, the switching device T includes two first switches S1 and two second switches S2 electrically connected to the first differential circuit A1, and includes two electrically connected second differential circuits A2. The first switch S1 and the two second switches S2. Each switch has a first end, a second end and a control end, and each control end is controlled such that the associated first end and the second end switch between conducting and non-conducting.
電連接第一差動電路A1的二個第一開關S1，會藉由各自的第一端分別接收該第一組差動電壓Vin1+、Vin1-，且藉由各自的第二端分別電連接該二電晶體NMOS1、2的閘極。The first switch S1 of the first differential circuit A1 is electrically connected to the first set of differential voltages Vin1+, Vin1- by the respective first ends, and is electrically connected by the respective second ends. The gate of the two transistors NMOS1, 2.
電連接第一差動電路A1的二個第二開關S2，會藉由各自的第一端分別接收第一偏壓電壓Vbn，且藉由各自的第二端分別電連接該二電晶體NMOS1、2的閘極。The two second switches S2 electrically connected to the first differential circuit A1 respectively receive the first bias voltage Vbn by the respective first ends, and are electrically connected to the two transistors NMOS1 by the respective second ends. 2 gates.
另一方面，電連接第二差動電路A2的二個第一開關S1，會藉由各自的第一端分別接收第二偏壓電壓Vbp，且藉由各自的第二端分別電連接該二電晶體PMOS3、4的閘極。On the other hand, the two first switches S1 electrically connected to the second differential circuit A2 respectively receive the second bias voltage Vbp by the respective first ends, and are electrically connected to the second terminals by the respective second ends. The gates of the transistors PMOS3, 4.
電連接第二差動電路A2的二個第二開關，會藉由各自的第一端分別接收該第二組差動電壓Vin2+、Vin2-，且藉由各自的第二端分別電連接該二電晶體PMOS3、4的閘極。The two second switches electrically connected to the second differential circuit A2 respectively receive the second set of differential voltages Vin2+, Vin2- by respective first ends, and are electrically connected to the second ends by respective second ends. The gates of the transistors PMOS3, 4.
該切換裝置T根據一控制信號來控制，使得所有第一開關S1同步導通或不導通，也使得所有第二開關S2同步導通或不導通。且值得注意的是，第一、二開關S1、S2的導通期間不會互相重疊(overlap)。The switching device T is controlled according to a control signal such that all the first switches S1 are turned on or off in synchronization, and all the second switches S2 are simultaneously turned on or off. It is also worth noting that the conduction periods of the first and second switches S1 and S2 do not overlap each other.
如此，當所有第一開關S1導通而所有第二開關S2不導通時，則第一差動電路A1操作於差動模式，第二差動電路A2操作於偏壓模式。當所有第一開關S1不導通而所有第二開關S2導通時，則第一差動電路A1操作於偏壓模式，第二差動電路A2操作於差動模式。Thus, when all of the first switches S1 are turned on and all of the second switches S2 are not turned on, the first differential circuit A1 operates in the differential mode, and the second differential circuit A2 operates in the bias mode. When all of the first switches S1 are not turned on and all of the second switches S2 are turned on, the first differential circuit A1 operates in the bias mode, and the second differential circuit A2 operates in the differential mode.
此外，增益電路G電連接於該第一、二差動電路A1~2之間，以接收來自該第一或二差動電路A1、A2的差動電流。且增益電路G提供一增益以將來自該第一、二差動電路的阻抗作用進行放大，以增加該組差動輸出電壓Vo+、Vo-的幅值。Further, the gain circuit G is electrically connected between the first and second differential circuits A1 to 2 to receive a differential current from the first or second differential circuits A1 and A2. And the gain circuit G provides a gain to amplify the impedance action from the first and second differential circuits to increase the amplitude of the set of differential output voltages Vo+, Vo-.
該增益電路G包括一第五電晶體PMOS5、一第六電晶體PMOS6、一第七電晶體NMOS7、一第八電晶體NMOS8、四個放大單元G1~G4。The gain circuit G includes a fifth transistor PMOS5, a sixth transistor PMOS6, a seventh transistor NMOS7, an eighth transistor NMOS8, and four amplification units G1~G4.
該四個放大單元G1~G4的輸入端分別電連接於該四電晶體PMOS5、PMOS6、NMOS7、NMOS8的源極，且四個放大單元G1~G4的輸出端分別電連接於該四電晶體PMOS5、PMOS6、NMOS7、NMOS8的閘極。The input ends of the four amplifying units G1 G G4 are electrically connected to the sources of the four transistors PMOS 5 , PMOS 6 , NMOS 7 , and NMOS 8 , respectively , and the output ends of the four amplifying units G1 G G4 are electrically connected to the four transistors PMOS 5 , respectively. , PMOS6, NMOS7, NMOS8 gate.
該四電晶體PMOS5、PMOS6、NMOS7、NMOS8的源極分別電連接於該四電晶體PMOS3、PMOS4、NMOS1、NMOS2的汲極。The sources of the four transistors PMOS5, PMOS6, NMOS7, and NMOS8 are electrically connected to the drains of the four transistors PMOS3, PMOS4, NMOS1, and NMOS2, respectively.
該二電晶體NMOS7、NMOS8的汲極分別電連接於該二電晶體PMOS5、PMOS6的汲極，且輸出該組差動輸出電壓Vo-、Vo+。The drains of the two transistors NMOS7 and NMOS8 are electrically connected to the drains of the two transistors PMOS5 and PMOS6, respectively, and output the set of differential output voltages Vo- and Vo+.
本實施例中的第一、二、七、八電晶體NMOS1、2、7、8是一N型金屬氧化物半導體場效電晶體，而該第三、四、五、六電晶體PMOS3~6是一P型金屬氧化物半導體場效電晶體。The first, second, seventh, and eighth transistors NMOS 1, 2, 7, and 8 in this embodiment are an N-type metal oxide semiconductor field effect transistor, and the third, fourth, fifth, and sixth transistors PMOS 3 to 6 It is a P-type metal oxide semiconductor field effect transistor.
又如圖5所示，為第一較佳實施例的變形，其中差別在於：沒有該增益電路G，而是第一差動電路A1直接電連接於第二差動電路A2，且該第一、二差動電路將分別起阻抗作用而根據所產生的差動電流產生該組差動輸出電壓Vo+、Vo-。又此變形的電路操作與上述類似，故不再重述。As shown in FIG. 5, it is a modification of the first preferred embodiment, wherein the difference is that the gain circuit G1 is not provided, but the first differential circuit A1 is directly electrically connected to the second differential circuit A2, and the first The two differential circuits respectively act as impedances to generate the set of differential output voltages Vo+, Vo- according to the generated differential current. The circuit operation of this modification is similar to the above, and will not be repeated.
而在詳細電路連接方式的差別為：該第一、二電晶體NMOS1、NMOS2的汲極分別電連接於該第三、四電晶體PMOS3、PMOS4的汲極，且輸出該組差動輸出電壓Vo-、Vo+。The difference in the detailed circuit connection manner is that the drains of the first and second transistors NMOS1 and NMOS2 are electrically connected to the drains of the third and fourth transistors PMOS3 and PMOS4, respectively, and the differential output voltage Vo is outputted. -, Vo+.
上述架構因移除尾端電流源，相較於先前技術可得到更廣的輸出振幅。The above architecture results in a wider output amplitude than the prior art due to the removal of the tail current source.
<第二較佳實施例><Second preferred embodiment>
如圖6所示，本發明運算放大器之第二較佳實施例，適用於接收一第一組差動輸入電壓Vin1+、Vin1-和一第二組差動輸入電壓Vin2+、Vin2-，並進行放大以輸出一組差動輸出電壓Vo+、Vo-。As shown in FIG. 6, the second preferred embodiment of the operational amplifier of the present invention is adapted to receive a first set of differential input voltages Vin1+, Vin1- and a second set of differential input voltages Vin2+, Vin2-, and to amplify To output a set of differential output voltages Vo+, Vo-.
且該運算放大器包含：一直流偏壓電路D、一第一差動電路B1、一第二差動電路B2、一切換裝置T、一增益電路G、一共模回授電路CF、一共模偏壓電路C。其中，增益電路G會透過該切換裝置T分別耦接到第一差動電路B1、一第二差動電路B2。The operational amplifier includes: a DC bias circuit D, a first differential circuit B1, a second differential circuit B2, a switching device T, a gain circuit G, a common mode feedback circuit CF, and a common mode offset. Voltage circuit C. The gain circuit G is respectively coupled to the first differential circuit B1 and the second differential circuit B2 through the switching device T.
直流偏壓電路D用於產生一呈直流的第一偏壓電流IB1，且包括一第十一電晶體PMOS11，該電晶體PMOS11具有一電連接於一直流電壓VDD的源極、一電連接於一偏壓電壓Vbp的閘極、和一輸出該第一偏壓電流IB1的汲極。The DC bias circuit D is configured to generate a DC bias current IB1, and includes an eleventh transistor PMOS11 having a source electrically connected to the DC voltage VDD and an electrical connection a gate of a bias voltage Vbp and a drain for outputting the first bias current IB1.
第一差動電路B1透過該切換裝置T耦接該直流偏壓電路D，並用於將所接收的電壓轉換成電流，且包括：一第一電晶體PMOS1及一第二電晶體PMOS2。該二電晶體PMOS1、2分別具有一閘極、一源極和一汲極。The first differential circuit B1 is coupled to the DC bias circuit D through the switching device T, and is configured to convert the received voltage into a current, and includes: a first transistor PMOS1 and a second transistor PMOS2. The two transistors PMOS1, 2 have a gate, a source and a drain, respectively.
該第二差動電路透過該切換裝置T耦接該直流偏壓電路，並用於將所接收的電壓轉換成電流，且包括：一第九電晶體PMOS9及一第十電晶體PMOS10。該二電晶體PMOS9、10分別具有一閘極、一源極和一汲極。The second differential circuit is coupled to the DC bias circuit through the switching device T and configured to convert the received voltage into a current, and includes: a ninth transistor PMOS 9 and a tenth transistor PMOS 10. The two transistors PMOS 9, 10 have a gate, a source and a drain, respectively.
該切換裝置T則用以切換地傳遞該第一組差動電壓或一偏壓電壓Vbp到二電晶體PMOS1、2的閘極，並用以切換地傳遞該第二組差動電壓或該偏壓電壓到PMOS9、10的閘極。較佳地，本例的第一、二組差動電壓相同。The switching device T is configured to switchably transmit the first set of differential voltages or a bias voltage Vbp to the gates of the two transistors PMOS1, 2, and to switch the second set of differential voltages or the biases Voltage to the gate of PMOS 9, 10 . Preferably, the first and second sets of differential voltages of this example are the same.
值得注意的是，當該切換裝置T傳遞第一組差動電壓到二電晶體PMOS1、2的閘極時，會傳遞偏壓電壓Vbp到二電晶體PMOS9、10的閘極。而當該切換裝置傳遞偏壓電壓Vbp到二電晶體PMOS1、2的閘極時，會傳遞第二組差動電壓到PMOS9、10的閘極。It should be noted that when the switching device T transmits the first set of differential voltages to the gates of the two transistors PMOS1, 2, the bias voltage Vbp is transferred to the gates of the two transistors PMOS9, 10. When the switching device transmits the bias voltage Vbp to the gates of the two transistors PMOS1, 2, a second set of differential voltages is delivered to the gates of the PMOSs 9, 10.
而各差動電路B1、B2會因為收到的信號不同，而操作於一差動模式或一偏壓模式。詳細作動情形說明如下。The differential circuits B1, B2 operate in a differential mode or a bias mode because the received signals are different. The detailed action situation is explained below.
參閱圖7，當二電晶體PMOS1、2的閘極分別收到第一組差動電壓Vin1+、Vin1-，第一差動電路B1會操作於差動模式而藉由該二電晶體PMOS1、2的汲極輸出一呈交流的第一差動電流id1。此時，由於二電晶體PMOS9、10的閘極分別收到偏壓電壓Vbp，所以第二差動電路B2會操作於偏壓模式而藉由二電晶體PMOS9、10的汲極輸出二第二偏壓電流IB2。該第一、二差動電路B1、B2和該共模偏壓電路C該更將起阻抗作用而根據該第一差動電流id1產生該組差動輸出電壓Vo+、Vo-。Referring to FIG. 7, when the gates of the two transistors PMOS1, 2 receive the first set of differential voltages Vin1+, Vin1-, respectively, the first differential circuit B1 operates in the differential mode by the two transistors PMOS1, 2 The drain output of the drain is the first differential current id1 of the alternating current. At this time, since the gates of the two transistors PMOS9, 10 respectively receive the bias voltage Vbp, the second differential circuit B2 operates in the bias mode and the second output of the two transistors PMOS9, 10 is second. Bias current IB2. The first and second differential circuits B1 and B2 and the common mode bias circuit C further function as impedances to generate the set of differential output voltages Vo+ and Vo− according to the first differential current id1.
參閱圖8，反之，當二電晶體PMOS1、2的閘極分別收到偏壓電壓Vbp，第一差動電路B1會操作於偏壓模式而藉由二電晶體PMOS1、2的汲極輸出二第三偏壓電流IB3。此時，由於二電晶體PMOS9、10的閘極分別接收該第二組差動電壓Vin2+、Vin2-，所以第二差動電路B2會操作於差動模式而藉由PMOS9、10的汲極輸出該第二差動電流id2。該第一、二差動電路B1、B2和該共模偏壓電路C該更將起阻抗作用而根據該第二差動電流id2產生該組差動輸出電壓Vo+、Vo-。Referring to FIG. 8, on the other hand, when the gates of the two transistors PMOS1 and 2 respectively receive the bias voltage Vbp, the first differential circuit B1 operates in the bias mode and the drain output of the two transistors PMOS1, 2 is two. The third bias current IB3. At this time, since the gates of the two transistors PMOS9, 10 respectively receive the second set of differential voltages Vin2+, Vin2-, the second differential circuit B2 operates in the differential mode and outputs the drains of the PMOSs 9, 10 The second differential current id2. The first and second differential circuits B1, B2 and the common mode bias circuit C will further act as an impedance to generate the set of differential output voltages Vo+, Vo- based on the second differential current id2.
該增益電路G電連接於該共模偏壓電路C和該切換裝置T，且提供一增益以將來自該第一、二差動電路B1、B2和該共模偏壓電路C的阻抗作用進行放大，以增加該組差動輸出電壓Vo+、Vo-的幅值。The gain circuit G is electrically connected to the common mode bias circuit C and the switching device T, and provides a gain to impedance the first and second differential circuits B1, B2 and the common mode bias circuit C. The function is amplified to increase the amplitude of the set of differential output voltages Vo+, Vo-.
回歸參閱圖6，共模回授(common-mode feedback,CMFB)電路CF，偵測該組差動輸出電壓Vo+、Vo-，而送出一期望將該組差動輸出電壓的共模值調整至一預設值的共模控制電壓VCMFB ，又此電路的詳細做法可參考「D. Senderowicz,S. Dreyer,J. II. Huggins,C. F. Rahim,and C. A. Laber,”A family of differential NMOS analog circuits for a PCM codes filter chip,”IEEE J. Solid-State Circuits ,vol. SC-17,Dec.1982,pp. 1014-1023」、「R. Castello and P. R. Gray,“A high-performance micropower switched-capacitor filter,”IEEE J. Solid-State Circuits ,vol. SC-20,no. 6,Dec. 1985,pp.1122-1132」，但不限於此文獻所述。Referring back to FIG. 6, a common-mode feedback (CMFB) circuit CF detects the set of differential output voltages Vo+, Vo-, and sends a desired common mode value of the set of differential output voltages to A preset value common mode control voltage V CMFB , and a detailed description of this circuit can be found in "D. Senderowicz, S. Dreyer, J. II. Huggins, CF Rahim, and CA Laber," A family of differential NMOS analog circuits. For a PCM codes filter chip," IEEE J. Solid-State Circuits , vol. SC-17, Dec. 1982, pp. 1014-1023", "R. Castello and PR Gray, "A high-performance micropower switched-capacitor Filter, " IEEE J. Solid-State Circuits , vol. SC-20, no. 6, Dec. 1985, pp. 1122-1132", but is not limited to this document.
共模偏壓電路C，用以接收該共模控制電壓VCMFB ，以將該組差動輸出電壓Vo+、Vo-的平均值維持於一預設值。The common mode bias circuit C is configured to receive the common mode control voltage V CMFB to maintain an average value of the set of differential output voltages Vo+ and Vo− at a predetermined value.
再者，詳細來說，本例之增益電路G的實施態樣是：包括一第五、六電晶體NMOS5、6、一第七、八電晶體PMOS7、8和四個放大單元G1~G4。其中，該四個放大單元G1~G4的輸入端分別電連接於該等電晶體NMOS5、6、PMOS7、8的源極，且四個放大單元G1~G4的輸出端分別電連接於該等電晶體NMOS5、6、PMOS7、8的閘極。二電晶體PMOS7、8的汲極分別電連接於該二電晶體NMOS5、6的汲極，且輸出該組差動輸出電壓Vo-、Vo+。Furthermore, in detail, the implementation of the gain circuit G of this example includes a fifth and sixth transistor NMOS 5, 6, a seventh, eight transistor PMOS 7, 8 and four amplification units G1 to G4. The input ends of the four amplification units G1 G G4 are respectively electrically connected to the sources of the transistors NMOS 5 , 6 , PMOS 7 , 8 , and the output ends of the four amplification units G1 G G4 are electrically connected to the same The gates of the crystal NMOS 5, 6, PMOS 7, 8. The drains of the two transistors PMOS7, 8 are electrically connected to the drains of the two transistors NMOS5, 6, respectively, and output the set of differential output voltages Vo-, Vo+.
而本例之切換裝置T的實施態樣是：包括電連接第一差動電路B1的六個第一開關S1和六個第二開關S2，且包括電連接第二差動電路B2的六個第一開關S1和六個第二開關S2。每一開關皆具有一第一端、一第二端和一控制端，且各控制端受控制使相關的第一端和第二端於導通與不導通之間切換。The implementation of the switching device T of the present example is: six first switches S1 and six second switches S2 electrically connected to the first differential circuit B1, and six electrically connected to the second differential circuit B2. The first switch S1 and the six second switches S2. Each switch has a first end, a second end and a control end, and each control end is controlled such that the associated first end and the second end switch between conducting and non-conducting.
電連接第一差動電路B1的該六第一開關S1的其中之二，會藉由各自的第一端分別接收該第一組差動電壓Vin1+、Vin1-，且藉由各自的第二端分別電連接該二電晶體PMOS1、2的閘極。Two of the six first switches S1 electrically connected to the first differential circuit B1 receive the first set of differential voltages Vin1+, Vin1-, respectively, by respective first ends, and by respective second ends The gates of the two transistors PMOS1, 2 are electrically connected, respectively.
電連接第一差動電路B1的該六第一開關S1的其中之另二，會藉由各自的第一端分別電連接於該二電晶體PMOS1、2的源極，且藉由各自的第二端分別電連接於該電晶體PMOS11的汲極。The other two of the six first switches S1 electrically connected to the first differential circuit B1 are electrically connected to the sources of the two transistors PMOS1 and 2 by respective first ends, and by respective The two ends are electrically connected to the drains of the transistor PMOS11, respectively.
電連接第一差動電路B1的該六第一開關S1的剩餘之二，會藉由各自的第一端分別電連接於該二電晶體NMOS5、6的源極，且藉由各自的第二端分別電連接該二電晶體PMOS1、2的汲極。The remaining two of the six first switches S1 electrically connected to the first differential circuit B1 are electrically connected to the sources of the two transistors NMOS 5, 6 by respective first ends, and by respective second The terminals are electrically connected to the drains of the two transistors PMOS1, 2, respectively.
電連接第一差動電路B1的該六個第二開關S2的其中之二，會藉由各自的第一端分別接收偏壓電壓Vbp，且藉由各自的第二端分別電連接該二電晶體PMOS1、2的閘極。Two of the six second switches S2 electrically connected to the first differential circuit B1 receive the bias voltage Vbp by the respective first ends, and are electrically connected to the second terminals by the respective second ends. The gates of the crystals PMOS1, 2.
電連接第一差動電路B1的該六個第二開關S2的其中之另二，會藉由各自的第一端分別電連接於該二電晶體PMOS1、2的源極，且藉由各自的第二端分別電連接於該直流電壓VDD。The other two of the six second switches S2 electrically connected to the first differential circuit B1 are electrically connected to the sources of the two transistors PMOS1, 2 by respective first ends, and by respective The second ends are electrically connected to the DC voltage VDD, respectively.
電連接第一差動電路B1的該六個第二開關S2的剩餘之二，會藉由各自的第一端分別電連接於該二電晶體PMOS7、8的源極，且藉由各自的第二端分別電連接於該二電晶體PMOS1、2的汲極。The remaining two of the six second switches S2 electrically connected to the first differential circuit B1 are electrically connected to the sources of the two transistors PMOS7, 8 by respective first ends, and by respective The two ends are electrically connected to the drains of the two transistors PMOS1, 2, respectively.
另一方面，電連接第二差動電路B2的該六個第一開關S1的其中之二，會藉由各自的第一端分別接收該偏壓電壓Vbp，且藉由各自的第二端分別電連接該二電晶體PMOS9、10的閘極。On the other hand, two of the six first switches S1 electrically connected to the second differential circuit B2 receive the bias voltage Vbp by the respective first ends, and are respectively separated by the respective second ends. The gates of the two transistors PMOS 9, 10 are electrically connected.
電連接第二差動電路B2的該六個第一開關S1的其中之另二，會藉由各自的第一端分別電連接於該二電晶體PMOS9、10的源極，且藉由各自的第二端分別電連接於該直流電壓VDD。The other two of the six first switches S1 electrically connected to the second differential circuit B2 are electrically connected to the sources of the two transistors PMOS 9, 10 by respective first ends, and by respective The second ends are electrically connected to the DC voltage VDD, respectively.
電連接第二差動電路B2的該六個第一開關S1的剩餘之二，會藉由各自的第一端分別電連接於該二電晶體PMOS7、8的源極，且藉由各自的第二端分別電連接該二電晶體PMOS9、10的汲極。The remaining two of the six first switches S1 electrically connected to the second differential circuit B2 are electrically connected to the sources of the two transistors PMOS7, 8 by respective first ends, and by respective The two ends are electrically connected to the drains of the two transistors PMOS 9, 10, respectively.
電連接第二差動電路B2的該六個第二開關S2的其中之二，會藉由各自的第一端分別接收該第二差動電壓Vin2+、Vin2-，且藉由各自的第二端分別電連接該二電晶體PMOS9、10的閘極。Two of the six second switches S2 electrically connected to the second differential circuit B2 receive the second differential voltages Vin2+, Vin2- by respective first ends, and by respective second ends The gates of the two transistors PMOS 9, 10 are electrically connected, respectively.
電連接第二差動電路B2的該六個第二開關S2的其中之另二，會藉由各自的第一端分別電連接於該二電晶體PMOS9、10的源極，且藉由各自的第二端分別電連接於該電晶體PMOS11的汲極。The other two of the six second switches S2 electrically connected to the second differential circuit B2 are electrically connected to the sources of the two transistors PMOS 9, 10 by respective first ends, and by respective The second ends are electrically connected to the drains of the transistor PMOS11, respectively.
電連接第二差動電路B2的該六個第二開關S2的剩餘之二，會藉由各自的第一端分別電連接於該二電晶體NMOS5、6的源極，且藉由各自的第二端分別電連接該二電晶體PMOS9、10的汲極。The remaining two of the six second switches S2 electrically connected to the second differential circuit B2 are electrically connected to the sources of the two transistors NMOS 5, 6 by respective first ends, and by respective The two ends are electrically connected to the drains of the two transistors PMOS 9, 10, respectively.
該切換裝置T根據一控制信號來控制，使得所有第一開關S1同步導通或不導通，也使得所有第二開關S2同步導通或不導通。且值得注意的是，第一、二開關S1、S2的導通期間不會互相重疊(overlap)。The switching device T is controlled according to a control signal such that all the first switches S1 are turned on or off in synchronization, and all the second switches S2 are simultaneously turned on or off. It is also worth noting that the conduction periods of the first and second switches S1 and S2 do not overlap each other.
如此，當所有第一開關S1導通而所有第二開關S2不導通時，則第一差動電路B1操作於差動模式，第二差動電路B2操作於偏壓模式。當所有第一開關S1不導通而所有第二開關S2導通時，則第一差動電路B1操作於偏壓模式，第二差動電路B2操作於差動模式。Thus, when all of the first switches S1 are turned on and all of the second switches S2 are not turned on, the first differential circuit B1 operates in the differential mode, and the second differential circuit B2 operates in the bias mode. When all of the first switches S1 are not turned on and all of the second switches S2 are turned on, the first differential circuit B1 operates in the bias mode, and the second differential circuit B2 operates in the differential mode.
此外，該共模偏壓電路C的實施態樣是：該共模偏壓電路C電連接於該增益電路G和該共模回授電路CF，且透過切換裝置T耦接到該第一、二差動電路B1、B2。In addition, the common mode bias circuit C is electrically connected to the gain circuit G and the common mode feedback circuit CF, and coupled to the first through the switching device T. One or two differential circuits B1, B2.
該共模偏壓電路C包括一NMOS3、4。該二電晶體NMOS3、4的閘極接收來自該共模回授電路CF的該共模控制電壓VCMFB ，該二電晶體NMOS3、4的源極電連接於地，該NMOS3、4的汲極分別電連接於該二電晶體NMOS5、6的源極。The common mode bias circuit C includes an NMOS 3, 4. The gates of the two transistors NMOS3, 4 receive the common mode control voltage V CMFB from the common mode feedback circuit CF, the sources of the two transistors NMOS3, 4 are electrically connected to the ground, and the drains of the NMOS 3, 4 They are electrically connected to the sources of the two transistor NMOSs 5, 6, respectively.
因本實施例使用由該第一、二差動電路B1、B2、切換裝置T和該增益電路G所構成的折疊式串疊型(folded-cascode)架構，相較於先前技術，可得到較大的輸出振幅。Since the present embodiment uses a folded-cascode architecture composed of the first and second differential circuits B1 and B2, the switching device T, and the gain circuit G, compared with the prior art, Large output amplitude.
本實施例中的第三~第六電晶體NMOS3~6是一N型金屬氧化物半導體場效電晶體(NMOS)，而第一、第二、第七~十一電晶體PMOS1、2、7~11是一P型金屬氧化物半導體場效電晶體(PMOS)。The third to sixth transistors NMOS 3 to 6 in this embodiment are an N-type metal oxide semiconductor field effect transistor (NMOS), and the first, second, seventh to eleven transistors PMOS 1, 2, and 7 ~11 is a P-type metal oxide semiconductor field effect transistor (PMOS).
又如圖9所示，為第二較佳實施例的變形，其中差別在於：沒有該增益電路G，又此變形的電路操作與該第二較佳實施例類似，故不再重述。As shown in FIG. 9, it is a modification of the second preferred embodiment, wherein the difference is that the circuit operation without the gain circuit G is similar to that of the second preferred embodiment and will not be repeated.
<第三較佳實施例><Third preferred embodiment>
如圖10所示，與第二較佳實施例的差別為將NMOS改成PMOS，而將PMOS改成NMOS，其中，該第三、四電晶體PMOS3、4的源極改成電連接於一直流電壓VDD，而該第十一電晶體NMOS11的源極改成電連接於地，電連接於第一差動電路B1的部分第二開關S2之第二端改電連接於地，電連接於第二差動電路B2的部分第一開關S1之第二端改電連接於地，其餘部分因其連接關係與操作類似，故不再重述。As shown in FIG. 10, the difference from the second preferred embodiment is that the NMOS is changed to a PMOS, and the PMOS is changed to an NMOS, wherein the sources of the third and fourth transistors PMOS3, 4 are electrically connected to one. The DC voltage VDD is changed, and the source of the eleventh transistor NMOS11 is electrically connected to the ground, and the second end of the second switch S2 electrically connected to the first differential circuit B1 is electrically connected to the ground and electrically connected to the ground. The second end of the part of the first switch S1 of the second differential circuit B2 is electrically connected to the ground, and the rest is similar to the operation because of its connection relationship, and therefore will not be described again.
又如圖11所示，為第三較佳實施例的變形，其中差別在於：沒有該增益電路G，又此變形的電路操作與該第三較佳實施例類似，故不再重述。Further, as shown in FIG. 11, it is a modification of the third preferred embodiment, wherein the difference is that the circuit operation without the gain circuit G is similar to that of the third preferred embodiment and will not be described again.
又上述所有實施例，不限於用金屬氧化物半導體場效電晶體(MOS)實現，也可改成雙載子接面電晶體(BJT)實現。Furthermore, all of the above embodiments are not limited to implementation by a metal oxide semiconductor field effect transistor (MOS), but may also be implemented as a bi-carrier junction transistor (BJT).
綜上所述，將本發明之較佳實施例應用於類比/數位轉換裝置之共享運算放大器的架構中具有以下優點：In summary, the application of the preferred embodiment of the present invention to the architecture of a shared operational amplifier of an analog/digital conversion device has the following advantages:
1.藉由該第一、二差動電路A1、A2或B1、B2切換於差動模式和偏壓模式中，可消除殘值記憶效應。1. By switching the first and second differential circuits A1, A2 or B1, B2 in the differential mode and the bias mode, the residual memory effect can be eliminated.
2.相較於先前技術，本發明的差動輸出電壓之振幅較大，因此，可容忍較大的雜訊，又因為雜訊正比於(k：波茲曼常數，T：絕對溫度，C：電容值)，所以本發明所推動的電容大小就可以降低，如果不需要推動太大的電容，就可以把MOS大小縮小，使總面積下降，進而減少成本。2. Compared with the prior art, the amplitude of the differential output voltage of the present invention is large, so that a large amount of noise can be tolerated, and because the noise is proportional to (k: Boltzmann constant, T: absolute temperature, C: capacitance value), so the size of the capacitor pushed by the present invention can be reduced. If it is not necessary to push too large a capacitor, the MOS size can be reduced to make the total area Decline, which in turn reduces costs.
3.更因為可容忍較大的雜訊，於供應較小的直流電壓即可達到與先前技術相同的信號雜訊比(SNR)，因此，可減少功率消耗。3. Because it can tolerate large noise, it can achieve the same signal-to-noise ratio (SNR) as the prior art by supplying a small DC voltage, thus reducing power consumption.
惟以上所述者，僅為本發明之較佳實施例而已，當不能以此限定本發明實施之範圍，即大凡依本發明申請專利範圍及發明說明內容所作之簡單的等效變化與修飾，皆仍屬本發明專利涵蓋之範圍內。The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.
A1~2．．．第一、二差動電路A1~2. . . First and second differential circuits
T．．．切換電路T. . . Switching circuit
S1~2．．．第一、二開關S1~2. . . First and second switches
G．．．增益電路G. . . Gain circuit
G1~4．．．放大單元G1~4. . . Amplification unit
NMOS1~2．．．第一、二電晶體NMOS1~2. . . First and second transistors
NMOS7~8．．．第七、八電晶體NMOS7~8. . . Seventh, eight transistors
PMOS3~6．．．第三~六電晶體PMOS3~6. . . Third to sixth transistor
D．．．直流偏壓電路D. . . DC bias circuit
C．．．共模偏壓電路C. . . Common mode bias circuit
CF．．．共模回授電路CF. . . Common mode feedback circuit
B1~2．．．第一、二差動電路B1~2. . . First and second differential circuits
PMOS1~2．．．第一、二電晶體PMOS1~2. . . First and second transistors
PMOS7~11．．．第七~十一電晶體PMOS7~11. . . Seventh to eleventh crystal
NMOS3~6．．．第三~六電晶體NMOS3~6. . . Third to sixth transistor
圖1是習知運算放大器的電路圖；1 is a circuit diagram of a conventional operational amplifier;
圖2是本發明第一較佳實施例的電路圖；Figure 2 is a circuit diagram of a first preferred embodiment of the present invention;
圖3是該第一較佳實施例輸出第一差動電流的電路圖；3 is a circuit diagram of outputting a first differential current in the first preferred embodiment;
圖4是該第一較佳實施例輸出第二差動電流的電路圖；4 is a circuit diagram of outputting a second differential current in the first preferred embodiment;
圖5是該第一較佳實施例變形的電路圖；Figure 5 is a circuit diagram showing a modification of the first preferred embodiment;
圖6是本發明第二較佳實施例的電路圖；Figure 6 is a circuit diagram of a second preferred embodiment of the present invention;
圖7是該第二較佳實施例輸出第一差動電流的電路圖；Figure 7 is a circuit diagram showing the output of the first differential current in the second preferred embodiment;
圖8是該第二較佳實施例輸出第二差動電流的電路圖；Figure 8 is a circuit diagram showing the output of the second differential current in the second preferred embodiment;
圖9是該第二較佳實施例變形的電路圖；Figure 9 is a circuit diagram showing a modification of the second preferred embodiment;
圖10是本發明第三較佳實施例的電路圖；及Figure 10 is a circuit diagram of a third preferred embodiment of the present invention; and
圖11是該第三較佳實施例變形的電路圖。Figure 11 is a circuit diagram showing a modification of the third preferred embodiment.
A1~2．．．第一、二差動電路A1~2. . . First and second differential circuits
T．．．切換電路T. . . Switching circuit
S1~2．．．第一、二開關S1~2. . . First and second switches
G．．．增益電路G. . . Gain circuit
G1~4．．．放大單元G1~4. . . Amplification unit
NMOS1~2．．．第一、二電晶體NMOS1~2. . . First and second transistors
NMOS7~8．．．第七、八電晶體NMOS7~8. . . Seventh, eight transistors
PMOS3~6．．．第三~六電晶體PMOS3~6. . . Third to sixth transistor
Claims (20)
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| TW99118716A TWI397258B (en) | 2010-06-09 | 2010-06-09 | Operational amplifier |
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| Application Number | Priority Date | Filing Date | Title |
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| TW99118716A TWI397258B (en) | 2010-06-09 | 2010-06-09 | Operational amplifier |
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| TWI397258B true TWI397258B (en) | 2013-05-21 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6759898B1 (en) * | 2003-01-24 | 2004-07-06 | Ion E. Opris | Dual input differential amplifier |
| EP1354399B1 (en) * | 2000-12-15 | 2006-04-19 | Broadcom Corporation | Differential amplifier with large input common mode signal range |
| TW200828788A (en) * | 2006-12-21 | 2008-07-01 | Novatek Microelectronics Corp | Differential amplifier with plurality of input pairs |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1354399B1 (en) * | 2000-12-15 | 2006-04-19 | Broadcom Corporation | Differential amplifier with large input common mode signal range |
| US6759898B1 (en) * | 2003-01-24 | 2004-07-06 | Ion E. Opris | Dual input differential amplifier |
| TW200828788A (en) * | 2006-12-21 | 2008-07-01 | Novatek Microelectronics Corp | Differential amplifier with plurality of input pairs |
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