TW201145813A - Operational amplifier - Google Patents

Abstract

An operational amplifier includes: a first differential circuit coupled to a ground; a second differential circuit coupled between a DC voltage and the first differential circuit; and a switching device coupled to the first and second differential circuit, and selectively configuring each of the first and second differential circuits to operate in a differential mode. When the first differential circuit operates in the differential mode, it outputs a first differential current based on a first set of differential voltages, and cooperates with the second differential circuit to generate a set of differential output voltages based on the first differential current. When the second differential circuit operates in the differential mode, it outputs a second differential current based on a second set of differential voltages, and cooperates with the first differential circuit to generate a set of differential output voltages based on the second differential current.

Description

201145813 VI. Description of the Invention: [Technical Field] The present invention relates to an amplifier, and more particularly to an operational amplifier. [Prior Art] A conventional pipeline analog/digital conversion apparatus converts an input voltage into a corresponding digital signal by a shared arithmetic amplifier structure to save power and area cost. However, the above analog/digital conversion device has the disadvantage that the gate capacitance of the input differential pair of the shared operational amplifier is such that the previous charge injection leaves the residual memory effect and reduces the overall efficiency. As shown in Figure 1, U.S. Patent No. 6,759 898 B1, dual input

the goal of. Point I is: using the tail current source 200, which reduces the size of the noise that can be tolerated by the circuit. However, the above operational amplifier has the disadvantage of limiting the amplitude of the differential output signal. [Invention] It is to provide a way to avoid limiting the differential input. For the purpose of the present invention, 201145813 increases the amplitude of the signal, increases the operational amplifier that can tolerate noise and reduce power consumption. The operational amplifier includes: a first differential circuit electrically connected to the ground; a second differential circuit electrically connected between the DC voltage and the first differential circuit; and a switching device electrically connected to the first One or two differential circuits, and the switching device selectively operates the differential circuits in a differential mode; wherein, when the first differential circuit operates in a differential mode, the differential is based on a first group The voltage outputs a first differential current, and the first and second differential circuits further act as an impedance to generate a set of differential wheeling voltages according to the first differential current; when the second differential circuit operates at the difference In the active mode, a second differential current is output according to a second set of differential voltages, and the first and second differential circuits further function as impedances to generate the set of differential output voltages according to the second differential currents. Another object of the invention is to provide another operational amplifier. The operational amplifier includes: - a DC bias circuit for generating - a first bias current of a DC current, a first differential circuit coupled to the DC bias circuit; and a second differential circuit coupled to the a DC bias circuit; a switching device electrically connecting the first and second differential circuits, and the switching selectively operating the differential circuits in a differential mode; and 5 201145813 a common mode bias circuit, Connecting the switching device; wherein, when the first differential circuit operates in a differential mode, the DC bias circuit is coupled to receive the first bias current, and according to a first set of differential voltage outputs - a first-differential current, and the first and second differential circuits and the common-mode bias circuit further act as an impedance to generate a set of differential output voltages according to the first differential current; The dynamic circuit operates in the differential mode, coupled to the DC bias circuit to receive the first bias current, and according to a second set of differential electric grind output - the second differential current 'and the first, The second differential circuit and the common mode bias circuit will further act as an impedance The second differential current generates the set of differential output voltages; and ^ the common mode bias circuit maintains the average of the set of differential output voltages at a predetermined value based on a common mode control voltage. The above and other technical contents, features and effects of the present invention will be apparent from the following detailed description of the preferred embodiments of the drawings. <First Preferred Embodiment> As shown in FIG. 2, a first preferred embodiment of the operational amplifier of the present invention is adapted to receive a first set of differential voltages and a second set of differential voltages and to amplify Take the wheel-set differential output voltages v〇+, v〇·. And the operation amplification includes: a first-differential circuit A1, a second differential circuit A2, a switching device T, and a gain circuit. The first differential circuit A1 is configured to convert the received voltage into a current. 201145813 includes a first transistor NMOS1 and a second transistor NM〇S2, wherein the first and second transistors NM〇S 1 and 2 respectively have a gate, a drain, and a source electrically connected to the ground. . The second differential circuit A2 is configured to convert the received voltage into a current, and includes a third transistor PM0S3 and a fourth transistor PM〇S4, wherein the third and fourth transistors PM0S3 and 4 respectively have a gate A pole, a drain and a source are electrically connected to the source of the DC voltage VDD.

The switching device T is configured to switchably transmit the first set of differential voltages or a first bias voltage Vbn to the gates of the first and second transistors NM〇s1, 2, and to switch the second group The differential voltage or a second bias voltage Vbp is applied to the gates of the PMOSs 3, 4. Preferably, the first and second sets of differential voltages of the present example are different, and therefore are represented by (Vini+, (Vin2+, Vin2-) respectively in the figure. 〃 It is worth noting that 'when the switching device transmits the first When the differential voltage reaches the first and second transistors NMOS1, 2# gate, the second bias voltage Vbp is transmitted to the interpoles of the third and fourth transistors pM〇S3, 4. When the switching device τ transmits When the first bias voltage Vbn reaches the gates of the first and second transistors (4) and 2, the second set of differential voltages are transmitted to the gates of the third and fourth transistors PM0S3, 4. The differential circuits will Because the signals received are different to Sun

, ▼...r rj I motion mode or -bias mode. The detailed operation situation is as follows: In Fig. 3, when the first and second transistors are difficult (10), the gates of 2 are made in the "group differential voltage Vhll+, ¥ 'the first differential circuit A1 is hit; in the dynamic mode The first and second transistors Lancome 51, 2 (4) 201145813 output a first differential power dl. At this time, since the third and fourth transistors _S3, 4 respectively receive the second bias The second differential circuit A2 operates in the bias mode and outputs two bias currents through the non-polarization of the third and fourth transistors PMOS3, 4. The first and second differential circuits Μ, A2 are further The set of differential output voltages Vo+, vQ_ will be generated according to the first differential current (8). Referring to FIG. 4, on the contrary, the gates of the first transistors NMOS1 and 2 respectively receive the first- The bias voltage Vbn, the first-differential circuit... operates in the partial mode, and the two-bias current is generated by the first and second transistors Nm〇si, 2, and the second bias current is 1dC2°. The gates of the crystals PM〇S3 and 4 respectively receive the second set of differential powers M Vin2+ and vin2_, so the second differential power 4 A2 operates in the differential mode and borrows The drains of the third and fourth transistor brains S3, 4 output the second differential current milk. The first and second differential circuits M and A2 will further act as impedances to generate the group according to the second differential current (10). Differential output voltage V〇+, ν〇-. Regression parameter _ 2, in detail, the oil changing device τ includes two first switches S1 and two second switches 电 electrically connected to the first differential circuit A1, and The switch includes two first switch si and two second switches S2 electrically connected to the second differential circuit A2. Each switch has a first end, a second end and a control end, and each control end is controlled to be The related __ terminal and the second end are switched between conducting and non-conducting. The two first opening si of the first differential circuit A1 are electrically connected, and the first group is respectively received by the respective first end. The driving voltages Vin1+, vini_ are electrically connected to the 201145813 interpoles of the two transistors (10) and 2 respectively through the respective second ends. The two second switches S2 electrically connected to the first differential circuit A1 are The first terminals respectively receive the first bias voltage vbn, and are respectively electrically connected to the gates of the two transistors NMOS1 and 2 through the respective second ends. On the other hand, the two first switches S1' electrically connected to the second differential circuit A2 respectively receive the second bias voltage Vbp by the respective first ends, and are electrically connected by the respective second ends respectively. The second transistor p]V[〇S3, 4 of the idle pole. • The second switch of the second differential circuit A2 is electrically connected, and the second set of differential voltages Vin2+ are respectively received by the respective first ends, Vin2_, and electrically connected to the gates of the two transistors PM〇S3, 4 by respective second ends, the switching device T is controlled according to a control signal, so that all the first switches s 1 are synchronously turned on or off, All of the second switches S2 are turned on or off. It is also worth noting that the on periods of the first and second switches S1, S2 do not overlap each other.

Thus, when all of the first switches S i are turned on and all of the second switches S2 are not turned on, the first differential circuit A1 operates in the differential mode, and the second differential circuit A2 operates in the bias mode. When all of the first switches S1 are not turned on and all of the second switches S2 are turned on, the first differential circuit Ai operates in the bias mode, and the second differential circuit A2 operates in the differential mode. Further, a gain circuit G is electrically connected between the first and second differential circuits ai to 2' to receive a differential current from the first or second differential circuits A1, A2. And the gain circuit G provides a gain to amplify the impedance from the first and second differential electric circuits "201145813 to increase the amplitude of the set of differential output voltages Vo+, Vo-. The gain circuit G includes a a fifth transistor PMOS5, a sixth transistor PMOS6, a seventh transistor NMOS7, an eighth transistor NMOS8, and four amplification units G1~G4. The input terminals of the four amplification units G1 G G4 are electrically connected to The sources of the four transistors PM0S5, PMOS6, NM0S7, and NMOS8, and the output terminals of the four amplification units G1 to G4 are electrically connected to the gates of the four transistors PMOS5, PMOS6, NMOS7, and NMOS8, respectively. The sources of the PMOS5, PMOS6, NMOS7, and NMOS8 are electrically connected to the drains of the four transistors PMOS3, PMOS4, NMOS1, and NMOS2. The drains of the two transistors NMOS7 and NMOS8 are electrically connected to the two transistors PMOS5 and PMOS6, respectively. The drain of the group and the output of the differential output electric house Vo-, Vo+. The first, second, seventh, and eighth transistors NMOS 1, 2, 7, and 8 in this embodiment are an N-type metal oxide semiconductor field effect. a transistor, and the third, fourth spring, five, six transistor P MOS3~6 is a P-type metal oxide semiconductor field effect transistor. As shown in Fig. 5, it is a modification of the first preferred embodiment, wherein the difference is: without the gain circuit G, but the first differential circuit A1 is directly electrically connected to the second differential circuit A2, and the first and second differential circuits will respectively perform an impedance action to generate the set of differential output voltages Vo+ according to the generated differential current, 10 201145813 v〇- The circuit operation of this deformation is similar to the above, so it will not be repeated. The difference in the detailed circuit connection manner is as follows: The first and second transistors NMOS1, NMOS2 are electrically connected to the third 'four electric The drains of the crystals PM0S3, PM〇S4, and the differential output voltages ν〇_, ν〇+ are output. The above structure can obtain a wider output amplitude than the prior art by removing the tail current source. Second preferred embodiment >

As shown in FIG. 6, a second preferred embodiment of the operational amplifier of the present invention is adapted to receive a first set of differential input voltages Vinl+, Vin and a second set of differential inputs (4) Vin2+, Vin2_, and to amplify A set of differential output voltages Vo+, Vo- is output. The operational amplifier includes: a DC bias circuit D, a first differential circuit B1', a H circuit B2, a switching device τ, a gain circuit G, a common mode feedback circuit CF, and a common mode bias voltage. Road c. The gain circuit G is connected to the first dynamic circuit βΐ and the second differential circuit B2 via the switching device. The DC bias circuit D is for generating a DC-first bias current IB1 and includes a tenth-transistor PM〇Su having a source electrically connected to the DC voltage VDD. A gate electrically connected to a dust-dusting voltage Vbp, and a gate electrically outputting the first partial current ΐβι. The first differential circuit B1 is coupled to the DC bias voltage through the tangent τ > ^^^, and is used to convert the received M into a current, a solar PMOS1 and a second transistor pM(10). The two crystals [body] 11 201145813 PMOS1, 2 respectively have a gate, a source and a drain. The second differential circuit is coupled to the DC bias circuit through the switching device, and is configured to convert the received voltage into a current, and includes a ninth transistor PMOS9 and a tenth transistor pM〇Si Hey. The two transistors PMOS 9, 10 have a gate, a source and a drain, respectively. The switching device T is configured to switchably transmit the first set of differential voltages or bias voltages M Vbp to the gates of the two transistors PM (10), 2, and to switch the second set of differential voltages or the biases Press the voltage to the gate of pM〇s9'. Preferably, the first and second sets of differential voltages of this example are the same. It is worth noting that when the switching device τ delivers the first set of differential voltages to the gates of one of the transistors PM0S1, 2, the bias voltage is delivered to the gates of the transistors PM0S9, 1G. When the switching device transmits the bias voltage Vbp to the gates of the two transistors PMOS 1, 2, the second set of differential voltages are transferred to the gates of the PMOS 9, 1 。. Each of the differential circuits B1 and B2 operates in a differential mode or a bias mode because the received signals are different. The detailed action situation is explained below. Referring to FIG. 7', when the two transistors PM〇sl and w are respectively received by the first group of differential voltages vinl+ and Vinl', the differential circuit B1 operates in the differential mode by the two transistors PMOS1. The drain output of 2 is the first differential current idi of the alternating current. At this time, since the gates of the two transistors pM〇S9 and ι〇 respectively receive the bias voltage Vbp', the second differential circuit B2 operates in the bias mode and the second transistor PMOS9, 1〇 Two second bias currents I.B2 are output. The first and second differential circuits B1, B2 and the common mode bias circuit C will further act as an impedance to generate the set of 12 201145813 differential output voltages Vo+, Vo- based on the first differential current (4).

Referring to FIG. 8, on the other hand, when the gates of the two transistors PMOS1 and 2 respectively receive the bias voltage Vbp, the first differential circuit B1 operates in the bias mode and the drain output of the two transistors PMOS1, 2 is two. The third bias current IB3. At this time, since the gates of the two transistors PMOS9, 10 respectively receive the second set of differential voltages Vin2+, Vin2-, the second differential circuit B2 operates in the differential mode and outputs the drains of the PMOSs 9, 10 The second differential current id2. The first and second differential circuits B1, B2 and the common mode bias circuit C will further act as an impedance to generate the set of differential output voltages Vo+ ' Vo- ° according to the second differential current id2. G is electrically coupled to the common mode bias circuit C and the switching device T, and provides a gain to amplify impedance effects from the first and second differential circuits B1, B2 and the common mode bias circuit C To increase the amplitude of the set of differential output voltages Vo+, Vo-. Referring back to FIG. 6, a common-mode feedback (CMFB) circuit CF detects the set of differential output voltages Vo+, Vo-, and sends a desired common mode value of the set of differential output voltages to A preset value of the common mode control voltage VCMFB, and the detailed description of this circuit can be found in "D. Senderowicz, S. Dreyer, J. II. Huggins, CF Rahim, and CA Laber," A family of differential NMOS analog circuits for a PCM codes filter chip," IEEE J. Solid-State Circuits, vol. SC-17, Dec. 1982, pp. 1014-1023", "R. Castello and PR Gray, "A high-performance micropower switched-capacitor filter , IEEE J. Solid-State Circuits, vol. SC-20, no. 6, Dec..i 13 201145813 1985, pp. 1122-1132", but is not limited to this document. The common mode bias circuit C is configured to receive the common mode control voltage to maintain an average value of the set of differential output powers M VQ+ and VG_ at a preset value. Furthermore, in detail, the implementation of the gain circuit G of this example is: including - fifth, sixth transistor face 〇S5, 6, a seventh, eight transistor PM 〇 S7, 8 and four amplification orders & G1~G4. The input ends of the four amplification units G1 G G4 are electrically connected to the transistors 55, 6, respectively.

The source of the PM 〇 S7'8, and the outputs of the four amplifiers (1) (10) are electrically connected to the gates of the transistors NM0S5, 6, PM 〇 S7, 8, respectively. The small electrodes of the two transistors PM〇S7 and 8 are electrically connected to the drains of the two crystal faces (10) and 6, respectively, and output the set of differential output voltages ν〇·, v〇+. The implementation of the switching device T of the present example is: six first switches S1 and six second switches including the first differential circuit 电 electrically connected, and six electrically connected second differential circuits B2 The first switch si and the six second switches S2. Each switch has a first end, a second end and a control end and each control terminal is (4) switched between the associated first end and the third end between conducting and non-conducting.

Two of the six first openings M S1 electrically connected to the first-differential circuit B1 receive the first-group differential (four)+, Vml-' by respective first ends and by respective second The terminals are electrically connected to the gates of the two transistors PMOS1, 2, respectively. The other two of the six first switches S1 electrically connected to the first differential circuit B1 are electrically connected to the sources of the two transistors PMOS1 and 2 by respective first ends, and by respective The two ends are electrically connected to the drain of the circuit 14 201145813 crystal PMOS11, respectively. The remaining two of the six first switches S1 electrically connected to the first differential circuit B1 are electrically connected to the sources of the two transistors NM〇S5'6 by respective first ends, and by respective The second ends are electrically connected to the drains of the two transistors PM0S1, 2, respectively.

One of the six second switches S2 electrically connected to the first differential circuit B1 receives the bias voltage Vbp by the respective first ends, and electrically connects the two terminals by the respective second ends. a gate of the crystal p M 〇s丨, 2: the other of the six second switches S2 electrically connected to the first differential circuit B1 is electrically connected to the two transistors by respective first ends The sources of PM0S1 and 2 are electrically connected to the DC voltage VDD by respective first ends. The six seconds of the switch are electrically connected to the source of the two transistors PMOS 7 8 by respective first ends and electrically connected to the two transistors by respective second ends. The drain of PMOS 1, 2. And two of the six S1s electrically connected to the second differential circuit Β2, respectively, receive the bias voltage by the first terminal from the junction gateway.

Vbp' and the gates of the second transistor PMOS9'10 are electrically connected by their respective first-eighth knives. y electrically connecting the other two of the six first switches of the second differential lightning performance circuit B2 to be electrically connected to the sources of the two PMOSs 9, 10 by respective 苐^, And the jade day is electrically connected to the 兮DC voltage VDD by the respective first ends. The remaining ones of the six first switches si electrically connected to the second differential circuit B2 are electrically connected to the sources of the two transistors 、7, 8 by respective first ends. The poles are electrically connected to the drains of the two transistors PMOS 9, 1 , respectively, by respective second ends. One of the six second switches of the second differential circuit B2 is hunted by the respective first ends to receive the second differential voltages Vin2+, Vni2-' and by respective second ends The gates of the two transistors PMOS 9, 10 are electrically connected, respectively. The other of the six second switches s2 electrically connected to the second differential circuit B2 is electrically connected to the sources of the two transistors PMOS9, H by respective first ends, and by respective The first end is electrically connected to the drain of the transistor PMOS11, respectively. The remaining two of the six second switches 电 electrically connected to the second differential circuit B2 are electrically connected to the sources of the two transistors NMOS 5, 6 respectively by the respective first ends, and by respective The two ends are electrically connected to the poles of the two transistors PMOS 9, 10, respectively. The switching device T is controlled according to a control signal such that all of the first switches S1 are turned on or off synchronously, and all of the second switches S2 are simultaneously turned on or off. It is also worth noting that the conduction periods of the first and second switches s i and S2 do not overlap each other. Thus, when all of the first switches S1 are turned on and all of the second switches S2 are not turned on, the first differential circuit B1 operates in the differential mode, and the second differential circuit B2 operates in the bias mode. When all of the first switches si are not turned on and all of the second switches S2 are turned on, the first differential circuit B1 operates in the bias mode 16 201145813 and the second differential circuit B2 operates in the differential mode. In addition, the common mode bias circuit C is electrically connected to the gain circuit G and the common mode feedback circuit CF, and coupled to the first through the switching device T. One or two differential circuits B1, B2. The common mode bias circuit C includes an NMOS 3, 4. The gates of the two transistors NMOS3, 4 receive the common mode control voltage VcMFB J from the common mode feedback circuit CF. The sources of the two transistors NMOS3, 4 are electrically connected to the ground, and the drains of the NMOSs 3 and 4 are respectively Electrically connected to the sources of the two transistors NMOS5, ^6. Since the present embodiment uses a folded-cascode architecture composed of the first and second differential circuits B1 and B2, the switching device T, and the gain circuit G, compared with the prior art, Large output amplitude. The third to sixth transistors NMOS 3 to 6 in this embodiment are an N-type metal oxide semiconductor field effect transistor (NMOS), and the first, second, seventh to eleven transistors PMOS 1, 2, 7 ~11 is a P-type metal oxide semiconductor field effect transistor (PM0S). Further, as shown in Fig. 9, a modification of the second preferred embodiment, wherein the difference is that the circuit operation without the gain circuit G is similar to that of the second preferred embodiment and will not be described again. <Third Preferred Embodiment> As shown in FIG. 10, the difference from the second preferred embodiment is that the NMOS is changed to PMOS and the PMOS is changed to NMOS, wherein the third and fourth transistors PMOS3, The source of 4 is electrically connected to the DC voltage VDD, and the source of the gas 17 201145813 eleventh transistor NMOS 11 is electrically connected to ground, and is electrically connected to a portion of the second switch S2 of the first differential circuit B1. The second end is electrically connected to the ground, and the second end of the first switch S1 electrically connected to the second differential circuit B2 is electrically connected to the ground. The rest of the switch is similar to the operation because of its connection relationship, and therefore will not be described again. Further, as shown in Fig. 11, a modification of the third preferred embodiment, wherein the difference is that the circuit operation without the gain circuit G is similar to that of the third preferred embodiment and will not be described again. Furthermore, all the above embodiments are not limited to being implemented by a metal oxide semiconductor field effect transistor (MOS), but may also be modified into a double carrier junction transistor (bjt) to achieve the training, and the preferred embodiment of the present invention. The example has the following advantages in the architecture of the co-occurrence operational amplifier of the analog/digital conversion device: 1_ switching between the differential mode and the bias mode by the first and second differential circuits A1, A2 or B1' B2, Can eliminate the residual memory effect. 2. Compared with the prior art, the amplitude of the differential output voltage of the present invention is large, so that it can withstand a large amount of noise, and because the noise is proportional to 2 (k: waveman constant 'T: absolute temperature, C: Capacitance value), so the size of the capacitor pushed by this method can be reduced. 'If you don't need to push too much capacitance, you can reduce the size of the MOS, so that the total area is reduced, and the cost is reduced. 3. Moreover, because of the large noise that can be tolerated, the supply of a smaller DC voltage, i, achieves the same signal-to-noise ratio (SNR) as in the prior art. Therefore, power consumption can be reduced. 18 201145813 The above description is only intended to limit the scope of the invention and the scope of the invention. [Simple description of the scheme] The best example of the month is the case. If not, the equivalent change and modification of the patent application form according to the present invention are still shown in the circuit diagram of the conventional operational amplifier.

2 is a circuit diagram of the first preferred embodiment of the present invention. FIG. 3 is a first diagram of the output of the first preferred embodiment. FIG. 4 is a circuit diagram of the current of the differential current. FIG. 4 is a second differential output of the first preferred embodiment. Figure 5 is a circuit diagram of a modification of the first preferred embodiment; Figure 6 is a circuit diagram of a second preferred embodiment of the present invention; • θ 〇 - the preferred embodiment of the circuit diagram Θ β for outputting the first differential current. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 9 is a circuit diagram showing a modification of the second preferred embodiment; FIG. 9 is a circuit diagram of a second preferred embodiment of the present invention; and FIG. A circuit diagram of a preferred embodiment variant. 19 201145813 [Description of main component symbols] A1 ~2.....first and second differential circuits T..........switching circuits S1~2 ••...first and second switches G.. ........Gain circuit G1-4····. Amplifier unit NMOS1~2 first, two transistors NMOS7~8 seventh, eight transistors PMOS3~6 third~six transistor D.. ........DC bias circuit C..........Common mode bias circuit CF........Common mode feedback circuit B1-2 ••... First and second differential circuits PMOS1~2 first and second transistors PMOS7-11 seventh to eleven transistors NMOS3~6 third to sixth transistors 20

Claims (1)

201145813 VII. Patent application scope ··· An operational amplifier comprising: - a first differential circuit electrically connected to ground; a first differential circuit electrically connected between a DC voltage and a moving circuit; and a difference switch The device is electrically connected to the first and second differential circuits, and the switching device selectively operates the differential circuits in a differential mode; wherein, when the first differential circuit operates in a differential mode, The first set of differential voltages outputs a first differential current, and the first, differential circuit further acts as an impedance to generate a set of differential output voltages according to the first differential current; when the second differential circuit Operating in the differential mode, a second differential current is output according to a first set of differential voltages, and the first and second differential circuits further function as impedances to generate the set of differences according to the second differential currents. Dynamic output voltage. 2. The operational amplifier according to claim i, wherein: the first differential circuit comprises a first transistor and a second transistor, wherein the first and second transistors respectively have a gate and a gate a drain and a source electrically connected to the ground; the second differential circuit includes a third transistor and a fourth transistor. The third and fourth transistors respectively have a gate, a drain and an electric a source connected to the DC voltage, wherein the first and second transistors are electrically connected to the third and fourth transistors, respectively; when the switching device transmits the first set of differential voltages To the first and second [ 21 201145813 transistor gates and pass the second two bias voltages to the third The drain of the second output of the first differential current, the drain of the second and fourth transistors outputs the two bias currents; The switching device transmits the first bias voltage to the gate of the first, _ crystal and transmits the second set of differential voltages to the third and fourth transistors The drain of the second and fourth transistors outputs the second differential current. 3. The operational amplifier according to claim 2, further comprising: a circuit: electrically connected between the first 'two differential circuits, and providing a gain to be derived from the first and second differences The impedance of the moving circuit is amplified to increase the amplitude of the set of differential output voltages. 4. The operational amplifier according to claim 3, wherein the switching device switches each differential circuit between the differential mode and a bias mode; when the switching device operates the first differential circuit In the differential mode, the second differential circuit is operated in the bias mode to generate a two-bias current according to a second bias voltage; when the switching device operates the first differential circuit to the bias voltage The mode 'will cause the second differential circuit to operate in the differential mode, and the first differential circuit generates the two bias currents according to a first bias voltage. 5. The operational amplifier according to claim 4, wherein: the first differential circuit comprises a first transistor and a second transistor 201145813, wherein the first and second transistors respectively have a gate, a drain and a source electrically connected to the ground; the second differential circuit includes a third transistor and a fourth transistor, the second and fourth transistors respectively having a gate, a drain and a Electrically connected to the source of the DC voltage; when the switching device transmits the first set of differential voltages to the gates of the first and second transistors and transmits the second bias voltage to the third and fourth transistors a first differential circuit that outputs the first differential current from the drains of the first and second transistors, and the second differential circuit passes through the third and fourth transistors The pole outputs the two bias currents; when the switching device transmits the first bias voltage to the gates of the first and second crystals and transmits the second set of differential voltages to the gates of the third body, The first-differential circuit generates the two bias currents by the first and second transistors And the second differential circuit 6 will by the second, four drain electrode of the output transistor of the second differential current. The operational amplifier according to claim 5, wherein the = changing device comprises: (4) -= a second switch electrically connected to the first differential circuit, and two electrically connected to the second differential circuit One: * The first-switch 'mother-switch has a first end, - the first end and the - control end' and each control end is controlled to make the phase: the two ends switch between conduction and non-conduction; Each of the two first switches of the first differential circuit receives the first set of differential voltages by the respective ends of the first differential circuit, and is electrically connected to the first by the respective ends a gate of the second transistor; 23 201145813 electrically connecting the two respective first ends of the first differential circuit to receive the first bias voltage 7: respectively, by electrically connecting the second terminal The gates of the first and second transistors; the respective second ends of the second differential circuits respectively receiving the second bias voltages: respectively, are electrically connected by the second ends The gates of the third and fourth transistors; the two second openings of the second differential circuit electrically connected Off, the first end of the first group receives the second set of differences respectively. The straw is electrically connected to the gates of the third and fourth transistors respectively. According to the operational amplification described in the scope of the patent application, the gain circuit comprises a fifth transistor, a sixth transistor, a seventh; a solar cell, a germanium transistor and four amplifying units; The input ends of the amplifying units are electrically connected to the sources of the fifth to eighth transistors, respectively, and the output ends of the four amplifying units are electrically connected to the gates of the fifth to eighth transistors, respectively; The sources of the fifth to eighth transistors are electrically connected to the drains of the first, first, and second transistors, respectively; the drains of the seventh and eighth transistors are electrically connected to the fifth and second transistors respectively. The pole 'and outputs the set of differential output voltages. 8. The operational amplifier according to claim 7, wherein the first, second, seventh, and eighth transistors are a germanium-type metal oxide semiconductor field effect transistor; the third, fourth, fifth, and sixth The transistor is a germanium-type metal oxide semiconductor field effect transistor. 24 201145813 9. An operational amplifier comprising: a first differential circuit for generating a direct current, coupled to the DC bias circuit; and the second differential circuit coupled to the DC bias circuit; 'Electrically connecting the first and second differential circuit changing devices to selectively operate the differential circuits in a differential mode; and a common mode biasing circuit electrically connecting the switching device; wherein, when the first differential The circuit operates in a differential mode, and the DC bias circuit is coupled to the DC bias circuit to receive the first bias current, and outputs a first differential current according to a first set of differential voltages, and the a differential circuit and the common mode bias circuit further act as an impedance to generate a set of differential output voltages according to the first differential current; when the second differential circuit operates in the differential mode, The DC bias circuit is coupled to receive the first bias current through the switching device, and output a second differential current according to a second set of differential voltages, and the first and second differential circuits and the The common mode bias circuit will further act as an impedance and according to the second difference The moving current generates the set of differential output voltages; and the δ hai common mode bias circuit maintains the average of the set of differential output voltages at a predetermined value according to a common mode control voltage. 10. The operational amplifier according to claim 9, wherein the switching device switches each differential circuit between the differential mode and a bias mode; and when the switching device operates the first differential circuit In the differential mode [s 25 201145813, the second differential circuit is operated in the bias mode to generate two second bias currents according to a bias voltage; when the switching device causes the first differential circuit Operating in the bias mode causes the second differential circuit to operate in the differential mode, and the first differential circuit generates two third bias currents based on the bias voltage. The operational amplifier according to claim 10, wherein: the first differential circuit comprises a first transistor and a second transistor, wherein the first and second transistors respectively have a gate, One source and one bungee The second differential circuit includes: a ninth transistor and a tenth transistor, the ninth and tenth transistors respectively having a gate, a source and a drain; the switching device is configured to switch the transfer a first set of differential voltages or the bias voltages to the gates of the first or second transistor, and for switchingly transmitting the second set of differential voltages or the bias voltages to the ninth or tenth The gate of the body is 'and the switching of the first bias flow to the first a source of a transistor or a source of the ninth or tenth transistor; wherein the switching device transmits the first set of differential voltages to the gate of the first transistor and transmits the bias to the gate帛9, 10th transistor gate' The first-differential circuit receives the first-(fourth) A by the source of the second transistor, and by the first and second transistors; outputting the first a differential current 'the second differential circuit outputs the second bias current through the drain of the first and ten transistors; and the second transistor transmits the bias voltage to the first a gate of 2011458458 and transmitting the second set of differential voltages to the gates of the ninth and tenth transistors, the first differential circuit outputting the second through the first and second transistors Three bias currents, and the second differential circuit receives the first bias current through the sources of the ninth and tenth transistors, and outputs the second through the drains of the ninth and tenth transistors Differential current. 12. The operational amplifier according to claim 5, further comprising: a gain circuit electrically connected to the common mode bias circuit and the switching device, and providing a gain to receive the first and second differences The impedance of the dynamic circuit and the common mode bias circuit is amplified to increase the amplitude of the set of differential output voltages. The operational amplifier according to claim 12, wherein the increased I circuit comprises a fifth transistor, a sixth transistor, a seventh electric solar cell, an eighth transistor, and four The input ends of the four amplifying units are electrically connected to the sources of the fifth to eighth transistors, respectively, and the output ends of the four amplifying units are electrically connected to the gates of the fifth to eighth transistors, respectively pole; ^, /, the source of the transistor is electrically connected to the third, the drain of the transistor, and the sources of the seventh and eighth transistors are respectively coupled to the first and second by means of a switching device The drain of the transistor; the drain of the seventh 'eight transistor is electrically connected to the drain of the fifth transistor, respectively, and outputs the set of differential output voltages. 14. The operational amplifier according to claim 13, wherein the DC-DC partial circuit comprises an eleventh transistor, the eleventh transistor shoulder having a source electrically connected to the DC voltage, - a gate connected to the biased f 27 201145813 and a drain outputting the first bias current. 15. The operational amplifier according to claim 14, wherein the switching device comprises six first-to-negative-switches electrically connected to the first differential path, and a switch, and an electrical connection. The sixth differential of the second differential circuit and the six second switches, each of which is closed to the second end of the second terminal, and the control terminals are controlled so that the associated first-throw is turned on and Switching between non-conducting; - electrically connecting the first of the six first switches of the first differential circuit to each other by the respective first ends respectively receiving the first set of differentials from the second end - the gate of the second transistor is electrically connected to the first switch of the first differential circuit, and the first switch is electrically connected to the source of the first and second bodies respectively by the respective first ends Electrically connected to the drain of the tenth transistor by the respective second ends; the remaining two of the six first switches electrically connected to the first differential circuit are respectively connected by the respective first ends Electrically connected to the fifth 'six electric shovel: the fault is electrically connected by the respective second end The first and a crystal are infinite; the six second switches electrically connected to the first differential circuit respectively receive the bias voltage by respective first ends, and the second ends are electrically connected to the second terminal The interpole of the first and second transistors, and the other two of the six second switches connected to the first differential circuit are electrically connected to the first by the respective first ends, 28 201145813 The source of the crystal, and by the respective voltage; the first file is not electrically connected to the current-current connection of the first-differential circuit; the second will be separated by the respective first end The rider is electrically connected to the seventh and eighth electro-crystals and electrically connected to the drains of the first and second transistors respectively by the respective second ends; The two differential switches of the two differential-distributed 丄-m-m under-differential circuits are respectively received by the μ μ 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐 乐The interpole of the nine or ten transistors; the other of the six first switches that are connected to the first differential circuit == The first ends are electrically connected to the ninth and tenth electrical voltages respectively, and the remaining second ends are electrically connected to the remaining ones of the six first-switches of the DC-忒-differential circuit respectively. The respective ends are electrically connected to the sources of the seventh and eighth transistors, respectively, and the second ends of the ninth and tenth solar days are respectively electrically connected by the respective second ends; Second, the two of the six second switches electrically connected to the second differential circuit respectively receive the second differential current by the respective first ends, and the first ends of the respective electrical connections are electrically connected The gates 9 of the ninth and tenth transistors are electrically connected to the six second switches of the second differential circuit: 'will be electrically connected to the first and tenth wires respectively by the respective first ends The source of the crystal is electrically connected to the parallel pole of the eleventh, 29 201145813 transistor by respective second ends. The first ends of the six second switches of the first differential circuit, ^μ j, ^ , 7rj m ^ mm 曰B - a are electrically connected to the sources of the fifth and sixth electric bodies, respectively And the ninth, the transistor of the transistor is electrically connected by the respective second ends by the respective white electrical faults. 16. The operation amplification according to claim 15, wherein the common mode bias circuit comprises a third transistor and a fourth transistor; The drains of the second and fourth transistors are electrically connected to the sources of the fifth and sixth transistors, respectively, and the sources of the third and fourth transistors are electrically connected to the ground respectively, and the gates of the third and fourth transistors are respectively The operational amplifier of the sixth aspect of the invention, wherein the second to sixth transistors are an N-type metal oxide semiconductor field effect transistor; The second, seventh to eleven transistors are a P-type metal oxide semiconductor field effect transistor. The operational amplifier according to claim 10, wherein: the common mode bias circuit comprises a third transistor and a fourth transistor, wherein the drains of the third and fourth transistors are electrically connected to The sources of the fifth and sixth transistors 'the third and fourth transistors are respectively electrically connected to the DC voltage, and the gates of the third and fourth transistors receive the common mode control voltage; the DC bias The circuit includes a second-electrode, the third-electrode 30 201145813 crystal having a source electrically connected to the ground, a gate electrically connected to the bias voltage, and a first bias current generated Bungee jumping. 19. The operational amplifier according to claim 18, wherein the second to sixth transistors are a P-type metal oxide semiconductor field effect transistor; the first, second, seventh to eleventh The transistor is an N-type metal oxide semiconductor field effect transistor. 20. The operational amplifier according to claim 9 of the patent application, further comprising: a common mode feedback circuit for detecting the differential output voltage of the group and sending a common mode adjustment for which the differential output is desired to be output. The common mode control voltage to the preset value. 31