JP2007274631A - Differential amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a differential amplifier circuit of which frequency characteristics are excellent. <P>SOLUTION: Diode connecting transistors 5, 6 of a differential amplifier circuit 1 includes transistor elements M2BP, M2BM including source terminals S1, S2 and transistor elements M2AP, M2AM connecting source terminals S3, S4 to drain terminals D1, D2 of the transistor elements M2BP, M2BM. Gate terminals G1, G2 of the transistor elements M2BP, M2BM and gate terminals G3, G4 of the transistor elements M2AP, M2AM are connected to drain terminals D3, D4 of the transistor elements M2AP, M2AM and the source terminal S3 of the transistor element M2AP and the source terminal S4 of the transistor element M2AM are connected to each other, and differential output terminals are the drain terminals D3, D4 of the transistor elements M2AP, M2AM of the diode connecting transistors 5, 6. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a fully differential amplifier circuit capable of high-speed operation with a low power supply voltage.

  There is a telescopic cascode amplifier as a differential amplifier circuit formed by a CMOS process. This telescopic cascode amplifier is disclosed in, for example, FIG. 2. When used in a feedback circuit such as a switched capacitor amplifier circuit and a sample-and-hold circuit, this telescopic cascode amplifier has features such as good stability, low power consumption, excellent high speed, and simple configuration.

  However, a problem arises when a telescopic cascode amplifier is formed by a fine CMOS process or the like. Since the input voltage of this telescopic cascode amplifier is usually far away from the ground level and power supply level (because the power supply voltage is VDD, it becomes a voltage close to VDD / 2), so when used in a switched capacitor circuit, this telescopic cascode amplifier There is a problem that the on-resistance of the analog switches connected to the input terminals of the amplifiers is increased, which requires a circuit for boosting the gate voltages of those analog switches.

  Also, FIG. When a telescopic cascode amplifier is used for the Integrator 1 shown in 3.8.2, since a plurality of analog switches are connected to the input terminal, a plurality of booster circuits are required, and there is a problem that power consumption and circuit area increase. .

  In order to solve this problem, a current mirror type differential amplifier circuit is used. For example, a current mirror type differential amplifier configured as shown in Non-Patent Document 2 or Non-Patent Document 3 is used.

  FIG. 6 is a circuit diagram showing a configuration of a conventional fully differential amplifier circuit 90. The fully differential amplifier circuit 90 includes P-channel MOS transistors M1a and M1b. A differential input voltage vinp is applied to the gate terminal of the P-channel MOS transistor M1a. A differential input voltage vinm is applied to the gate terminal of the P-channel MOS transistor M1b. The source terminal of the P-channel MOS transistor M1a and the source terminal of the P-channel MOS transistor M1b are connected to the drain terminal of the P-channel MOS transistor Mc. The source terminal of the P-channel MOS transistor Mc is connected to the common line, and the voltage vb5 is applied to the gate terminal.

  The drain terminal of the P-channel MOS transistor M1a is connected to the drain terminal of the N-channel MOS transistor M2a. The source terminal of the N-channel MOS transistor M2a is connected to the drain terminal of the N-channel MOS transistor M2b. The source terminal of the MOS transistor M2b is connected to another common line. The gate terminal of the MOS transistor M2b is connected to the drain terminal of the MOS transistor M2a.

  The drain terminal of the P-channel MOS transistor M1b is connected to the drain terminal of the N-channel MOS transistor M2c. The source terminal of the N-channel MOS transistor M2c is connected to the drain terminal of the N-channel MOS transistor M2d. The source terminal of the MOS transistor M2d is connected to the common line. The gate terminal of the MOS transistor M2d is connected to the drain terminal of the MOS transistor M2c.

  The drain terminals of MOS transistors M2a and M2c are connected to the drain terminals of N-channel MOS transistors M2e and M2f, respectively, and the source terminals of MOS transistors M2e and M2f are connected to a common line. The input voltage vb1 is applied to the gate terminals of the MOS transistors M2e and M2f.

  The fully differential amplifier circuit 90 is provided with N-channel MOS transistors M3a and M3b connected in series. The gate terminal of the MOS transistor M3b is connected to the gate terminal of the MOS transistor M2b. The source terminal of the MOS transistor M3b is connected to the common line.

  The fully differential amplifier circuit 90 includes N-channel MOS transistors M3c and M3d connected in series. The gate terminal of the MOS transistor M3d is connected to the gate terminal of the MOS transistor M2d. The source terminal of the MOS transistor M3d is connected to the common line. The gate terminals of the MOS transistors M3a, M2a, M2c, and M3c are connected to each other and applied with the input voltage vb2b.

  The fully differential amplifier circuit 90 is provided with P-channel MOS transistors M4a and M4b connected in series. The voltage vb4b is applied to the gate terminal of the MOS transistor M4b. The MOS transistors M3a and M4b are connected to an output terminal from which the differential output voltage voutp is output.

  The fully differential amplifier circuit 90 is provided with P-channel type MOS transistors M4c and M4d connected in series. The voltage vb4b is applied to the gate terminal of the MOS transistor M4d. The MOS transistors M3c and M4d are connected to an output terminal from which the differential output voltage voutm is output. The output voltage of the common mode feedback circuit CMFB is applied to the gate terminals of the MOS transistors M4a and M4c.

By using this amplifier, it becomes possible to bring the input voltage of the amplifier closer to the ground level (potential of the lower common line), and the on-resistance of the analog switch connected to the input terminal of this amplifier can be reduced. It is. In addition, since this amplifier has a feature that a trade-off between bandwidth and noise can be set by setting a current mirror ratio (Non-patent Document 2: Presentation Material, page 8), the power consumption is lower than that of a telescopic cascode amplifier. It is possible.
G. Nicollini et. Al., “A Fully Differential Sample-and-Hold Circuit for High-Speed Applications”, IEEE Journal of Solid-State Circuits, vol.24, no.5, pp.1461-1465, Oct. 1989 . Y. Fujimoto, et. Al., “An 80 / 100MS / s 76.3 / 70.1dB SNDR DS ADC for Digital TV Receivers”, IEEE International Solid-State Circuits Conference, Feb. 2006. (including presentation slides) L. Yao, et. Al., “A 0.8-V 8-uW, CMOS OTA with 50-dB Gain and 1.2-MHz GBW in 18-pF Load”, 29th European Solid-State Circuits Conference, Sept. 2003.

  However, the configuration of the current mirror type differential amplifier circuit shown in FIG. 6 has a problem that the output common mode voltage fluctuates greatly during slewing. Slewing is a phenomenon that occurs when the differential output voltage voutp-voutm changes greatly. At this time, the current that can be supplied from the output terminals (voutp and voutm) as differential output is I, and the differential output terminal If the load capacitance connected to C is C, the time change of the differential output voltage is I / C (slew rate).

  The bias conditions in the steady state are assumed as shown in (Table 1) below.

  The current mirror ratio between the MOS transistors M3d and M2d (between the MOS transistors M3b and M2b) is set to 2.

  At the time of slewing, a differential voltage having a large difference between the differential input voltage vinp and the differential input voltage vinm is applied (considering a case where the differential input voltage vinp−the differential input voltage vinm is large). . At this time, the MOS transistor M1a is turned off and the MOS transistor M1b is turned on. If the current flowing through the MOS transistor Mc is 2 × IIN, all of the current flows through the MOS transistor M1b. Since a constant current 0.5 × IIN always flows through the MOS transistors M2e and M2f, a current of 3 × IIN tends to flow through the MOS transistor M3d. On the other hand, no current flows through the MOS transistor M3b.

  On the other hand, a current of IIN always flows through the MOS transistors M4a and M4c to which the output voltage of the CMFB circuit is fed back. Therefore, the voutm terminal tries to draw a current of 2 × IIN from the load connected to the voutm terminal, but the voutp terminal tries to output the IIN current from the load connected to the voutp terminal. In order to keep the common mode stable, the value of the current drawn between the differential output terminals needs to be the same as the value of the output current. However, since there is a difference between the currents in the operational amplifier of FIG. 6 (IIN and 3 × IIN), the output common mode voltage (voutp + voutm) / 2 fluctuates greatly during slewing. In order to suppress the fluctuation, it is necessary to pass a large amount of current through the MOS transistors M4a and M4c which are output stages, and the power efficiency is deteriorated.

  In order to solve this problem, the amplifier circuit on the output side (MOS transistors M3a to M3d and M4a to M4d) is replaced with an amplifier (FIG. 2 of Non-Patent Document 1) configured by a differential pair and a tail transistor. This can be avoided by replacing, but in that case, the bias voltage of the differential input pair of the amplifier becomes high, and the diode-connected transistor of the amplifier circuit on the input side (MOS transistors Mc, M1a, M1b, M2a to M2f). It is necessary to reduce the W / L (W: channel width, L: channel length) of the MOS transistor M2b and the MOS transistor M2d and increase the impedance. When the impedance between the MOS transistor M2b and the MOS transistor M2d is increased, the frequency characteristic is deteriorated (the phase margin of the differential amplifier circuit is deteriorated and unstable when the differential amplifier circuit is used in the feedback circuit). become).

  The present invention has been made in view of the above-described problems, and an object of the present invention is to increase the common mode impedance and to reduce the differential impedance in a pair of diode-connected transistors used in a differential amplifier circuit. The object is to provide a pair of diode-connected transistors that can be reduced. Furthermore, by using the diode-connected transistor, it is to realize a differential amplifier circuit having a stable common mode output voltage without deterioration of frequency characteristics.

  In order to solve the above-described problem, a fully differential amplifier circuit according to the present invention includes a pair of diode-connected transistors arranged in parallel to each other, and each diode-connected transistor has a predetermined bias voltage. A first transistor element having a source terminal to be applied; a second transistor element having a source terminal connected to a drain terminal of the first transistor element; the gate terminal of the first transistor element; The gate terminal of the transistor element is connected to the drain terminal of the second transistor element, the source terminal of the second transistor element provided in one diode-connected transistor, and the second transistor provided in the other diode-connected transistor The source terminal of the element is connected to each other, and the differential output terminal Characterized in that it is a drain terminal of the second transistor element provided to each diode-connected transistor.

Due to this feature, the transconductance of the second transistor element provided in each diode-connected transistor is made much larger than the transconductance of the first transistor element, thereby reducing the differential mode impedance _ZDM, while reducing the common mode impedance. it is possible to increase the impedance _{Z CM.} Further, by increasing the W / L of the second transistor element of each diode-connected transistor and decreasing the W / L of the first transistor element of each diode-connected transistor, while maintaining the differential mode impedance Z _DM small, The gate voltage of the first transistor element and the second transistor element of the diode-connected transistor can be increased. For this reason, it is possible to set the input bias voltage of the post-stage amplifier circuit to a desired value while keeping the differential impedance of the pair of diode-connected transistors at a desired value. As a result, it is possible to prevent the deterioration of the frequency characteristics due to the increase in the differential impedance of the pair of diode-connected transistors.

  The fully differential amplifier circuit according to the present invention preferably further includes a current source connected to a drain terminal of a second transistor element provided in each diode-connected transistor.

  According to the above configuration, the size of the differential pair MOS transistor and the current flowing can be increased without increasing the size of each diode-connected transistor, and noise and bandwidth can be improved. That is, since most of the current flowing through the differential pair MOS transistor is caused to flow through a pair of current sources (the current source is configured by a MOS transistor), the current flowing through each diode-connected transistor can be reduced.

  In the fully differential amplifier circuit according to the present invention, it is preferable that the first transistor element and the second transistor element respectively provided in each diode-connected transistor have the same polarity.

  According to the above configuration, it is possible to configure a fully differential amplifier circuit in which the terminal of the second transistor element opposite to the first transistor element is the differential output terminal.

  In order to solve the above problems, the differential amplifier circuit according to the present invention is a differential amplifier circuit further comprising a first stage amplifier circuit and a rear stage amplifier circuit provided on the rear stage side of the first stage amplifier circuit. The circuit is the fully differential amplifier circuit of the present invention.

  According to the above configuration, the present invention can be applied to a two-stage differential amplifier circuit.

  In order to solve the above problems, another fully differential amplifier circuit according to the present invention includes a pair of diode-connected transistors arranged in parallel to each other, wherein each diode-connected transistor has a predetermined bias. A first transistor element having a first polarity having a source terminal to which a voltage is applied; and a second transistor element having a second polarity different from the first polarity and having a drain terminal connected to a drain terminal of the first transistor element. And the gate terminal of the first transistor element and the gate terminal of the second transistor element are connected to the drain terminal of the second transistor element, and the second transistor element provided in one diode-connected transistor is provided. Source terminal and source of second transistor element provided in the other diode-connected transistor Terminal and, are connected to each other, the differential output terminals, characterized in that the drain terminal of the second transistor element provided to each diode-connected transistor.

Therefore, by making the transconductance of the second transistor element of the second polarity provided in each diode-connected transistor far larger than the transconductance of the first transistor element of the first polarity, the differential mode impedance Z _DM one to reduce, it is possible to increase the common-mode impedance Z _CM. Further, by increasing the W / L of the second transistor element of the second polarity of each diode-connected transistor and decreasing the W / L of the first transistor element of the first polarity of each diode-connected transistor, the differential mode impedance The gate voltage of the first transistor element of the first polarity and the second transistor element of the second polarity of one diode-connected transistor can be increased while keeping Z _DM small. For this reason, it is possible to set the input bias voltage of the post-stage amplifier circuit to a desired value while keeping the differential impedance of the pair of diode-connected transistors at a desired value. As a result, it is possible to prevent the deterioration of the frequency characteristics due to the increase in the differential impedance of the pair of diode-connected transistors.

  As described above, in the fully differential amplifier circuit according to the present invention, the gate terminal of the first transistor element and the gate terminal of the second transistor element are connected to the drain terminal of the second transistor element, and one diode connection is made. Since the source terminal of the second transistor element provided in the transistor and the source terminal of the second transistor element provided in the other diode-connected transistor are connected to each other, the differential impedance of the pair of diode-connected transistors is reduced. It is possible to set the input bias voltage of the post-stage amplifier circuit to a desired value while maintaining the desired value, and it is possible to prevent deterioration of frequency characteristics due to an increase in the differential impedance of the pair of diode-connected transistors. There is an effect.

  In the other fully differential amplifier circuit according to the present invention, as described above, the gate terminal of the first transistor element and the gate terminal of the second transistor element are connected to the drain terminal of the second transistor element. Since the source terminal of the second transistor element provided in the diode-connected transistor and the source terminal of the second transistor element provided in the other diode-connected transistor are connected to each other, the differential of the pair of diode-connected transistors It is possible to set the input bias voltage of the post-stage amplifier circuit to a desired value while maintaining the impedance at a desired value, and to prevent deterioration of the frequency characteristics due to an increase in the differential impedance of the pair of diode-connected transistors. There is an effect that can be done.

  An embodiment of the present invention will be described with reference to FIGS. 1 to 5 as follows.

(Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration of a fully differential amplifier circuit 1 according to the first embodiment. The fully differential amplifier circuit 1 includes a first stage amplifier circuit 2 and a rear stage amplifier circuit 3 provided on the rear stage side of the first stage amplifier circuit 2.

  In this specification, the “fully differential amplifier circuit” means an amplifier circuit having two differential inputs and two differential outputs. The “differential amplifier circuit” indicates that the input is a differential two input, and the output may be a single one output or a differential two output. Since a differential amplifier circuit having two differential inputs and a single single output is already well known, in the following embodiments, the differential amplifier circuit outputs two differential outputs. “Polarity” indicates whether it is an N-channel MOS or a P-channel MOS.

  The first stage amplifier circuit 2 has a diode-connected transistor block 4. The diode-connected transistor block 4 is provided with a pair of diode-connected transistors 5 and 6.

  The diode-connected transistor 5 includes N-channel MOS transistors M2BP and M2AP connected in series. The source terminal S1 of the MOS transistor M2BP is connected to a common line to which power is supplied. The drain terminal D1 of the MOS transistor M2BP is connected to the source terminal S3 of the MOS transistor M2AP. The gate terminal G1 of the MOS transistor M2BP and the gate terminal G3 of the MOS transistor M2AP are connected to the drain terminal D3 of the MOS transistor M2AP.

  The diode-connected transistor 6 includes N-channel MOS transistors M2BM and M2AM connected in series. The source terminal S2 of the MOS transistor M2BM is connected to the common line. The drain terminal D2 of the MOS transistor M2BM is connected to the source terminal S4 of the MOS transistor M2AM. The gate terminal G2 of the MOS transistor M2BM and the gate terminal G4 of the MOS transistor M2AM are connected to the drain terminal D4 of the MOS transistor M2AM.

  The first stage amplifier circuit 2 has a P-channel MOS transistor M1P. The drain terminal of the MOS transistor M1P is connected to the drain terminal D3 of the MOS transistor M2AP. A differential input voltage vinp is applied to the gate terminal of the MOS transistor M1P.

  The first stage amplifier circuit 2 is provided with a P-channel MOS transistor M1M. The drain terminal of the MOS transistor M1M is connected to the drain terminal D4 of the MOS transistor M2AM. A differential input voltage vinm is applied to the gate terminal of the MOS transistor M1M.

  The first stage amplifier circuit 2 has a P-channel MOS transistor M1C. The source terminal of the MOS transistor M1C is connected to another common line. The drain terminal of the MOS transistor M1C is connected to the source terminal of the MOS transistor M1P and the source terminal of the MOS transistor M1M. A voltage vb5 is applied to the gate terminal of the MOS transistor M1C.

  The post-stage amplifier circuit 3 has an N-channel MOS transistor M3M. The gate terminal of the MOS transistor M3M is connected to the drain terminal D4 of the MOS transistor M2AM. The post-stage amplifier circuit is provided with an N-channel MOS transistor M3P. The gate terminal of the MOS transistor M3P is connected to the drain terminal D3 of the MOS transistor M2AP.

  The post-stage amplifier circuit 3 has an N-channel type MOS transistor M3C. The source terminal of the MOS transistor M3C is connected to the common line, and the drain terminal is connected to the source terminal of the MOS transistor M3M and the source terminal of the MOS transistor M3P. The output voltage of the CMFB circuit is applied to the gate terminal of the MOS transistor M3C.

  The post-stage amplifier circuit 3 is provided with P-channel MOS transistors M4M and M4P. The source terminals of the MOS transistors M4M and M4P are connected to the drain terminal of the MOS transistor M1C through another common line. The gate terminal of the MOS transistor M4M and the gate terminal of the MOS transistor M4P are connected to each other, and the voltage vb5b is applied.

  The drain terminal of the MOS transistor M4M is connected to the drain terminal of the MOS transistor M3M. A differential output voutm is output from an output terminal provided between the MOS transistors M4M and M3M. The drain terminal of the MOS transistor M4P is connected to the drain terminal of the MOS transistor M3P. A differential output voutp is output from an output terminal provided between the MOS transistors M4P and M3P.

  The differential amplifier circuit 1 shown in FIG. 1 has a configuration in which two amplifier circuits (first stage amplifier circuit 2 and rear stage amplifier circuit 3) are connected in series. The first stage amplifying circuit 2 is a fully differential amplifying circuit having a relatively low gain, which is composed of MOS transistors M1C, M1P, M1M, M2AP, M2BP, M2AM, and M2BM. The post-stage amplifier circuit 3 is a differential amplifier circuit having a relatively high gain, which is configured by MOS transistors M3P, M3M, M3C, M4M, and M4P (basically the same as FIG. 2 of Non-Patent Document 1).

  In this differential amplifier circuit 1, a tail transistor (MOS transistor) M3C is added in order to keep the sum of the current values flowing through the MOS transistor M3P and the MOS transistor M3M as a differential pair constant. For this reason, the output common mode voltage is stabilized even during slewing.

  However, by employing this differential amplifier circuit, the input common mode voltage of the differential amplifier circuit (the average value of the gate voltages of the MOS transistor M3M and the MOS transistor M3P) is prevented from entering the linear region of the MOS transistor M3C. In addition, it is necessary to set a slightly higher voltage.

That is,
Vg3> Vgs3 + Vdsat3c,
here,
Vgs3: gate-source voltage of MOS transistors M3P and M3M,
Vdsat3c: a source-drain voltage required for the MOS transistor M3C to operate in the saturation region,
It is.

  In order to optimally bias the input common mode voltage, a diode-connected transistor 5 configured by MOS transistors M2AP and M2BP and a diode-connected transistor 6 configured by MOS transistors M2AM and M2BM are used as loads of the first stage amplifier circuit 2. The diode-connected transistor block 4 is employed.

  FIG. 2A is a circuit diagram for explaining the operation in the differential mode of the diode-connected transistor block 4, and FIG. 2B is a circuit diagram for explaining the operation in the common mode.

Differential mode impedance Z _DM and the common mode impedance Z _CM by small signal analysis is represented by approximately below each (Equation 1) and (Equation 2).

here,
gm _2A : transconductance of MOS transistors M2AP and M2AM,
gm _2B : transconductance of MOS transistors M2BP and M2BM,
It is.

When the transconductance gm _2A is configured to be much larger than the transconductance gm _2B (gm _2A >> gm _2B ), the differential mode impedance Z _DM is reduced while the common mode impedance Z _CM is increased. Can do.

Also, increasing the W / L of the MOS transistor M2AP · M2AM, by decreasing the W / L of the MOS transistor M2BP · M2BM, while keeping small the differential mode impedance _{Z DM,} the gate voltage of the MOS transistor M2AP · M2BP Can be high.

  In the case of the conventional differential amplifier circuit 90 shown in FIG. 6, in order to increase the gate voltage of the diode-connected transistors M2b and M2d, it is necessary to increase the differential impedance, which deteriorates the differential characteristics of the operational amplifier circuit. It was. According to the differential amplifier circuit 1 according to the first embodiment shown in FIG. 1, the input bias voltage of the post-stage amplifier circuit 3 is set to a desired value while maintaining the differential impedance of the diode-connected transistors 5 and 6 at a desired value. Can be set.

  In the first embodiment, an N-channel MOS transistor is used as the configuration of the diode-connected transistor, but a P-channel MOS transistor may be used. The same applies to the embodiments described later. In addition, although a MOS transistor is used here, the same configuration can be achieved using a bipolar transistor or the like.

(Embodiment 2)
FIG. 3 is a circuit diagram showing a configuration of the differential amplifier circuit 1a according to the second embodiment. The same components as those described in the first embodiment are given the same reference numerals. Therefore, detailed description of these components is omitted.

  The first stage amplifier circuit 2a of the differential amplifier circuit 1a includes a diode-connected transistor block 4a. The diode-connected transistor block 4a includes diode-connected transistors 5a and 6a. The diode-connected transistor block 4a is provided with a pair of N-channel type MOS transistors M2C (current source). One source terminal of the MOS transistor M2C is connected to the common line, and its drain terminal is connected to the drain terminal of the MOS transistor M2AP. The other source terminal of the MOS transistor M2C is connected to the common line, and its drain terminal is connected to the drain terminal of the MOS transistor M2AM. A predetermined constant voltage vb1 is applied to the gate terminals of the pair of MOS transistors M2C.

  By adding a pair of MOS transistors M2C in this way, the size of the differential pair MOS transistors M1P and M1M of the first stage amplifier circuit 2a and the current to flow are increased without increasing the size of the diode-connected transistors 5a and 6a. It is possible to improve noise and bandwidth. That is, since most of the current flowing through the differential pair MOS transistors M1P and M1M flows through the pair of MOS transistors M2C, the current flowing through the MOS transistors M2BP and M2BM can be reduced.

(Embodiment 3)
FIG. 4 is a circuit diagram showing a configuration of a fully differential amplifier circuit 1b according to the third embodiment. The fully differential amplifier circuit 1b has a diode-connected transistor block 4b. Diode connected transistors 5b and 6b are provided in the diode connected transistor block 4b.

  The diode-connected transistor 5b has a P-channel MOS transistor M2BPX and an N-channel MOS transistor M2AP connected in series. The source terminal S1X of the MOS transistor M2BPX is connected to the common line. The drain terminal D1X of the MOS transistor M2BPX is connected to the drain terminal D3 of the MOS transistor M2AP. The gate terminal G1X of the MOS transistor M2BPX and the gate terminal G3 of the MOS transistor M2AP are connected to the drain terminal D3 of the MOS transistor M2AP.

  The diode connection transistor 6b has a P-channel MOS transistor M2BMX and an N-channel MOS transistor M2AM connected in series. The source terminal S2X of the MOS transistor M2BMX is connected to the common line. The drain terminal D2X of the MOS transistor M2BMX is connected to the drain terminal D4 of the MOS transistor M2AM. The gate terminal G2X of the MOS transistor M2BMX and the gate terminal G4 of the MOS transistor M2AM are connected to the drain terminal D4 of the MOS transistor M2AM.

  The fully differential amplifier circuit 1b has a pair of N-channel MOS transistors M0C2. The source terminal of one N-channel MOS transistor M0C2 is connected to the other common line, and the drain terminal is connected to the source terminal S3 of the MOS transistor M2AP. The source terminal of the other N-channel MOS transistor M0C2 is connected to another common line, and the drain terminal is connected to the source terminal S4 of the MOS transistor M2AM. A predetermined constant voltage vb1a is applied to each gate terminal of the pair of MOS transistors M0C2. The source terminal S3 of M2AP and the source terminal S4 of M2AM are short-circuited.

  The fully differential amplifier circuit 1b has an N-channel MOS transistor M1P. The drain terminal of the MOS transistor M1P is connected to the drain terminal D3 of the MOS transistor M2AP. A differential input voltage vinp is applied to the gate terminal of the MOS transistor M1P.

  The fully differential amplifier circuit 1b is provided with an N-channel MOS transistor M1M. The drain terminal of the MOS transistor M1M is connected to the drain terminal D4 of the MOS transistor M2AM. A differential input voltage vinm is applied to the gate terminal of the MOS transistor M1M.

  The fully differential amplifier circuit 1b has an N-channel MOS transistor M0C. The source terminal of the MOS transistor M0C is connected to another common line. The drain terminal of the MOS transistor M0C is connected to the source terminal of the MOS transistor M1P and the source terminal of the MOS transistor M1M. The voltage vb1b is applied to the gate terminal of the MOS transistor M0C.

As described above, the diode-connected transistor may be configured by combining the N-channel MOS transistor and the P-channel MOS transistor. At this time, by setting transconductance gm _2A >> transconductance gm _2B , the common mode between the terminals is maintained while the differential mode impedance between the terminals to which the drain terminals of the differential transistors M1P and M1M are connected is kept low. Impedance can be increased. Also, the common mode voltage of the terminal can be lowered from the power supply voltage level without affecting the differential mode impedance.

  The fully-differential amplifier circuit 1b is used as a front-stage amplifier circuit, and a rear-stage amplifier circuit similar to that described in the first and second embodiments is added (the polarity of the rear-stage amplifier circuit in the first and second embodiments is inverted). It is necessary to form a fully differential amplifier circuit similar to the fully differential amplifier circuits 1 and 1a. At this time, the differential input of the subsequent stage amplifier circuit is connected to the drain terminals D3 and D4 of the transistors M2AP and M2AM, respectively.

(Embodiment 4)
FIG. 5 is a circuit diagram showing a configuration of a differential amplifier circuit 1c according to the fourth embodiment. The same components as those described in the first embodiment are given the same reference numerals. Therefore, detailed description of these components is omitted.

  In the differential amplifier circuit 1c, an N-channel MOS transistor M2C is provided between the diode-connected transistor block 4 and a common line to which power is supplied. The source terminal of the MOS transistor M2C is connected to the common line, and the drain terminal is connected to the source terminal of the MOS transistor M2BP and the source terminal of the MOS transistor M2BM. The gate terminal and the drain terminal of the MOS transistor M2C are connected to each other.

  As described above, by further disposing the diode-connected transistor between the diode-connected transistor and the power supply terminal, the voltage of the terminal TC can be biased to a constant value, and the output common mode voltage of the first stage amplifier circuit can be more flexible. It is possible to set.

  As described above, by using the differential amplifier circuit having the diode-connected transistor shown in the first to fourth embodiments as a load, it is possible to arbitrarily set the output common mode voltage while keeping the output differential impedance low. It becomes. Also, by combining the differential amplifier circuit of the embodiment with the differential amplifier circuit composed of a differential pair and a tail transistor, an operational amplifier circuit that can avoid common-mode instability that was a problem in the past has been realized. It becomes possible to do.

  The present invention is not limited to the differential amplifier circuit formed by the CMOS process, and can also be applied to a bipolar differential amplifier circuit.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The present invention can be applied to a differential amplifier circuit capable of high-speed operation with a low power supply voltage.

1 is a circuit diagram showing a configuration of a differential amplifier circuit according to a first embodiment. (A) is a circuit diagram for demonstrating operation | movement in the differential mode of a pair of diode connection transistor used as a load of a fully differential amplifier circuit, (b) is a circuit diagram for demonstrating operation | movement in a common mode. It is. FIG. 6 is a circuit diagram showing a configuration of a differential amplifier circuit according to a second embodiment. FIG. 5 is a circuit diagram showing a configuration of a fully differential amplifier circuit according to a third embodiment. FIG. 6 is a circuit diagram showing a configuration of a differential amplifier circuit according to a fourth embodiment. It is a circuit diagram which shows the structure of the conventional differential amplifier circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Differential amplifier circuit 2 First stage amplifier circuit 3 Later stage amplifier circuit 4 Diode connection transistor block 5, 6 Diode connection transistor M2BP, M2BM MOS transistor (1st transistor element)
M2AP, M2AM MOS transistor (second transistor element)
M2C MOS transistor (current source)
S1, S2 Source terminal D1, D2 Drain terminal G1, G2 Gate terminal S3, S4 Source terminal D3, D4 Drain terminal G3, G4 Gate terminal

Claims (5)

In a fully differential amplifier circuit comprising a pair of diode-connected transistors arranged in parallel with each other,
Each diode-connected transistor includes a first transistor element having a source terminal to which a predetermined bias voltage is applied;
A second transistor element having a source terminal connected to a drain terminal of the first transistor element;
A gate terminal of the first transistor element and a gate terminal of the second transistor element are connected to a drain terminal of the second transistor element;
The source terminal of the second transistor element provided in one diode-connected transistor and the source terminal of the second transistor element provided in the other diode-connected transistor are connected to each other,
A fully differential amplifier circuit, wherein the differential output terminal is a drain terminal of a second transistor element provided in each diode-connected transistor.   The fully differential amplifier circuit according to claim 1, further comprising a current source connected to a drain terminal of a second transistor element provided in each diode-connected transistor.   The fully differential amplifier circuit according to claim 1, wherein the first transistor element and the second transistor element respectively provided in each diode-connected transistor have the same polarity. In the differential amplifier circuit further comprising a first stage amplifier circuit and a rear stage amplifier circuit provided on the rear stage side of the first stage amplifier circuit,
The differential amplifier circuit according to claim 1, wherein the first stage amplifier circuit is the fully differential amplifier circuit according to claim 1. In a fully differential amplifier circuit comprising a pair of diode-connected transistors arranged in parallel with each other,
Each diode-connected transistor includes a first transistor element having a first polarity having a source terminal to which a predetermined bias voltage is applied;
A second transistor element having a second polarity different from the first polarity and having a drain terminal connected to a drain terminal of the first transistor element;
A gate terminal of the first transistor element and a gate terminal of the second transistor element are connected to a drain terminal of the second transistor element;
The source terminal of the second transistor element provided in one diode-connected transistor and the source terminal of the second transistor element provided in the other diode-connected transistor are connected to each other,
A fully differential amplifier circuit, wherein the differential output terminal is a drain terminal of a second transistor element provided in each diode-connected transistor.

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