JP2005347949A - Differential amplification circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a differential amplification circuit constituting a CMFB loop with phase compensation applied so that an in-phase output potential can be stably set to a desired set potential, and capable of spreading a bandwidth. <P>SOLUTION: The differential amplification circuit converts from voltage to current by an input transconductor 1, again converts the signal current from current to voltage by an output transconductor 2 constituting equivalent resistance on an output part for setting a voltage gain with a ratio of input and output transconductance values. Phase compensation capacitances C<SB>1</SB>and C<SB>2</SB>of an in-phase feedback circuit 3 for determining an in-phase output potential are connected between the source terminal of a diode-connected MOS transistor forming the output transconductor 2 and the output terminal of the in-phase feedback circuit 3 instead of a differential output terminal. Thus, the phase compensation of an in-phase feedback loop is realized without the phase compensation capacitances C<SB>1</SB>and C<SB>2</SB>serving as differential output loads, and without decreasing a band of the differential amplification circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a differential amplifier circuit, and more particularly to an open-loop differential amplifier circuit using a transconductor.

  Conventionally, an amplifier circuit is used in various parts of a circuit that performs analog signal processing. In particular, a differential amplifier circuit is used from the viewpoint of external noise resistance. The main characteristics required for the amplifier circuit are a bandwidth, a distortion characteristic, a noise characteristic, and the like. When used as a variable gain amplifier (VGA), a gain variable width is also a required characteristic.

  As a configuration of the amplifier circuit, a so-called closed loop configuration in which an operational amplifier is used to set a gain according to the feedback amount of the operational amplifier input and output, and a transconductor is used to perform voltage-current conversion on the input side, and further on the output side. There are roughly two types of so-called open loop configurations in which current-voltage conversion is performed and gain setting is performed according to input / output conversion ratios.

  The closed loop method using an operational amplifier generally has a high gain setting accuracy because the gain (gain) is determined by the ratio of external passive elements such as resistance elements, and the linearity of the variable gain amplifier is determined by the linearity of the passive elements. Also, the distortion characteristics are good. However, because it is used in a feedback configuration, it is necessary to provide loop stability to the amplifier circuit itself, and the unity gain frequency of the operational amplifier is reduced by phase compensation, and the bandwidth is determined in conjunction with this. Not suitable for. Also, the circuit scale tends to be large. Further, in order to continuously change the set gain, for example, it is necessary to continuously change the external resistance value. However, in general, this is difficult, and this is not suitable for use as a variable gain amplifier.

  On the other hand, in the open loop method using a transconductor, the linearity of the transconductor itself greatly affects the linearity of the amplifier circuit. However, since there is no feedback loop in the differential circuit itself, it is easy to realize a wide band. In addition, since the transconductance value can be easily continuously varied by a bias current, it is optimal as a variable gain amplifier when configuring an automatic gain adjustment amplifier.

  For the above reasons, an open-loop amplifier circuit using a transconductor has been used particularly for wideband applications (see, for example, Patent Document 1).

FIG. 8 shows a schematic configuration diagram of an example of a conventional amplifier circuit. As shown, an input transconductor 101, an output transconductor 102, current sources Is ₁₀ and Is _{20 of} each transconductor, an in-phase feedback circuit (hereinafter referred to as “CMFB circuit”) 103, a phase compensation capacitor Cc0, It comprises current sources Isp0 and Isn0 for biasing the input transconductor 101 and the output transconductor 102.

First, the input transconductor 101 is composed of a differential pair transistor composed of MOS transistors, and differential pair input signals Vip0 and Vin0 are inputted to the respective gate terminals, and between the common source terminal side of the differential pair transistor and the ground. Is provided with a current source Is ₁₀ . The drain terminal of the transistor to which the input signal Vip0 is input is connected to the drain terminal side of one of the differential pair transistors that constitute the output transconductor 102, and the drain of the transistor to which the input signal Vin0 is input. The terminal is connected to the drain terminal side of the other transistor of the differential pair transistor.

The differential pair transistors of the output transconductor 102 are respectively connected to the load current sources Isn0 and Isp0 on the drain terminal side. The current sources Isn0 and Isp0 are each connected to a power source to which the voltage Vcc is supplied. Each transistor of the differential pair transistor has a drain terminal and a gate terminal connected to each other, and a current source Is ₂₀ is provided between the common source terminal side of the differential pair transistor and the ground.

Furthermore, each drain terminal of the differential pair transistor constituting the output transconductor 102 is connected to an input terminal of the CMFB circuit 103. In addition, one end of capacitive elements C ₁₀ and C ₂₀ for phase compensation, which will be described later, is connected to each drain terminal of the differential pair transistor of the output transconductor 102, and the capacitive elements C ₁₀ and C ₂₀ are connected to each other. The other end is connected to the output terminal of the CMFB 103.

  The CMFB 103 sends a control signal corresponding to the difference between the common-mode potential of the output voltages Von and Vop input from the output transconductor 102 and a reference potential (not shown in FIG. 8) from its output terminal to the current sources Isn0 and Isp0. To control the current value biased to the input / output transconductors 101 and 102.

  Next, the operation of the conventional amplifier circuit shown in FIG. 8 will be described. First, the differential input signals Vip0 and Vin0 are applied between the gate terminals of the differential pair transistors constituting the input transconductor 101. Here, there are various examples of specific implementation methods of the transconductor, but the essence is that a differential output current proportional to the differential input voltage can be obtained. In FIG. 8, the differential output current is obtained as a drain current, and is subjected to current-voltage conversion again by the output transconductor 102.

  The output transconductor 102 has the same configuration as the input transconductor 101. As shown in FIG. 8, the differential pair transistors are diode-connected, so that the differential input / output is short-circuited, and the equivalent resistance [1 / Gm2] (gm2; output transconductance), so that the drain current change generated in the input transconductor 101 becomes the drain current change in the output transconductor 102, and as a result, the output differential pair Therefore, a differential output voltage is generated between the gate terminals of the transistors, so that the voltage gain Av is expressed as Av = gm1 / gm2 where the input transconductance is gm1.

  Here, since the common-mode output of the amplifier circuit in the example of FIG. 8 is high impedance as it is, it is necessary to set the desired common-mode output potential by the CMFB 103. The function of the CMFB 103 is to monitor the common-mode output potential, negatively feed back the difference from the reference potential, and set the common-mode output potential to the reference potential. As shown in FIG. , 102 is fed back to the constant current sources Isn0 and Isp0 that bias the current 102.

FIG. 9 shows a specific circuit configuration example of the conventional amplifier circuit shown in FIG. 9, in comparison with FIG. 8, n-channel MOS transistors N101 to N104 constitute the input transconductor 101, and n-channel MOS transistors N107 to N110 constitute the output transconductor 102. Further, n-channel MOS transistors N105, N106, N111, N112, p-channel MOS transistor P101~P104 each constitute a constant current source _{Is 1 0, Is 2 0,} Isn0, Isp0, p -channel MOS transistor P105～P108, The n channel MOS transistors N113 to N115 constitute the CMFB circuit 103.

Input the source terminal of the n-channel MOS transistors N101 and N102 of the differential pair constituting the transconductor 101 is connected to ground via a respective n-channel MOS transistors N105 and N106 constitute a current source Is ₁ 0. The drain terminal of the transistor N101 is connected to the drain terminal of the p-channel MOS transistor P101 constituting the current source Isn0, and the drain terminal of the transistor N102 is also the drain of the p-channel MOS transistor P102 also constituting the current source Isp0. Connected to the terminal.

  Further, N-channel MOS transistors N103 and N104 for adjusting the transconductance value are connected between the source terminals of the transistors N101 and N102. The differential pair input signals Vin0 and Vip0 are input to the gate terminals of the transistors N101 and N102, respectively.

Further, the source terminal of the n-channel MOS transistors N107 and N108 of the differential pair constituting the output transconductor 102 is connected to ground via a respective n-channel MOS transistors N111 and N112 constitute a current source Is ₂ 0 . The drain terminal of the transistor N107 is connected to the drain terminal of the p-channel MOS transistor P103 constituting the current source Isn0, and the drain terminal of the transistor N108 is the drain of the p-channel MOS transistor P104 also constituting the current source Isp0. Connected to the terminal. The drain terminals and gate terminals of the transistors N107 and N108 are diode-connected, respectively. Further, n-channel MOS transistors N109 and N110 for adjusting the transconductance value are connected between the source terminals of the transistors N107 and N108.

  The output signals Von0 and Vop0 are taken out from the output node of the output transconductor 102, that is, the drain terminals of the transistors N107 and N108, respectively.

A voltage Vbc0 is applied to each gate terminal of the transistors N105, N106, N111, and N112.

  Transistors P101 and P103 constituting the bias current source Isn0 of the input and output transconductors 101 and 102 are connected in series, and transistors P102 and P104 also constituting the current source Isp0 are connected in series. The source terminals of the transistors P101 and P102 are connected in common and coupled to a power supply that supplies the voltage Vcc.

One end of the resistance element _{R 1} 0 to obtain the drain terminal and the common mode output voltage of the transistor N107 is connected, one end of the same resistive element _{R 2} 0 and the drain terminal of the transistor N108 is connected, the resistance element _{R 1} 0 and _{R 2} Connect the other end of 0. Then, the midpoint of connection between the resistance elements R ₁ 0 and R ₂ 0 is connected to the gate terminal of the n-channel MOS transistor N113 which is an input node of the CMFB circuit 103.

  In the CMFB circuit 103, the source terminal of the n-channel MOS transistor N114 forming a differential pair with the transistor N113 and the source terminal of the transistor N113 are connected in common and connected to the ground via the n-channel MOS transistor N115 to which the voltage Vbn0 is applied. The

  The drain nodes of the differential pair transistors N113 and N114 are connected to a current mirror circuit composed of p-channel MOS transistors P105, P106, P107, and P108. That is, the drain terminal of the transistor N113 is commonly connected to the drain terminal of the transistor P107, and is connected to the power supply via the transistor P105 connected in series with the transistor P107. Similarly, the drain terminal of the transistor N114 is commonly connected to the drain terminal of the transistor P108, and is connected to the power supply via the transistor P106 connected in series with the transistor P108. The drain terminal of the transistor P107 and the gate terminals of the transistors P105 and P106 are connected.

A voltage Vbp0 is applied to the gate terminals of the transistors P103 and P104 and the transistors P107 and P108. A voltage source is connected to the gate terminal of the transistor N114, the reference potential V _{CM 0} which is compared with the common mode output voltage.

  The output node of the differential pair transistor, that is, the drain terminal of the transistor N114 is connected to the gate terminals of the transistors P101 and P102.

As the phase compensation circuit of the CMFB circuit 103, the drain terminal of the transistor N114 and one end of each of the capacitive elements C ₁₀ and C ₂ 0 are connected, and the other end of the capacitive element C ₁₀ is the transistor of the output transconductor 102. The other end of the capacitive element C ₂₀ is connected to the drain terminal of the transistor N108 of the output transconductor 102 to the drain terminal of N107.

In FIG. 9, the CMFB circuit 103 first detects the common-mode output potential of the differential amplifier circuit. This is obtained by the midpoint potential of the resistors R ₁ 0 and R ₂ 0, and the comparison with the reference potential V _CM 0 is performed by the differential pair transistors N113 and N114. The comparison result is fed back to the gate terminals of P101 and P102 which are current sources of the input / output transconductor.

There are a plurality of methods for realizing the CMFB circuit 103 as well as the configuration of the input and output transconductors. For example, instead of obtaining the common-mode potential with the resistance elements R ₁ 0 and R ₂ 0, this corresponds to the transistor N113. The common-mode potential detection transistors may be arranged in parallel, and the positive-phase and negative-phase output terminals may be independently connected to the gate terminal of the common-mode potential detection transistor N113. It is essential to compare with the differential amplifier circuit a reference phase voltage V _{CM 0} and the common mode output potential anyway.

  Further, according to this comparison result, that is, depending on whether the common-mode output potential is higher or lower than the desired reference potential, a feedback common-mode current is caused to flow to the output node, which normally causes a bias current to flow to the transconductor. This is done by a load transistor. Therefore, although feedback is applied to the p-channel side current source in the example of FIG. 9, it is also possible to feed back to the n-channel side, that is, the transistors N105, N106, N111, and N112.

Here, the phase compensation of the CMFB loop will be described. FIG. 10 shows a small signal equivalent circuit for the CMFB loop. In FIG. 10, R ₀ is the common-mode output resistance of the output transconductor 102, and Co is the common-mode component of the load capacitance of the output transconductor 102 and the parasitic capacitance. Further, _{g s} is the transconductance of the output transconductance of the transistor N113 for detecting the phase component of the output voltage of the transconductor 102, _{g f} transistors P101 to form a current source load of the transistor N107 and N108 and P102, R _f output output resistance of the differential circuit for detecting the phase component of the output voltage of the transconductor 102, the C _f is a parasitic capacitance associated with the output node of the input capacitor and the CMFB circuit 103 of the gate terminal of the transistor P101 and P102.

The common-mode output voltage V _O is converted into current by the transistor N113, that is, transconductance g _s , drives the loads R _f and C _f at the output node of the CMFB circuit 103, and transistors P101 and P102, which are bias current sources of the output transconductor 102, That is, the transconductance g _f drives R _o and C _o of the common-mode output node, and negative feedback is applied to the common-mode output voltage V _o .

As can be understood from FIGS. 9 and 10, since the CMFB loop has a two-pole characteristic with two high impedance nodes, a pole-sprit by Miller compensation is required to maintain loop stability. Is generally done. This is not necessarily a precedent, but for example, Paul R in the old days. Gray and Robert G. Meyer, “Analysis and Design of Analog Integrated Circuits,” John Wiley & Sons, 1977.
JP 2002-314374 A

  FIG. 11 shows a small signal equivalent circuit in which the CMFB loop of FIG. 10 is subjected to mirror compensation. However, as can be seen from FIG. 9, the mirror compensation capacitor Cc0 indispensable for the phase compensation of the CMFB loop is simultaneously a differential load capacitor connected to the output node of the differential amplifier circuit. For this reason, the bandwidth of the differential amplifier circuit is limited by the phase compensation of the CMFB loop.

  Similarly, in the case of the device described in Patent Document 1, the capacitive element for phase compensation connected to the output node of the differential amplifier circuit is a differential load capacitance. In the device described in Patent Document 1, the source terminal of the differential pair transistor is directly grounded, and the common-mode output potential is high.

  From the above, there has been a demand for CMFB phase compensation that can stably set the common-mode output potential to a desired set potential without limiting the signal band of the differential amplifier circuit.

  In view of such a point, the present invention provides a differential amplifier circuit that can form a CMFB loop subjected to phase compensation so that the in-phase output potential can be stably set to a desired set potential, and can widen the bandwidth. The purpose is to provide.

  In order to solve the above problems and achieve the object, the first means of the present invention includes a first transistor in which a first output terminal, a gate terminal and a drain terminal are connected to each other, a second output terminal and a gate terminal. And a control signal corresponding to the comparison result of the reference signal and the in-phase component of the output signal obtained from the output terminals of the first and second transistors and the transconductor composed of the second transistor whose drain terminals are connected to each other The common-mode feedback circuit, a current source that supplies a current according to the control signal of the common-mode feedback circuit to the first and second transistors of the transconductance, and an output terminal of the common-mode feedback circuit and a source terminal of the first transistor. Between the connected first capacitive element, the output terminal of the common-mode feedback circuit, and the source terminal of the second transistor And having a second capacitance element that has been continued.

  The second means of the present invention is a first transistor in which the first output terminal, the gate terminal and the drain terminal are connected to each other, and the second output terminal, the gate terminal and the drain terminal are connected to each other. A common mode feedback circuit for outputting a control signal corresponding to a comparison result of a reference signal and a common signal of an output signal obtained from the output terminals of the first and second transistors, a transconductor composed of transistors, and the common mode feedback circuit; Common-mode components of the output signal connected to the current source for supplying the current corresponding to the control signal to the first and second transistors of the transconductance, the output terminal of the common-mode feedback circuit, and the first and second output terminals, respectively. And a capacitive element connected to the middle point of the first and second resistance elements.

  According to the first and second means of the present invention, one end of the capacitive element provided for phase compensation is connected to the output terminal of the common-mode feedback circuit, and the other end is connected to the source terminal side of the transconductor or the output. Since it is connected to the middle point of each resistive element that extracts the common-mode component of the signal, the capacitive element does not become a direct load capacitance, and stable common-mode feedback without greatly limiting the signal bandwidth of the differential amplifier circuit A loop can be realized and the common-mode output potential can be set to a desired potential.

  According to the present invention, a CMFB phase compensation method capable of stably setting the common-mode output potential to a desired set potential without limiting the signal band of the differential amplifier circuit is enabled. There is an effect that the bandwidth of the differential amplifier circuit can be increased without sacrificing any other performance such as distortion.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a diagram showing a schematic configuration of an example of an embodiment of the present invention, and shows a concept of this example. The example shown in FIG. 1 includes an input transconductor 1, an output transconductor 2, current sources Is ₁ and Is _{2 of} each transconductor, an in-phase feedback circuit (hereinafter referred to as a “CMFB circuit”) 3, and a phase compensation capacitor Cc1. The input transconductor 1 and the output transconductor 2 are constituted by current sources Isp and Isn for biasing.

First, the input transconductor 1 is composed of a differential pair transistor composed of MOS transistors, the differential pair input signals Vip and Vin are inputted to the respective gate terminals, and a current source is connected between the source terminal side of the differential pair transistor and the ground. Is ₁ is provided. The output terminal of the transistor to which the input signal Vip is input is connected to the drain terminal side of one of the differential pair transistors constituting the output transconductor 2, and the output terminal of the transistor to which the input signal Vin is input. Is connected to the drain terminal side of the other transistor of the differential pair transistor.

The differential pair transistors of the output transconductor 2 have drain terminal sides connected to load current sources Isn and Isp, respectively. The current sources Isn and Isp are each connected to a power source to which a voltage Vcc is supplied. Further, while connecting the drain terminal and the gate terminal of each transistor of the differential pair transistors, providing the current source Is ₂ between the source terminal side and the ground of the differential pair transistors.

Further, each drain terminal of the differential pair transistor constituting the output transconductor 2 is connected to an input terminal of the CMFB circuit 3. Further, phase compensation capacitive elements C ₁ and C ₂ are connected between the output terminal of the CMFB circuit 3 and the source of the differential pair transistor, respectively.

  The CMFB circuit 3 sends a control signal corresponding to the difference between the common-mode potential of the output voltages Von and Vop input from the output transconductor 2 and a reference potential (not shown in FIG. 1) from its output terminal to the current source Isn. , Isp to control the current value biased to the input / output transconductors 1 and 2.

  Next, the operation of the differential amplifier circuit of the present embodiment shown in FIG. 1 will be described. First, the differential input signals Vip and Vin are applied between the gate terminals of the differential pair transistors constituting the input transconductor 1. Here, there are various examples of specific implementation methods of the transconductor, but the essence is that a differential output current proportional to the differential input voltage can be obtained. In FIG. 1, the differential output current is obtained as a drain current, and is subjected to current-voltage conversion again by the output transconductor 2.

  The output transconductor 2 has the same configuration as the input transconductor 1 and, as shown in FIG. 1, the differential pair transistors are diode-connected, so that the differential input / output is short-circuited, and the equivalent resistance [1 / Gm2] (gm2; output transconductance), so that the drain current change generated in the input transconductor 1 becomes the drain current change in the output transconductor 2, and as a result, the output differential pair Therefore, a differential output voltage is generated between the gate terminals of the transistors, so that the voltage gain Av is expressed as Av = gm1 / gm2 where the input transconductance is gm1.

  Here, since the common-mode output of the differential amplifier circuit in the example of FIG. 1 is high impedance as it is, it is necessary to set the desired common-mode output potential by the CMFB circuit 3. The function of the CMFB circuit 3 is to monitor the common-mode output potential, perform negative feedback (negative feedback) on the difference from the set potential, and set the common-mode output potential to the set potential. As shown in FIG. A control signal is fed back to the constant current sources Isn and Isp for biasing the conductors 1 and 2.

FIG. 2 shows a specific circuit configuration example of the differential amplifier circuit shown in FIG. In FIG. 2, n-channel MOS transistors N1 to N4 constitute the input transconductor 1 and n-channel MOS transistors N7 to N10 constitute the output transconductor 2 in comparison with FIG. The n-channel MOS transistors N5, N6, N11, N12, and the p-channel MOS transistors P1 to P4 constitute constant current sources Is ₁ , Is ₂ , Isn, and Isp, respectively, and p-channel MOS transistors P5 to P8, n-channel The MOS transistors N13 to N15 constitute the CMFB circuit 3.

Each source terminal of the n-channel MOS transistors N1 and N2 of the differential pair constituting the input transconductor 1, connected to ground via a respective n-channel MOS transistors N5 and N6 constituting a current source Is _1. The drain terminal of the transistor N1 is connected to the drain terminal of the p-channel MOS transistor P1 constituting the current source Isn, and the drain terminal of the transistor N2 is connected to the drain terminal of the p-channel MOS transistor P2 also constituting the current source Isp. Connect to.

  Further, N-channel MOS transistors N3 and N4 for adjusting the transconductance value are connected between the source terminals of the transistors N1 and N2. Since the transistors N3 and N4 operate in the triode region, these are hereinafter referred to as a triode region transistor. One input voltage Vip of the differential input voltage is inputted by connecting the gate terminal of the transistor N3 to the gate terminal of the transistor N1. Further, the other input voltage Vin of the differential input voltage is input by connecting the gate terminal of the transistor N4 to the gate terminal of the transistor N2. By using the triode region transistors N3 and N4, the linearity of the transconductor is improved, and when the gate voltage of one of the triode region transistors connected in parallel at the time of large amplitude input is increased, the on-resistance is increased. Decreases, and the decrease in transconductance can be offset.

Moreover, to connect the respective source terminals of n-channel MOS transistors N7 and N8 of the differential pair constituting the output transconductor 2, to ground via a respective n-channel MOS transistors N11 and N12 constitute a current source Is _2. The drain terminal of the transistor N7 is connected to the drain terminal of the p-channel MOS transistor P3 constituting the current source Isn, and the drain terminal of the transistor N8 is connected to the drain terminal of the p-channel MOS transistor P4 also constituting the current source Isp. Connect to. The drain terminals and gate terminals of the transistors N7 and N8 are diode-connected, respectively.

  Further, similarly to the input transconductor 1, the triode region transistors of n-channel MOS transistors N9 and N10 for adjusting the transconductance value are connected between the source terminals of the transistors N7 and N8.

  Then, output signals Von and Von are respectively taken out from the output node of the output transconductor 2, that is, the drain terminals of the transistors N7 and N8.

  A voltage Vbc is applied to each gate terminal of the transistors N5, N6, N11, and N12.

  The transistors P1 and P3 constituting the bias current source Isn of the input and output transconductors 1 and 2 are connected in series, and the transistors P2 and P4 also constituting the current source Isp are connected in series. The source terminals of the transistors P1 and P2 are connected in common and coupled to a power source that supplies the voltage Vcc.

Also, connect one end of the resistance element R ₁ to obtain the drain terminal and the common mode output voltage of the transistor N7, and connect the same end of the resistance element R ₂ and the drain terminal of the transistor N8, other resistive elements R ₁ and R ₂ Connect the ends. Then, the midpoint of connection between the resistance elements R ₁ and R ₂ is connected to the gate terminal of the n-channel MOS transistor N 13 that is the input node of the CMFB circuit 3.

  In the CMFB circuit 3, the source terminal of the n-channel MOS transistor N14 that forms a differential pair with the transistor N13 and the source terminal of the transistor N13 are connected in common and connected to the ground via the n-channel MOS transistor N15 to which the voltage Vbn is applied. To do.

  The drain nodes of the differential pair transistors N13 and N14 are connected to a current mirror circuit composed of p-channel MOS transistors P5, P6, P7 and P8. That is, the drain terminal of the transistor N13 is commonly connected to the drain terminal of the transistor P7, and is connected to a power source to which the voltage Vcc is supplied via the transistor P5 connected in series with the transistor P7. Similarly, the drain terminal of the transistor N14 is commonly connected to the drain terminal of the transistor P8, and is connected to a power source to which the power source Vcc is supplied via the transistor P6 connected in series with the transistor P8. Further, the drain terminal of the transistor P7 and the gate terminals of the transistors P5 and P6 are connected.

A voltage Vbp is applied to the gate terminals of the transistors P3 and P4 and the transistors P7 and P8. A voltage source is connected to the gate terminal of the transistor N14, the reference potential V _CM to be compared with the common mode output voltage.

  The output node of the differential pair transistor, that is, the drain terminal of the transistor N14 is connected to the gate terminals of the transistors P1 and P2 of the bias current source of the input and output transconductors 1 and 2.

As a CMFB loop phase compensation circuit, the capacitive element C ₁ is connected between the drain terminal of the transistor N 14 that is the output node of the CMFB circuit 3 and the source terminal of the transistor N 7 of the output transconductor 2. Similarly, to connect the capacitor C ₂ and the drain terminal of the transistor N14, between the source terminal of the transistor N8.

In FIG. 2 described above, the CMFB circuit 3 first detects the common-mode output potential of the differential amplifier circuit. This is obtained by the midpoint potential of the resistive element _{R 1} and _{R 2,} compared with the reference potential _{V CM} is carried out in the differential pair transistors N13, N14. Then, according to the comparison result, that is, depending on whether the common-mode output potential is higher or lower than the desired reference potential, a feedback common-mode current is passed through the output node. Note that this is done by a load transistor that passes a bias current through the transconductance.

  The difference between the example of FIG. 2 and the conventional example is that one end of the Miller compensation capacitor is connected to the output node of the CMFB circuit 3 and the other end is connected to the source terminal of the output transconductor 2. The phase compensation capacitor is not connected to the output node of the amplifier circuit. For this reason, the mirror compensation capacitance does not become a direct differential load capacitance, and a stable CMFB loop can be realized and the common-mode output potential can be set to a desired potential without greatly limiting the bandwidth of the amplifier circuit. Become.

  As described above, this is usually performed for a load transistor in which a bias current is passed through the transconductor. Therefore, in the example of FIG. 2, feedback is applied to the transistors P1 and P2 of the p-channel side current source, but feedback may be made to the n-channel side, that is, the transistors N5, N6, N11, and N12.

  In the specific circuit example of FIG. 2, the bias currents of the input transconductor 1 and the output transconductor 2 are determined by the transistors N5, N6 and N11, N12, respectively, and are not varied independently. Therefore, the respective gate terminals are independently biased, and as a result, the bias currents of the input transconductor 1 and the output transconductor 2 are independently variable, so that the amplification factor can be varied, that is, used as a variable gain amplifier (VGA). Of course it is also possible. Of course, the present invention can also be applied to this case.

  The transistors N3, N4, N9, and N10 that operate in the triode region are installed for the purpose of improving the linearity of each transconductor. And the source terminals of the input differential pair can be short-circuited to each other.

Next, a modification of the embodiment of the present invention shown in FIG. 2 will be described. FIG. 3 is a circuit diagram showing a modification of the embodiment of the present invention. In addition to the configuration of the input and output transconductors 1 and 2 in this example, a plurality of methods are conceivable regarding the method of realizing the CMFB circuit. For example, as shown in FIG. 2, instead of obtaining the common-mode potential by the resistance elements R ₁ and R ₂ , the common-mode potential detection transistors corresponding to the transistor N13 are paralleled, and the positive-phase and reverse-phase output terminals are independent from each other. May be connected to the gate terminal of the common-mode potential detection transistor. The reference phase voltage V _CM and the common mode output potential anyway only has to be compared in a differential amplifier circuit.

  Specifically, in FIG. 3, a CMFB circuit 13 having a configuration in which transistors N13n and N13p are arranged in parallel is provided instead of the common-mode potential detection transistor N13 of the CMFB circuit 3 of FIG. The drain terminal of the transistor N8 of the output transconductor 2 is connected to the gate terminal of the transistor N13p, and the drain terminal of the transistor N7 is connected to the gate terminal of the transistor N13n.

  In the case described above, there is an advantage that the gain of the differential amplifier circuit does not decrease because there is no load resistance.

  Furthermore, an example of another embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a schematic configuration diagram showing the concept of another embodiment of the present invention. FIG. 5 is a diagram showing a circuit configuration of another embodiment of the present invention.

  In the example of FIGS. 2 and 3 described above, a phase compensation capacitor can be seen in parallel with the triode operation transistors N9 and N10 for linearization of the differential signal, which limits the band as the differential amplifier circuit. . This example of another embodiment of the present invention eliminates this problem and further extends the bandwidth.

  The difference between the conventional example and the examples of FIGS. 2 and 3 is that, as shown in FIG. 4, one end of the mirror compensation capacitor Cc2 is connected to the output node of the CMFB circuit 3, and the other end is the common-mode output potential of the differential amplifier circuit. The phase compensation capacitor is not connected to the output node of the differential amplifier circuit or the linearization circuit (here, transistors N9 and N10).

Specifically, as shown in FIG. 5, with connecting one end of the capacitor C ₃ and the output node of the CMFB circuit 3, the resistance element R ₁ for taking out the common-mode output potential of the differential amplifier circuit and other end And R ₂ are connected to the midpoint of connection. Similarly, one end of the capacitive element C ₄ is connected to the output node of the CMFB circuit 3, and the other end is connected to the connection middle point of the resistance elements R ₁ and R ₂ for extracting the common-mode output potential of the differential amplifier circuit. .

  For this reason, the mirror compensation capacitance does not directly become a differential load capacitance, and no differential signal component is added to the phase compensation capacitance of the CMFB loop. Therefore, it is possible to realize a stable CMFB loop and set the common-mode output potential to a desired potential without greatly limiting the bandwidth of the amplifier circuit. The other effects are the same as those of the embodiment described with reference to FIGS.

  FIG. 6 shows the open loop gain and phase characteristics of the CMFB loop in the conventional and each embodiment of the present invention, and FIG. 7 shows the gain characteristics of the differential amplifier circuit in the conventional and each embodiment of the present invention. . 6 and 7, A1 represents the characteristic curve of the example of the embodiment shown in FIG. 1, A2 represents the characteristic curve of the example of the other embodiment according to FIG. 4, and B represents the characteristic curve of the conventional example. .

  In FIG. 6, when looking at the phase at a frequency where the gain is 0 dB, in the above-described embodiments, the phase margin is 80 degrees or more because it is above the -100 degree line, and is sufficiently stable (in general, It can be read that it is considered to be stable at about 60 degrees or more. That is, in the above-described embodiment, the phase compensation method is changed from the conventional method, so that the original phase compensation purpose is not adversely affected and a sufficient phase margin is secured and a stable CMFB loop is obtained. Is configured. Note that the gain / phase characteristic curve according to the example of the other embodiment is shifted to the low frequency side, but this indicates only how much the (unnecessary) in-phase component can be suppressed up to, This is not a problem because the bandwidth of the CMFB loop is slightly lowered, not the bandwidth of the differential amplifier circuit.

  In FIG. 7, the bandwidth of the conventional example is 230 MHz, the bandwidth of the example of one embodiment (see FIGS. 1 to 3) is 445 MHz, and the example of another embodiment (see FIGS. 4 and 5). The bandwidth is 775 MHz. Accordingly, the bandwidth of the differential amplifier circuit is greatly increased in the example of one embodiment from the conventional example and further in the example of the other embodiment, and it is possible to surely achieve the wide band which is the object of the present invention. It can be said that.

  As can be seen from the above, according to the above-described differential amplifier circuit of the present invention, the bandwidth of the amplifier circuit can be greatly extended while maintaining the stability of the CMFB loop.

  According to the present invention, a CMFB phase compensation method capable of stably setting the common-mode output potential to a desired setting potential without limiting the signal band of the differential amplifier circuit is enabled, and as a result, consumption The bandwidth of the differential amplifier circuit can be increased without sacrificing any other performance such as power and distortion.

  Note that even if the n-channel and the p-channel of each transistor in the example of the above-described embodiment are interchanged, a circuit having the same function can be configured, and the same operation effect can be obtained.

  Further, the present invention is not limited to the above-described embodiments, and various other configurations can be taken without departing from the gist of the present invention.

It is a figure which shows schematic structure of the example of one embodiment of this invention. It is a circuit diagram which shows the example of one embodiment of this invention. It is a circuit diagram which shows the modification of one embodiment of this invention. It is a figure which shows schematic structure of the example of other embodiment of this invention. It is a circuit diagram which shows the example of other embodiment of this invention. It is a diagram which shows the open loop gain and phase characteristic of the CMFB loop in the conventional and each embodiment of the present invention. It is a diagram which shows the gain characteristic of the differential amplifier circuit in each prior art and each embodiment of this invention. It is a figure which shows schematic structure of an example of the conventional amplifier circuit. It is a figure which shows an example of the conventional amplifier circuit. It is a CMFB loop small signal equivalent circuit diagram. It is a small signal equivalent circuit diagram which performed mirror compensation.

Explanation of symbols

1 ... Input transconductor, 2 ... output transconductors, 3 ... phase feedback _{circuit, C 1, C 2, C} 3, C 4 ... ( phase compensation) capacitive element, Isp, Isn ... current source

Claims (8)

A transconductor including a first transistor in which a first output terminal, a gate terminal, and a drain terminal are connected to each other; a second transistor in which a second output terminal, a gate terminal, and a drain terminal are connected to each other;
An in-phase feedback circuit that outputs a control signal according to a comparison result between the in-phase component of the output signal obtained from the output terminals of the first and second transistors and a reference signal;
A current source for supplying a current corresponding to the control signal of the common-mode feedback circuit to the first and second transistors of the transconductance;
A first capacitor connected between an output terminal of the common-mode feedback circuit and a source terminal of the first transistor;
A differential amplifier circuit comprising: a second capacitor connected between an output terminal of the common-mode feedback circuit and a source terminal of the second transistor. The current source is provided on the drain side of the transconductor;
One end of the first and second capacitive elements and an output terminal from which a control signal of the common-mode feedback circuit is output are connected to a gate terminal of a transistor constituting the current source provided on the drain side of the transconductor. The differential amplifier circuit according to claim 1, wherein: The current source is provided on the source side of the transconductor;
One end of the first and second capacitive elements and an output terminal from which a control signal of the common-mode feedback circuit is output are connected to a gate terminal of a transistor constituting the current source provided on the source side of the transconductor. The differential amplifier circuit according to claim 1, wherein: The common-mode output voltage obtained at the middle point of the resistive element connected to each of the first output terminal and the second output terminal of the transconductor is input to one of the differential pair transistors constituting the common-mode feedback circuit, and the difference The differential amplifier circuit according to claim 1, wherein a desired reference voltage is input to the other of the dynamic pair transistors, and an output of the differential pair transistor is input to the current source of the transconductor as the control signal. One input part of the differential pair transistor is composed of two transistors connected in parallel,
Each of the first and second output terminals is connected to a gate terminal of a parallel transistor of one input section of the differential pair transistor, and the other input of the differential pair transistor is used as a desired reference voltage source. 5. The differential amplifier circuit according to claim 4, wherein the differential amplifier circuit is connected, and an output of the differential pair transistor is connected to a gate terminal of a transistor constituting a current source of the transconductor. A transconductor including a first transistor in which a first output terminal, a gate terminal, and a drain terminal are connected to each other; a second transistor in which a second output terminal, a gate terminal, and a drain terminal are connected to each other;
An in-phase feedback circuit that outputs a control signal according to a comparison result between the in-phase component of the output signal obtained from the output terminals of the first and second transistors and a reference signal;
A current source for supplying a current corresponding to the control signal of the common-mode feedback circuit to the first and second transistors of the transconductance;
An output terminal of the common-mode feedback circuit; and a capacitive element connected to a midpoint of the first and second resistance elements that extract the common-mode component of the output signal connected to the first and second output terminals, respectively. A differential amplifier circuit comprising: The current source is provided on the drain side of the transconductor;
One end of the capacitive element and an output terminal from which a control signal of the common-mode feedback circuit is output are connected to a gate terminal of a transistor constituting the current source provided on the drain side of the transconductor. The differential amplifier circuit according to claim 6. The current source is provided on the source side of the transconductor;
One end of the capacitive element and an output terminal from which a control signal of the common-mode feedback circuit is output are connected to a gate terminal of a transistor constituting the current source provided on the source side of the transconductor. The differential amplifier circuit according to claim 6.

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