JP3442613B2 - Variable gain amplifier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain amplifier circuit which is the basis for analog signal processing in a MOS semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, with the increase in digital equipment and the progress of digital signal processing technology, C suitable for digital signal processing has been developed.
MOS integrated circuits are occupying most of the semiconductor market. However, it is easier to process video and audio in analog because the input and output are analog.
Even in the case of digital processing, analog circuits are required for A / D and D / A conversion, filter processing before and after the A / D conversion, and an oscillator for clock generation. Bipolar is suitable for analog circuits, and CMOS has been unsuitable except for some circuits such as analog switches and sample hold. However, the cost of the bipolar and BiCMOS processes is rather high, and there is a strong demand for the CMOS to be integrated into one chip by digital / analog mixed mounting.
The circuit development for analog signal processing is becoming popular.

There is a "variable gain amplifier" as an important function which is frequently used in analog signal processing and has a great influence on the total performance. In bipolar, there is a convenient combinational transistor circuit called "gain cell", and if a variable gain amplifier is constructed using this, a circuit having a gain proportional to the ratio of two bias currents can be easily realized. However, when making a variable gain amplifier in CMOS, in a circuit in which bipolar is simply replaced by CMOS or a modified circuit thereof,
Encounter a problem that always causes a large second-order distortion. For example, FIG. 11 was recently published (Japanese Patent Laid-Open No. 8-29).
Japanese Patent No. 8416) is a variable gain differential amplifier composed of CMOS. The problem of the conventional circuit will be described below by taking this as an example. This circuit consists of MOS transistors M1 and M
The main circuit is a differential circuit composed of 2 and a current source I1, and a differential circuit composed of MOS transistors M3 and M4 and a current source I2. All of these are of a type in which a pair transistor whose source is directly connected is biased by a current source. Therefore, consider a one-sided differential circuit composed of one-sided MOS transistors M1 and M2 and a current source I1. However, it is assumed that the inputs are fully differential signals, both transistors are operating in the saturation region (pinch-off region), and the short channel effect is not considered for simplicity. At this time, the characteristics of each MOS transistor can be expressed as I = (k / 2) (VGS-Vth) ² by using the values of k and Vth which are main parameters. Here, k is a constant represented by “μCoxW / L” where W is the gate width, L is the gate length, Cox is the gate capacitance, and μ is the carrier mobility of the channel. Using this, the descriptive expression of the operation of the MOS transistors M1 and M2 can be expressed as follows.

M1: I11 = (k / 2) (VGS1-Vth) ² (1) M2: I12 = (k / 2) (VGS2-Vth) ² (2) where (1)-(2 ), I11-I12 = (k / 2) (VGS1 + VGS2-2Vth) (VGS1-VGS2) = (k / 2) (VGS1 + VGS2-2Vth) Vin ... (3) However, VGS1 and VGS2 are the gate-source voltages of the MOS transistors M1 and M2, respectively, and Vin is the differential input voltage. Since the input signal is assumed to be a fully differential signal, the midpoint potential of the input signal is VB, and the input voltage supplied to the input terminal is VB + Vin / 2 and VB-Vin /
It can be expressed as 2. Here, the source potential VA of the differential pair is calculated. In this case, VGS1 = VB + Vin / 2-VA and VGS2 = VB-Vin / 2-VA, so that VB-VA-Vth = A (1) +
From (2),

[Equation 1] Becomes therefore,

[Equation 2] Becomes Substituting this into (3), the transconductance Gm1 of this differential pair [= (I11-I12) / Vin]
And ask

[Equation 3] Becomes Similarly, transconductance Gm2 [= (I21-I22) / Vin] is similarly calculated for the differential circuit on one side composed of MOS transistors M3, M4 and I2.

[Equation 4] Is asked. However, k of MOS transistors M3 and M4
The values of Vth and Vth are equal to those of the MOS transistors M1 and M2. As described above, the calculated two differential circuits connect outputs of opposite polarities to each other, so that the value of the total transconductance Gm is the difference between (5) and (6).

[Equation 5] It turns out that. As is clear from this equation, the transconductance Gm is the instantaneous amplitude value Vin of the input signal.
It will change dynamically according to. This means that distortion will occur in the output. Since the transconductance Gm includes the squared term of Vin, the distortion is mainly second-order. This cannot be canceled not only when a linear element such as a resistor is used as a load for the output, but also when a MOS transistor having a square characteristic is used as a load, and only a more complicated distortion waveform results. CMO
When the variable gain amplifier is made of S, it is unavoidable that a large amount of distortion is generated and the quality of the signal is deteriorated.

[0005]

As described above, a variable gain differential amplifier is conventionally used as an analog circuit in the C-type.
If it is attempted to realize it only by MOS, a large distortion is always generated, and it is unavoidable that the signal quality is remarkably deteriorated.

An object of the present invention is to provide a variable gain differential amplifier that does not generate any distortion in principle by an analog circuit using CMOS.

[0007]

In order to solve the above-mentioned problems, the first method of the present invention is to use a field effect transistor to provide an input differential signal between the gate terminals.
The source terminal of the first differential transistor pair were both connected to the reference potential, that of the first differential transistor pair
Detecting the average value of the drain current flowing to the drain terminal of Les, the drain of the each folded the average current
And average current supply means for supplying to the terminal, and an offset control means for controlling the DC voltage of the input signal, wherein each
The current drawn from the drain terminal of is the respective output current, and the ratio of the amplitude of the output current to the input signal amplitude is
A means for controlling by controlling the DC voltage is provided.

As a second method, a first and a second differential transistor pair, which are field effect transistors and have source terminals connected to a common reference potential point, are provided . The same input differential signal is applied between the gate terminals, and the drains having opposite polarities with respect to the inputs are output between the first and second differential transistor pairs.
Drain each of the in- currents so that they add to each other.
A signal amplifying means is constructed by connecting a down terminals are respectively detects the average value of the first and second of said pressurized <br/> calculated drains current of the differential transistor pair, folding the average current A pair of drain terminals connected to each other
On the average current supply means for supplying each consist offset control means for providing a respective input differential signal to have a controllable DC offset between the first and second differential transistor pair, wherein each The drain edge
The current drawn from the connection point of the child is set as each output current, and the ratio of the amplitude of the output current to the input signal amplitude is controlled by controlling the DC offset voltage.

As a third method, a first differential transistor pair composed of field effect transistors having source terminals connected to a first reference potential point and source terminals connected to a second reference potential point. A second differential transistor pair, wherein the same input differential signal is applied between the gate terminals of the respective differential transistor pairs, and the input differential signals are inverted between the first and second differential transistor pairs with respect to the inputs. To add the drain currents that are polar outputs to each other ,
Signal amplifying means configured by connecting drain terminals to each other ,
Said addition of said first and second differential transistor pair
The average value of the drain currents is detected, and the average currents are returned to the pair of connected drain terminals.
An average current supply means for supplying each, and the first reference voltage
Consists position point and offset control means for imparting a controllable DC offset voltage between the second reference potential point, taken out from the connection point of the respective drain terminals
It is characterized in that the ratio of the amplitude of the output current to the amplitude of the input signal is controlled by controlling the direct current offset voltage by using the generated current as each output current.

By adopting such a circuit form, the input signal is directly input as the gate-source voltage of each element of the CMOS differential pair, so that the MO signal is input.
It is converted into a pure square current by the square characteristic of S. The DC component of the squared current and the secondary component of the input signal are canceled by the average current subtraction circuit, and only the DC component × the input signal (first component) can be taken out as the output current. The transconductance Gm (output current divided by input voltage) of this circuit is proportional to only the DC voltage, and by changing this DC voltage, Gm can be changed to change the gain. Further, Gm does not depend on the instantaneous amplitude value Vin of the input signal at all. That is, since the Gm value does not dynamically change according to the input signal, the variable gain does not cause distortion.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a circuit configuration diagram for explaining a first embodiment of the present invention. This embodiment is basically composed of a pair of source-grounded differential transistors composed of MOS transistors M1 and M2. An input differential signal is supplied to the gate terminal of the differential transistor via the DC offset generating means Vc. This DC offset is controlled so that the same voltage is applied to the MOS transistors M1 and M2, and the same change amount is obtained. Furthermore, MOS transistors M1 and M2
Means for detecting the average current of the drain current of the MOS transistor M1 is supplied from the power source Vcc.
And pour into the drain terminal of M2. In this way, M
The drain terminals of the OS transistors M1 and M2 have a difference current Io between their respective drain currents and their average currents.
1 and Io2 are output. By controlling the DC offset voltage with such a circuit, the output differential current Io1
And control the ratio of Io2 to the input signal amplitude.

When compared with the conventional FIG. 11, the basic difference is that the source connection point of the differential transistor is biased by the current source in FIG. 11, whereas the source of the differential transistor is different in this embodiment. This is the point where the connection point is fixed at a constant potential (GND in FIG. 1). In the conventional circuit, N
As is clear from the fact that the expression (4) has a term including Vin2, the source connection point of the MOS differential pair was caused by the secondary ripple of the signal and caused distortion. On the other hand, in this embodiment, since this point is connected to the ground GND, the input signal voltage is directly applied between the gate and source of each element of the NMOS differential pair, so that distortion will occur due to the operation described later. Is to suppress.

To prove that the embodiment of FIG. 1 does not generate distortion, the transconductance Gm of the differential circuit of FIG. 1 is calculated. However, various conditions are the same as in the case of the conventional example of FIG. 11, the input is a fully differential signal, both transistors operate in the saturation region (pinch-off region), the short channel effect is not taken into consideration, and k of each MOS transistor is not considered.
And Vth are equal to each other, and k is a constant represented by “μCoxW / L” where W is a gate width, L is a gate length, Cox is a gate capacitance, and μ is a carrier mobility of a channel. Since the input signal is assumed to be a fully differential signal, the midpoint voltage of the input signal with reference to the ground GND is V
As B, the input voltage supplied to the input terminal is VGS1 = VB + Vc + Vin / 2 VGS2 = VB + Vc-Vin / 2. Therefore, the descriptive expression of the operation of the MOS transistors M1 and M2 in this case can be expressed as follows.

M1: I11 = (k / 2) (VGS1−Vth) ² = (k / 2) (VB + Vc−Vth + Vin / 2) ² (8) M2: I12 = (k / 2) (VGS2−Vth) ) ² = (k / 2) (VB + Vc-Vth-Vin / 2) ² (9) Since the average current detection outputs the current of (I11 + I12) / 2, the output currents Io1 and Io2 are Can be expressed as

Io1 = (I11 + I12) / 2-I11 = (I12-I11) / 2 = -k (VB + Vc-Vth) Vin (10) Io2 = (I11 + I12) / 2-I12 = (I11-I12) / 2 = k (VB + Vc-Vth) Vin ... (11) k is a constant that allows the shape of the MOS element to be (VB + V
c-Vth) is a controllable DC voltage, so the output current Io
1 and Io2 are directly proportional to the input amplitude Vin and have no distortion component. As described above, in the embodiment shown in FIG. 1, a single output as well as a differential output has a distortion-free output waveform, and a completely symmetrical and distortion-free output can be obtained. Transconductance Gm [= as a differential circuit of this circuit
When (Io2-Io1) / Vin] is obtained, Gm = 2k (VB + Vc-Vth) (12) It can be seen from the comparison between the equation (7) of the conventional circuit and this equation that the distortion can be completely removed. Even with a single output, there is no distortion, so the precondition that the input signal is a fully differential signal can be maintained in the next stage, and there is no distortion even if connected in multiple stages. Gm can be easily controlled by changing Vc.
If Vc is reduced to be equal to -VB + Vth, Gm
Can be = 0. In this way, the gain (transconductance) can be controlled from an infinitesimally small value, so that the control range is wide. However, in this case, since the input dynamic range is also small, it is not realistic to reduce Gm to near 0.

Further, unlike the method of biasing with a current source, since the sources of the differentially configured MOS transistors M1 and M2 are used by dropping them to the ground GND, a wide dynamic range can be secured on the drain side. Therefore, it is also suitable for lowering the voltage. Furthermore, since the source is connected to the ground GND, it has the advantage that it is not affected by the substrate effect even if it is made by a normal P substrate process, and it has high precision and
A low distortion analog circuit can be constructed.

FIG. 2 shows the average current detecting means 11 of FIG. 1 replaced with a concrete circuit example. The average current detecting means 11 is a MOS transistor M3 as shown in the figure.
And a current copy circuit for the MOS transistors M1 and M2, and a current mirror for adding the copy currents and halving the currents. Transistor M
Since 3 and M4 share the gate and source with the MOS transistors M1 and M2, respectively, the drain currents of the MOS transistors M3 and M4 are equal to the drain currents of the MOS transistors M1 and M2, respectively. By connecting the drain terminals of the MOS transistors M3 and M4 to the input of the current mirror, these drain currents are added, and by folding at a mirror ratio of 1/2, the average value of the drain current is output. By preparing a pair of these and sending them to the drain terminals of the MOS transistors M1 and M2, the current subtraction in the above equations (10) and (11) is executed, and only the first-order term of Vin is taken out. Is.

Next, a second embodiment of the present invention will be described with reference to FIG. In this embodiment, the MOS transistor M3 is provided in parallel with the first source-grounded differential pair composed of the MOS transistors M1 and M2 in FIG.
And a second source grounded differential pair made up of M4 and M4. First added to the second differential pair added
The same input signal as that of the first differential pair is applied, but at this time, the input to the first differential pair is supplied with a voltage difference of DC offset Vc. The DC offset is controlled so that the same voltage is applied to the MOS transistors M3 and M4 so that the same change amount is obtained. The drain terminal is the output of the MOS transistor M1 which has an opposite polarity to the input and the MO
Drain of S transistor M4, MOS transistor M
The drain of 2 and the drain of the MOS transistor M3 are connected to each other, and the added current of each is used as the output current. Further, the average current detecting means 11 for the drain addition currents of the MOS transistors M1 and M4 and the MOS transistors M2 and M3 is provided, and currents equal to this average current are added to the addition currents from the power supply Vcc. In this case, since the average value of the drain sum currents of the MOS transistors M1 and M4 and the MOS transistors M2 and M3 is equal, this current value is the same as the MOS transistor M4.
The total added current of the four drain currents 1 to M4 is halved. In this way, the difference currents Io1 and Io2 between the respective drain addition currents and the average currents of both drains are output to the output terminal. By controlling the DC offset voltage Vc with such a circuit, the output differential current Io
Control the ratio of 1 and Io2 to the input signal amplitude.

In this circuit as well as in the embodiment of FIG. 1, the source connection point of the differential transistor is at a constant potential (GN in FIG. 3).
Since it is fixed to D), the input signal voltage is directly applied between the gate and source of each element of the NMOS differential pair, and distortion can be suppressed by the action described later.

The transconductance Gm of the differential circuit shown in FIG. 3 will be calculated. However, it is assumed that various conditions are the same as in the case of FIG. Since the input signal is assumed to be a fully differential signal, the midpoint voltage of the input signal with reference to the ground GND is V
As B, the input voltage supplied to the input terminal is VGS1 = VB + Vin / 2 VGS2 = VB-Vin / 2. Therefore, in this case, the MOS transistors M1 ...
The descriptive expression of the operation of M4 can be expressed as follows. M1: I11 = (k / 2) (VGS1-Vth) ² = (k / 2) (VB-Vth + Vin / 2) ² ... (13) M2: I12 = (k / 2) (VGS2-Vth) ² = ( k / 2) (VB-Vth-Vin / 2) ² ... (14) M3: I21 = (k / 2) (VGS3-Vth) ² = (k / 2) (VB-Vc-Vth + Vin / 2) ² ... (15) M4: I22 = (k / 2) (VGS4-Vth) ² = (k / 2) (VB-Vc-Vth-Vin / 2) ² (16) Average current detection is (I11 + I12 + I21 + I22) / 2 Since a current is output, the output currents Io1 and Io2 can be expressed as follows.

Io1 = (I11 + I12 + I21 + I22) / 2- (I11 + I22) = {(I21-I22)-(I11-I12)} / 2 = (k / 2) {2 (VB-Vc-Vth) Vin-2 (VB -Vth) Vin} =-kVc Vin (17) Io2 = (I11 + I12 + I21 + I22) / 2- (I12 + I21) = {(I11-I12)-(I21-I22)} / 2 = (k / 2) {2 (VB −Vth) Vin−2 (VB−Vc−Vth) Vin} = kVcVin ... (18) k is a constant that allows the shape of the MOS element, and Vc is a DC control voltage.
It is directly proportional to in and has no distortion component. As described above, in the embodiment shown in FIG. 3, a single output as well as a differential output has a distortion-free output waveform, and a completely symmetrical and distortion-free output can be obtained. Transconductance Gm (= (Io2-Io1) /
When Vin) is calculated, Gm = 2 kVc (19) As is clear from the fact that this expression does not include the Vin term as in the conventional example, it is clear that the strain can be completely removed as in the first embodiment. The transconductance Gm can be easily controlled by changing Vc. If Vc is reduced to 0, Gm = 0 can be achieved. In this way, the gain (transconductance) can be controlled from an infinitesimally small value, so that the control range is wide. In this case, since Vc can be set independently of VB and the like, VB can be set to a required value to secure the input dynamic range.

In this embodiment, when the transconductance Gm is reduced as in FIG. 1, the input dynamic range does not become insufficient and good characteristics can be maintained. Also, Gm is k and V
Since it is given in a very simple form of only c and does not include element parameters other than k such as Vth, the variation sensitivity to variation in process parameters is low and a highly accurate variable gain circuit can be configured. The single output is also distortion-free, so that it is not distorted even if it is connected in multiple stages, is suitable for lowering the voltage, and is not affected by the substrate effect, as in the embodiment of FIG.

In the second embodiment, the average current detecting means 11
FIG. 4 shows a circuit example in which is replaced with a concrete circuit. The average current detecting means 11 is composed of MOS transistors M1 'and M2' as shown in FIG.
Current copy circuit, a current copy circuit of MOS transistors M3 and M4 consisting of MOS transistors M3 'and M4', and a current mirror which adds up all of these copy currents and folds them back in half. The MOS transistors M1 'to M4' are respectively MOS transistors M1 to M4.
Since the gate and source are common, the drain currents of the MOS transistors M1 'to M4' are equal to the drain currents of the MOS transistors M1 to M4, respectively. By connecting the drain terminals of the MOS transistors M1 to M4 to the input of the current mirror, these drain currents are fully added, and by folding back at a mirror ratio of 1/2, the added value of the drain currents of the MOS transistors M1 and M4, It outputs the average current of the sum of the drain currents of the MOS transistors M2 and M3. By preparing a pair of these and sending them to the output terminal, the current subtraction in the expressions (17) and (18) is executed, and only the first-order term of Vin is taken out.

FIG. 5 is a circuit diagram for explaining the third embodiment of the present invention. In this embodiment,
In the embodiment of FIG. 3, instead of applying the DC offset Vc applied to the inputs to the MOS transistors M3 and M4 forming the second differential pair to the gate voltage of the differential pair transistor as shown in FIG. , The source voltage of the differential pair transistor as shown in FIG.

The variable gain operation of the circuits of the embodiments of FIGS. 3 and 5 is by adding a relative voltage difference to the DC voltage between the gate and source of two differential pair transistors that supply the same input signal. Achieve this function. Therefore, the embodiment of FIG. 3 in which the gate voltage has an offset and the embodiment of FIG. 5 in which the source voltage has an offset are
Since the relative relationship between the gate and the source of the first differential pair and the second differential pair is exactly the same, the operation is exactly the same.

FIG. 6 shows a circuit example in which the average current detecting means is replaced with a concrete circuit in the third embodiment.
The average current detecting means is exactly the same as that of the second embodiment of FIG. 4, and the current copy circuit of the MOS transistors M1 and M2 composed of the MOS transistors M1 'and M2' and the MO.
It consists of a current copy circuit of MOS transistors M3 and M4 consisting of S-transistors M3 'and M4', and a two-output current mirror that adds up all of these copy currents and folds them back in half. And only the first-order term of Vin is taken out.

FIG. 7 shows a modification of the first embodiment of the present invention shown in FIG. This example is different from the circuit shown in FIG. 1 in that a grounded gate transistor is placed on the drain side of a differential transistor pair consisting of basic MOS transistors M1 and M2, and a drain current is output through these transistors. By adding these transistors, it is possible to prevent the output terminal from returning to the input side via the mirror capacitors of the MOS transistors M1 and M2 and deteriorating the frequency characteristic even if the output terminal swings with a large amplitude. ing.

FIG. 8 shows a differential output amplifier for voltage output formed by adding a resistance load to the circuit of the first embodiment of the present invention shown in FIG. Gm of this circuit is (1
Since it is expressed by the equation (2), the voltage gain GA between the input and output can be expressed as GA = 2k (VB + Vc-Vth) RL (20). Further, as is clear from the expressions (10) and (11), the output currents Io1 and Io2 have zero DC component. Therefore, the DC potential of the output is determined only by the bias voltage VB to be supplied and does not change even if the gain control voltage Vc is changed.

9 and 10 show that a filter circuit capable of adjusting frequency characteristics can be constructed by adding a load of a capacitor to the circuit of the embodiment shown in FIG. The circuit on the left side of FIG. 9 is the same first embodiment of the present invention as that of FIG. 1, and is represented by the symbol as shown on the right side of FIG. In this way, by combining this circuit and a capacitor to form a circuit as shown in FIG. 10,
This is a second-order BPF. Since each Gm has a completely linear characteristic as described above and each capacitor is a linear element, an undistorted output can be obtained from this filter.

Further, since each Gm value can be collectively controlled by changing Vc, the frequency characteristic can be proportionally controlled with respect to the frequency axis, and the filter characteristic of the filter characteristic due to the time constant deviation due to the semiconductor manufacturing variation can be obtained. The variation can be corrected. The application to such a filter is shown in FIG.
The filter circuit can be configured in exactly the same manner not only in the first embodiment shown in FIG. 3 but also in the second embodiment shown in FIG. 3 and the third embodiment shown in FIG. it can.

The first to third embodiments and specific examples of details thereof have been described above as examples using the present invention. In these examples, the configuration based on the NMOS is shown as an example, but the NMOS is changed to the PMOS and the power supply Vcc is changed.
By replacing GND with GND and GND with Vcc, a completely similar PMOS variable gain differential amplifier can be constructed. Even if you do this, the operation will be exactly the same,
It goes without saying that the exact same effect can be obtained.

[0032]

As described above, the C according to the present invention
The fully differential type variable gain amplifier composed of MOS has one or two sets of differential M in which the source connection point is connected to the constant voltage terminal.
A variable gain amplifier, which is composed of an OS transistor and an average current detection circuit, is provided with an input signal by adding a DC offset to the input, and in principle can obtain an undistorted output. In addition, the control range can be controlled from infinitesimally small, the control range is wide, the gain is directly proportional to the control voltage, so the control is easy and easy to handle. It has many advantages such as, and is extremely useful.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining a first embodiment of the present invention.

FIG. 2 is a circuit diagram for more specifically explaining the average current detection means in FIG.

FIG. 3 is a circuit diagram for explaining a second embodiment of the present invention.

FIG. 4 is a circuit diagram for more specifically explaining the average current detection means in FIG.

FIG. 5 is a circuit diagram for explaining a third embodiment of the present invention.

FIG. 6 is a circuit diagram for more specifically explaining the average current detection means in FIG.

FIG. 7 is a circuit diagram for explaining a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram for explaining an application example of the embodiment of FIG.

FIG. 9 is a circuit diagram for explaining another application example of the embodiment of FIG.

FIG. 10 is a circuit diagram for explaining yet another application example of the embodiment of FIG.

FIG. 11 is a circuit diagram for explaining a conventional variable gain differential amplifier composed of CMOS.

[Explanation of symbols]

11 ... Average current detecting means, M1 to M4, M1 'to M4' ... M
OS transistor, Vin ... Differential input voltage, Vc ... DC control voltage, Io1, Io2 ... Output differential current, Vcc ... Power supply,
GND ... Grounded.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-57-205796 (JP, A) JP-A-6-152320 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03G 3/10 H03G 3/30 H03F 3/34

Claims (9)

(57) [Claims] 1. A first differential transistor pair, which comprises a field effect transistor, applies an input differential signal between gate terminals, and has source terminals both connected to a reference potential, and a first differential transistor pair. Each drain end
Detecting the average value of the drain current flowing to the child, and <br/> average current supply means for supplying said the respective drain terminals wrap the average current, and offset control means for controlling the DC voltage of the input signal, The current drawn from each of the drain terminals is
A variable gain amplifier, which has different output currents, and controls the ratio of the amplitude of the output current to the amplitude of the input signal by controlling the DC voltage. 2. The average current supply means includes a second differential transistor pair having a gate terminal and a source terminal in common with the first differential transistor pair, and two equal current values.
A current mirror having an output current , adding the drain currents of the second differential transistor pair, and configuring the sum as the input of the current mirror. An average value of drain currents that are supplied to the respective drain terminals of the first differential transistor pair and two output currents of the current mirror flow through the respective drain terminals of the first differential transistor pair. 2. The variable gain amplifier according to claim 1, wherein the mirror ratio is set to be equal to. 3. The four field effect transistors forming the first and second differential transistor pairs have the same shape, and the mirror ratio of the current mirror is set to 1/2. 2. The variable gain amplifier according to 2 above. 4. A source composed of a field effect transistor
A first and second differential transistor pair which connects the terminal to a common reference potential point, each differential transistor
The same input differential signal is applied between the gate terminals of the pair of data transistors so that the drain currents that are outputs of opposite polarities with respect to the inputs of the first and second differential transistor pairs are added together . Connect the drain terminals to each other
A signal amplifying means for configuring it continues, and the addition of the first and second differential transistor pair
The average value of the drain currents is detected, and the average currents are returned to the pair of connected drain terminals.
An input differential signal having a controllable DC offset between the average current supply means for supplying each and the first and second differential transistor pairs, respectively.
Consists offset control means for providing, it is taken out from the connection point of the respective drain terminals
A variable gain amplifier, wherein a current is used as each output current, and the ratio of the amplitude of the output current to the input signal amplitude is controlled by controlling the DC offset voltage. 5. A source composed of a field effect transistor
A first differential transistor pair having a terminal connected to a first reference potential point and a second differential transistor having a source terminal connected to a second reference potential point
A differential transistor pair, each differential Trang
The same input differential signal is applied between the gate terminals of the pair of transistors, and the drain currents that become outputs of opposite polarities with respect to the inputs of the first and second differential transistor pairs are added together . Connect the drain terminals to each other
The addition of the signal amplifying means, said first and second differential transistor pair constituting Te
The average value of the drain currents is detected, and the average currents are returned to the pair of connected drain terminals.
And respectively supplied average current supplying means consists of a offset control means for imparting a controllable DC offset voltage between the first reference potential point and the second reference potential point, the drains Taken out from the connection point of the terminal
A variable gain amplifier, wherein a current is used as each output current, and the ratio of the amplitude of the output current to the input signal amplitude is controlled by controlling the DC offset voltage. 6. The average current supply means includes a third differential transistor pair having a gate terminal and a source terminal in common with the first differential transistor pair, and a gate terminal and a source terminal of the second differential transistor pair. A fourth differential transistor pair common to the first and second moving transistor pairs, and a current mirror having two output currents having the same current value.
Adding four drain currents of the differential transistor pair,
Configure this to be the input of the current mirror,
The two output currents of the current mirror are
Characterized in that supplying each pair of drain terminals, setting the mirror ratio such that the two output current is equal to the average value of <br/> summed drain current said at respective drain terminals of said current mirror The variable gain amplifier according to claim 4 or claim 5. 7. A resistor is connected as a load to the output terminal that outputs the output current , and a difference current between the output terminals is output.
The variable gain amplifier according to claim 1, wherein the ratio of the output amplitude to the input amplitude is controlled by changing the DC offset voltage. 8. A filter circuit is configured by connecting a capacitor as a load to the output terminal that outputs the output current so as to have a function of an integrating circuit, and connecting two or more such integrating circuits to each other to connect them. 6. The variable gain amplifier according to claim 1, wherein the frequency characteristic of the filter is controlled by changing the DC offset voltage. 9. equal all shapes of the eight field effect transistors constituting said first to fourth differential transistor pair, claims, characterized in that setting the mirror ratio of the current mirror to 1/2 6. The variable gain amplifier according to item 6.