JP2004096324A - Amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplifier circuit capable of highly accurately cancelling offset and able to be made small in size, low in power consumption, low in noise, and operated at a high speed. <P>SOLUTION: A capacitor C1 is connected to the output terminal of an operational amplifier OP 1. First and second switching elements SW1, SW2 electrically connect the input terminal of the operational amplifier OP 1 and the terminal of a capacitor C1 at a post-stage side to a reference potential level, thereby charging an offset voltage to the capacitor C1. Then the second switching element SW2 is turned off to permit the capacitor C1 to hold the voltage, and the first switching element SW1 is thrown to the position of a signal input terminal IN side to give the input signal to the operational amplifier OP1 and subtract the offset voltage for offset cancellation. Thus, the number of required elements is decreased, the deterioration in the accuracy due to dispersion in the element characteristics is suppressed, and downsizing, low power, low noise and high speed operations are promoted at the same time. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an amplifier circuit, and more particularly to a high-accuracy and high-amplification amplifier circuit that handles a low-frequency small voltage including a DC component.
[0002]
[Prior art]
Although the high integration and low power technology of CMOS circuits in recent years greatly contributes to the miniaturization and low power of the amplifier circuit, an operational amplifier having a CMOS circuit configuration is basically used as an amplifier circuit of a sensor device for detecting a minute voltage. When an amplifier circuit as an element is employed, the following problem occurs.
[0003]
As shown in FIG. 4, an operational amplifier having a CMOS circuit configuration (hereinafter, CMOS operational amplifier) connects a differential section including N-channel MOS transistors N1 and N2, and connects the differential section to a high-potential power supply terminal VDD. P-channel MOS transistors P1 and P2, an N-channel MOS transistor N3 for connecting the differential section to the low-potential power supply terminal VSS, a P-channel MOS transistor P3 and an N-channel MOS transistor N4 Output unit. The negative phase input terminal IN− and the positive phase input terminal IN + are connected to the gates of the MOS transistors N1 and N2, respectively, and the output terminal OUT is connected to the connection point between the MOS transistors P3 and N4. A bias voltage terminal VB is connected to the gates of the MOS transistors N3 and N4. Such a CMOS operational amplifier has an input offset voltage V due to variations in threshold voltages of the MOS transistors N1 and N2. _OS Having. For example, in a positive-phase operational amplifier using this, as shown in FIG. 5, the negative-phase input terminal of the operational amplifier OP is connected to a reference potential Vref via a resistor R1, and the operational amplifier OP is connected via a resistor R2. The input terminal is connected to the output terminal OUT, and the positive-phase input terminal is connected to the signal input terminal IN. The output terminal OUT has an input offset voltage V _OS Offset voltage αV obtained by multiplying the gain by α _OS Occurs. This output offset voltage causes a large output offset voltage (hereinafter referred to as an offset voltage) when a CMOS operational amplifier is used in a sensor device that handles a small signal, and in some cases, its operation region deviates from a linear region. It becomes a clip state. Therefore, various modifications have been proposed to cancel the offset voltage.
[0004]
For example, Japanese Patent Application Laid-Open No. 6-45875 discloses a switched capacitor amplifier circuit in which a capacitor CL is provided between a negative input terminal of an operational amplifier and a reference potential as shown in FIG. An operational amplifier load during operation is disclosed. The operation is as follows. At the time of the cancel operation, the switches A3, 4, 5 are turned on, and the switches B6, 7 are turned off. _in And the input offset voltage is V _OS Then, the capacitor αC10 has V _OS -V _in Only charge the capacitor C11 with V _OS Just charge. Conversely, during the amplification operation, the switches A3, 4, 5 are turned off, and the switches B6, 7 are turned on. _out Then, the capacitor αC10 has V _OS Only charge the capacitor C11 with V _OS -V _out Just charge. Here, the charge at the inverting input of the operational amplifier is constant, and αC (V _OS -V _in ) + CV _OS = ΑCV _OS + C (V _OS -V _out ) Holds and V _out = ΑV _in And the offset voltage is cancelled.
[0005]
Japanese Patent Application Laid-Open No. 6-54118 discloses that in an image sensor device, as shown in FIG. An analog switch 26 and a capacitor 27 are connected in parallel between the positive-phase input terminal (point A) and ground, and the output terminal of the operational amplifier 22 Is connected to the positive-phase input terminal of the operational amplifier 23 via the analog switch 28 and the capacitor 29, and the analog switch 30 and the capacitor 31 are connected in parallel between the positive-phase input terminal (point B) and the ground. The switch 4 (1) is connected between the positive input terminal of the operational amplifier 21 and the ground, and the analog switch 5 (1) is connected between the output terminal of the operational amplifier 23 and the output line OUTL. Connect the amplifier circuit is disclosed which enables cancel the offset voltage. The operation is as follows. At time t1, the analog switches 24, 26, 28 and 30 are turned on to charge the capacitors 25 and 29. Voltage V between terminals of capacitors 25 and 29 _c25 , V _c29 Is V _c25 = 20 (V _in + _Vos1 ), V _c29 = 20V _os2 It becomes. Where V _in Is the input voltage, V _os1 , V _os2 Are input offset voltages of the amplifiers 21 and 22, respectively. Next, at time t2, the analog switches 24, 26, 28, and 30 are turned off, and the switch 4 (1) is turned on to discharge the charge accumulated in the signal line L (1). Next, when the analog switches 24 and 28 are turned on at time t3, the potential V at the point A _A , The potential V at point B _B Is V _A = (20 _Vos1 -V _c25 ) / 2 + V _os2 = -V _in + V _os3 , V _B = ｛20 (-10V _in + V _os2 ) -V _c29 ｝ / 2 + V _os3 = -100V _in + V _os3 It becomes. Where V _os3 Is the input offset voltage of the operational amplifier 23, and the input offset voltage V _os1 , V _os2 Is canceled, the overall circuit gain can be made 100 times, and the final stage input offset voltage V _os3 Influence on the final output can be reduced.
[0006]
[Problems to be solved by the invention]
However, in the switched capacitor amplifier circuit shown in FIG. 6, variations actually occur in each capacitor due to a process problem, and it is difficult to sufficiently cancel the offset voltage. In addition, the area occupied by the capacitor increases, which hinders miniaturization of the integrated circuit chip when integrating the amplifier circuit. In addition, the amplification factor cannot be made variable, and is not suitable as an amplification circuit for applications requiring fine adjustment, such as amplification of a minute voltage.
[0007]
In the case where the three operational amplifiers shown in FIG. 7 are connected in cascade via a capacitor and an analog switch, the positive-phase input terminals of the operational amplifiers 22 and 23 float between time t2 and time t3. Capacitors 27 and 31 are provided in order to hold the charges charged in the capacitors 25 and 29 during that period, in other words, to hold the data previously input sufficiently during that time. , 31 require a large capacity. Also, as in the case of the above-described switched capacitor amplifier circuit, the accuracy of canceling the offset voltage also depends on the accuracy of the capacitors 27 and 31, so that it is difficult to cancel the offset voltage with high accuracy. Further, since the analog switches 24 and 28 are provided on the signal transmission path of each operational amplifier, noise due to switching and transmission delay due to parasitic capacitance occur. As described above, the number of constituent elements is large, and the circuit configuration, which requires a large number of control lines for switching elements, is complicated, and this also hinders downsizing, low power, and high-speed operation of the device.
[0008]
Accordingly, an object of the present invention is to provide an amplifier circuit that can perform offset cancellation with high accuracy, and that can be downsized, reduced in power, reduced in noise, and operated at high speed.
[0009]
[Means for Solving the Problems]
An amplifier circuit according to the present invention includes an operational amplifier, a capacitor having one terminal connected to the output terminal of the operational amplifier, and the other terminal connected to an output buffer, and an input terminal of the operational amplifier connected to a signal input terminal or a reference terminal. A first switching element for selectively conducting to a potential, and a second switching element for selectively conducting the other terminal of the capacitor to the reference potential, wherein both the first and second switching elements are connected to the reference potential. And the second switching element is turned off, and then the first switching element is turned on to the signal input terminal side.
[0010]
In the amplifier circuit of the present invention, each of the output terminals is connected to a respective capacitor, and a plurality of cascaded operational amplifiers are connected to the input terminal of the next stage via the respective capacitors. A first switching element for selectively conducting an input terminal of the preceding operational amplifier to a signal input terminal or a reference potential; an output buffer connected to the last operational amplifier via a capacitor; And a plurality of second switching elements for selectively conducting a terminal on the next stage side to the reference potential, and conducting both the first and second switching elements to the reference potential side, and then from the final stage. It is also preferable that the first switching element is turned on to the signal input terminal side after the second switching element of each stage is sequentially turned off to the front stage.
[0011]
Further, it is preferable that the operational amplifier and the output buffer include a field effect transistor.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail based on examples with reference to the accompanying drawings.
[0013]
The configuration of the amplifier circuit according to the first embodiment of the present invention will be described with reference to the block diagram of FIG. The operational amplifier OP1 is similar to the operational amplifier composed of the MOS transistors shown in FIG. The operational amplifier OP1 has its negative-phase input terminal − connected to the reference potential Vref via the resistor R1 and to the output terminal X of the operational amplifier OP1 via the resistor R1. It is connected to the signal input terminal IN via one switching element SW1, the operational amplifier OP1 forms a positive-phase operational amplifier, and the amplifier circuit of the present example functions as a positive-phase operational amplifier.
[0014]
The output terminal X of the operational amplifier OP1 is connected to the input terminal of the output buffer BUF via the capacitor C1. The output buffer BUF is also formed of a MOS transistor and has a high-impedance input terminal. The terminal of the capacitor C1 connected to this input terminal is connected to the operational amplifier by turning off the second switching element SW2. As long as the input of OP1 does not change, the previous charge can be held. The output buffer BUF only needs to have a high-impedance input terminal, and other configurations may be appropriately selected. The output terminal OUT ′ of the output buffer BUF is an output terminal to a not-shown subsequent circuit of the amplifier circuit of the present example. The connection point OUT between the capacitor C1 and the output buffer BUF is connected to the reference potential Vref via the second switching element SW2.
[0015]
The first switching element SW1 selectively connects the positive-phase input terminal + to the signal input terminal IN or the reference potential Vref, and is, for example, a three-terminal analog switch including a MOS transistor. The second switching element SW2 is also an analog switch composed of a MOS transistor. The conduction state of the first and second switching elements SW1 and SW2 is controlled by a clock signal from a control circuit (not shown), and operates as described later.
[0016]
Next, the operation of the amplifier circuit of the present example composed of the above components will be described. In the operation of the amplifier circuit of this example, both the first and second switching elements SW1 and SW2 are made conductive to the reference potential Vref side, and the positive-phase input terminal + and the connection point OUT are made conductive to the reference potential Vref (state 1). . Here, the potential of the reference potential Vref is set to 0 V, and the potential of the output terminal X in the state 1 is set to V _X1 And the potential of the connection point OUT is V _OUT1 And the input offset voltage of the operational amplifier OP1 is V _OS When the resistance values of the resistors R1 and R2 are R1 and R2, respectively, the capacitance value of the capacitor C1 is C, and the charge charged in the capacitor C1 in the first state is ΔQ, the following equation (1) is established.
V _OUT1 -V _X1 = -V _OS × (1 + R2 / R1) = ΔQ / C (1)
[0017]
That is, the input offset voltage V in the operational amplifier OP1 _OS The capacitor C1 is charged with a charge corresponding to the error of the output voltage caused by the above.
[0018]
Next, the second switching element SW2 is turned off to disconnect the connection point OUT and the reference potential Vref (state 2). Here, the input terminal of the output buffer BUF has a high impedance, and the terminal on the connection point OUT side of the capacitor C1 becomes floating by turning off the second switching element SW2, and the positive-phase input terminal + becomes the reference potential. Since the potential of the output terminal X does not change while being connected to Vref, the charge charged in the capacitor C1 in the first state is held. Here, the voltage held between the terminals of the capacitor C1 is the input offset voltage V _OS The capacitance value of the capacitor C1 may be smaller than that of the capacitor 25 or the like as in the conventional capacitor shown in FIG.
[0019]
Next, the first switching element SW1 is disconnected from the reference potential Vref, and is made conductive to the signal input terminal IN side (state 3). As a result, the positive-phase input terminal + is changed to the reference potential Vref and connected to the signal input terminal IN, and an input signal is input to the operational amplifier OP1. Here, the charge of the capacitor C1 in the states 1 and 2 is stored, and the potential of the output terminal X in the state 3 is set to V _X3 And the potential of the connection point OUT is V _OUT3 And the potential of the input signal is V _in Then, the following equation (2) holds.
V _OUT3 -V _X3 = V _OUT3 − (V _in + V _OS ) × (1 + R2 / R1) = ΔQ / C (2)
By substituting equation (1) into equation (2), the following equation (3) holds.
V _OUT3 = V _in × (1 + R2 / R1) ・ ・ ・ ③
[0020]
From equation (3), in state 3, the input offset voltage V _OS Output voltage error V _OS × (1 + R2 / R1), that is, the output voltage V with the offset voltage canceled _OUT3 Occurs at the connection point OUT. This is output from an output terminal OUT 'of the output buffer BUF to a subsequent circuit (not shown).
[0021]
The amplifier circuit of this example can amplify an input signal without being affected by an input offset voltage by repeating states 1, 2, and 3. During the transition period from state 1 to state 2, the error V _OS A voltage corresponding to × (1 + R2 / R1) may be set as a period during which the capacitor C1 can be charged. The period between the transition from the state 2 to the state 3 may be a period during which the switching element SW2 can be sufficiently turned off by the clock signal, and the period from the state 3 to the state 1 is held by the capacitor C1. Any period may be used as long as the offset voltage can be canceled by the voltage of the error, and may be appropriately determined according to the subsequent circuit. For example, the state may be switched from state 3 to 1 in accordance with the sampling timing of the subsequent circuit.
[0022]
As described above, in the amplifier circuit of this example, the input offset voltage V _OS After holding the offset voltage generated between the terminals of the capacitor C1, the input signal is input and the offset voltage held in the capacitor C1 is subtracted to perform offset cancellation. Therefore, offset cancellation can be performed with a simple configuration including one capacitor and two switching elements, and the size and power consumption of the amplifier circuit can be reduced.
[0023]
In the case of using a plurality of capacitors for holding the offset voltage of one operational amplifier as in the conventional device shown in FIGS. 6 and 7, it was difficult to perform the offset cancellation with high accuracy due to the variation in the capacitance value of the capacitor. In this amplifier circuit, the offset voltage of one operational amplifier is held by one capacitor and used for canceling operation, so that the adverse effects due to such variations in the capacitance values of a plurality of capacitors are significantly reduced, and highly accurate offset cancellation is possible. It becomes.
[0024]
In the conventional device shown in FIG. 7, an input signal is input, and a voltage corresponding to the input signal and an offset voltage are held in a capacitor, and then offset cancellation is performed by subtracting the offset voltage. It was necessary to charge only the voltage plus the voltage of the input signal, and it was difficult to reduce the capacitance value of the capacitor, in other words, the area. For this reason, the conventional capacitor shown in FIG. 7 also requires the holding capacitors 27 and 31. On the other hand, in the present example, the capacitor C1 only needs to be able to hold the offset voltage, so that the capacitance value of the capacitor C1, that is, the area thereof can be suppressed as much as possible. There is no need to provide a capacitor, and the integration of the amplifier circuit is highly effective in reducing the chip area.
[0025]
Further, in the conventional device shown in FIG. 7, by providing an analog switch between the output terminal of the operational amplifier and the capacitor and turning them off, the voltage charged in the capacitor affects the input side of each operational amplifier. The circuit configuration and its control are complicated by that amount, and in addition, there is a problem that circuit characteristics such as noise and transmission delay due to the switching of the analog switch and the influence of parasitic capacitance are deteriorated. Was. On the other hand, in the amplifier circuit of the present example, the first and second switching elements SW1 and SW2, both of which are made conductive to the reference potential in order to charge the capacitor C1 with the offset voltage, have the first and second switching elements SW1 and SW2 on the input terminal side of the operational amplifier OP1. By turning off the second switching element SW2 on the output side before the one switching element SW1, the offset voltage is held in the capacitor C1 without being affected by the input side of the operational amplifier. As a result, it is not necessary to provide an analog switch separately between the output terminal of the operational amplifier OP1 and the capacitor C1, the circuit configuration and its control can be simplified, noise and transmission delay can be suppressed as much as possible, Power consumption, low noise, and high-speed operation can be promoted.
[0026]
Next, a second embodiment of the present invention will be described. In the first embodiment, the amplifier circuit functioning as a positive-phase operational amplifier has been described. However, the present invention is not limited to this, and may be an amplifier circuit functioning as a negative-phase operational amplifier. Will be described. The amplifier circuit of this example is configured as shown in FIG. 2, and in FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. The positive-phase input terminal of the operational amplifier OP1 is connected to the reference potential Vref, the negative-phase input terminal − is connected to the first switching element SW1 via the resistor R1, and is connected to the output terminal X via the resistor R2. . Thus, the operational amplifier OP1 forms an anti-phase operational amplifier, and the amplifier circuit of the present example functions as an anti-phase operational amplifier. The first switching element conducts the negative-phase input terminal − to the reference potential Vref via the resistor R1 and conducts to the signal input terminal IN. Other connection relationships are the same as those in the configuration of FIG.
[0027]
Next, the operation of this example will be described. The first and second switching elements SW1 and SW2 are both made conductive to the reference potential Vref side, and the negative-phase input terminal − and the connection point OUT are made conductive to the reference potential Vref (state 1). In the first state, the following equation (1) ′ holds for ΔQ of the electric charge charged in the capacitor C1. In Expression (1) ', the same reference numerals as those in Expression (1) indicate the same values. The same applies to the following equations.
V _OUT1 -V _X1 = V _OS × (R2 / R1) = ΔQ / C (1) '
[0028]
Next, the second switching element SW2 is turned off to disconnect the connection point OUT and the reference potential Vref (state 2). When the second switching element SW2 is turned off, the terminal on the connection point OUT side of the capacitor C1 becomes floating, and the potential of the output terminal X remains while the negative-phase input terminal − is connected to the reference potential Vref via the resistor R1. Does not change, the electric charge charged in the capacitor C1 in the first state is held.
[0029]
Next, the first switching element SW1 is disconnected from the reference potential Vref, and is made conductive to the signal input terminal IN side (state 3). As a result, the negative-phase input terminal-is changed to the reference potential Vref via the resistor R1 and connected to the signal input terminal IN, and the input signal is input to the operational amplifier OP1. Here, the charge of the capacitor C1 in the states 1 and 2 is stored, and the following equation (2) ′ is satisfied.
V _OUT3 -V _X3 = V _OUT3 + (V _in + V _OS ) × (R2 / R1) = ΔQ / C (2) '
By substituting equation (1) 'into equation (2)', the following equation (3) 'holds.
V _OUT3 = -V _in × (R2 / R1) ・ ・ ・ ▲ 3 ▼ '
[0030]
From Equation (3) ′, in state 3, the error V of the output voltage caused by the input offset voltage Vos in the operational amplifier OP1 _OS × (R2 / R1), that is, the output voltage V with the offset voltage canceled _OUT3 Occurs at the connection point OUT. This is output from an output terminal OUT 'of the output buffer BUF to a subsequent circuit (not shown).
[0031]
The amplifying circuit functioning as the reverse-phase amplifier of the present example having the configuration and operation as described above has the same operation and effect as the amplifying circuit functioning as the positive-phase amplifier of the first embodiment.
[0032]
Next, a third embodiment of the present invention will be described. In the first and second embodiments, the amplifier circuit using one operational amplifier has been described. However, the present invention is not limited to this. To make it more suitable for handling a small voltage and to obtain a larger amplification factor. Alternatively, an amplifier circuit formed by cascading a plurality of operational amplifiers may be configured as follows. FIG. 3 shows the amplifier circuit of this example. In this figure, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. The operational amplifier OP2 is similar to the operational amplifier OP1, and its positive-phase input terminal + is connected to the output terminal X of the operational amplifier OP1 via the capacitor C1. The output terminal Y of the operational amplifier OP2 is connected to the input terminal of the output buffer BUF via the capacitor C2. A second switching element SW3 is further connected between the connection point OUT ″ between the capacitor C2 and the output buffer BUF and the reference potential Vref.
[0033]
In this example, the resistors R2 and R3 are connected in series between the negative-phase input terminal − and the output terminal X of the operational amplifier OP1. Switching elements SW4 and SW5 for short-circuiting the both ends are connected between both ends of the resistors R2 and R3, and the ON and OFF of each of the switching elements SW4 and SW5 are controlled by a clock signal from a control circuit (not shown). The resistance value connected between the negative-phase input terminal − and the output terminal X of the operational amplifier OP1 can be selected, and the amplification factor of the positive-phase operational amplifier included in the operational amplifier OP1 is variable. It is advantageous for an amplifier circuit that handles a very small voltage that such an amplification factor can be easily adjusted. For example, in the switched capacitor amplifier circuit shown in FIG. 6, it was difficult to adjust the gain.
[0034]
The negative-phase input terminal of the operational amplifier OP2 is connected to the reference potential Vref via the resistor R4, and between the negative-phase input terminal and the output terminal Y, the resistors R5 and R6 are connected in series to connect the positive-phase operational amplifier. Constitute. Similarly to the normal-phase operational amplifier included in the operational amplifier OP1, switching elements SW6 and SW7 for short-circuiting the both ends are connected between both ends of the resistors R5 and R6, and the operational amplifier OP2 is switched by the switching elements SW6 and SW7. The variable gain of the positive-phase operational amplifier is variable.
[0035]
The operational amplifier OP2 has a high-impedance input terminal. The terminal of the capacitor C1 connected to the input terminal is floating when the second switching element SW2 is off, and the input of the previous operational amplifier changes. Unless otherwise, the charge of the capacitor C1 can be held. The operational amplifier OP2 only needs to have a high impedance input terminal.
[0036]
Next, the operation of the amplifier circuit of this example will be described. First, the first switching element SW1, the second switching elements SW2 and SW3 are all turned on to the reference potential Vref side, and the positive-phase input terminal + of the operational amplifier OP1 and the positive-phase input terminal + of the operational amplifier OP2 (connection point OUT ) And the connection point OUT ″ to the reference potential Vref (state 1). With the same operation as in the first embodiment, the difference between the terminals of the capacitor C1 due to the input offset voltage of the operational amplifier OP1. A voltage corresponding to an error due to the input offset voltage of the operational amplifier OP2 is generated between the terminals of the capacitor C2 by the same action.
[0037]
Next, the second switching element SW3 of the last operational amplifier OP2 is turned off (state 2-1). As a result, the terminal on the connection point OUT "side of the capacitor C2 becomes floating, and the positive-phase input terminal + of the operational amplifier OP2 is connected to the reference potential Vref, so that the input offset voltage of the operational amplifier OP2 is connected between the terminals of the capacitor C2. Then, the second switching element SW2 of the foremost operational amplifier OP1 is turned off (state 2-2), whereby the terminal on the connection point OUT side of the capacitor C1 becomes floating. Since the positive-phase input terminal + of the operational amplifier OP1 is connected to the reference potential Vref, a voltage corresponding to an error due to the input offset voltage of the operational amplifier OP1 is held between the terminals of the capacitor C1.
[0038]
Next, the first switching element SW1 is disconnected from the reference potential Vref, and is made conductive to the signal input terminal IN side (state 3). As a result, the positive-phase input terminal + of the operational amplifier OP1 is connected to the signal input terminal IN instead of the reference potential Vref, and an input signal is input to the operational amplifier OP1. By the same operation as in the first embodiment, an output voltage of the operational amplifier OP1 having its offset voltage canceled is generated at the connection point OUT. In the operational amplifier OP2 to which this output voltage is input, an output voltage having its offset voltage canceled is generated at the connection point OUT "in the operational amplifier OP2 by the same operation as in the first embodiment. This is the output terminal of the output buffer BUF. OUT ′ is output to a subsequent circuit (not shown).
[0039]
As described above, like the amplifier circuit of the present embodiment, even if the operational amplifier is multi-stage based on the amplifier circuit of the first embodiment, the first switching element SW1, the second switching element SW2, and the SW3 are connected to the reference potential side. And the capacitors C1 and C2 in each stage are charged with the offset voltage of the operational amplifier in each stage, and the second switching elements SW2 and SW3 are turned off in order from the second switching element in the last stage. After the electric charge of each stage is held and the voltage between the terminals is held, the first switching element SW1 is made conductive to the signal input terminal IN side, so that the operational amplifier of each stage is the same as in the first embodiment. Can cancel the offset voltage of the operational amplifier at each stage. Therefore, the amplifying circuit of the present embodiment also has the same operation and effect as those of the first embodiment. Further, in the amplifier circuit of the present embodiment, a large amplification factor can be obtained by increasing the number of stages of the operational amplifier as compared with that of the first embodiment. Further, in the amplifier circuit of the present example, since there is no switching element such as an analog switch between the output of the operational amplifier and the capacitor as in the conventional circuit shown in FIG. Even if proceeding, it becomes possible to minimize problems such as noise, transmission delay, and complicated control due to the switching element.
[0040]
In this embodiment, the number of stages of the operational amplifier is two. However, the number of stages may be further increased by using the method of the above-described embodiment. Each of the operational amplifiers, especially those in the second and subsequent stages, may have a high impedance input terminal.
In this embodiment, the amplifier circuit having a multi-stage operational amplifier configuration functioning as a positive-phase operational amplifier has been described. It is also possible to configure an amplifier circuit having a multi-stage operational amplifier configuration that functions as an antiphase operational amplifier.
[0041]
【The invention's effect】
In the amplifier circuit of the present invention, offset cancellation can be performed using a single capacitor. Therefore, unlike the conventional one using a plurality of capacitors, there is no decrease in accuracy due to variation in the capacitance value of the capacitor, and high-accuracy offset cancellation is possible. It becomes. This makes it possible to provide a high-precision amplifier circuit that is suitable for applications handling minute voltages, such as sensor devices. Further, since the present invention is not a switched-capacitor-type amplifier circuit, it is possible to adjust an amplification factor which cannot be achieved with a switched-capacitor-type amplifier circuit.
[0042]
Further, the capacitance value of the capacitor may be such that the voltage corresponding to the error due to the input offset voltage of the operational amplifier can be charged, and a capacitor having a small capacitance value can be used. In the case of performing offset cancellation after capturing an input signal as in a conventional device, a large-capacity capacitor is required to be able to hold the voltage including the voltage of the input signal. Therefore, the size of the capacitor can be reduced. In particular, when the amplifier circuit is integrated, it is advantageous in promoting the miniaturization of the chip by the small area occupied by the capacitor.
[0043]
Further, since the second switching element is turned off prior to the first switching element and the other terminal of the capacitor is separated from the reference potential and floats, the error due to the input offset voltage is not affected by the input change of the operational amplifier. The voltage can be held in the capacitor, and there is no need to provide a switching element between the operational amplifier and the capacitor as in the prior art. Therefore, it is possible to eliminate problems such as switching noise due to the switching element, transmission delay due to parasitic capacitance, complicated switching control, etc., and to promote low noise, high speed operation, and low power of the amplifier circuit. Can be. Further, since there is no need to provide a switching element between the operational amplifier and the capacitor and the above-described problem does not occur, it is easy to increase the number of stages of the operational amplifier in the amplifier circuit, and it is suitable for handling a very small voltage. It becomes easy to configure an amplifier circuit having a large amplification factor.
[0044]
In addition, in the amplifier circuit of the present invention, since the capacitance value of the capacitor can be reduced and the number of necessary switching elements can be reduced as described above, miniaturization, low power, low noise, and high speed operation can be achieved. You can proceed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an amplifier circuit according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of an amplifier circuit according to a second embodiment of the present invention.
FIG. 3 is a block diagram showing the configuration of the amplifier circuit according to the first embodiment of the present invention.
FIG. 4 is an electric circuit diagram showing a configuration of a CMOS operational amplifier.
FIG. 5 is a block diagram showing a configuration of a positive-phase operational amplifier.
FIG. 6 is a block diagram showing a configuration of a conventional offset-cancelled switched-capacitor amplifier circuit.
FIG. 7 is a block diagram showing a configuration of a conventional offset canceling amplifier circuit.
[Explanation of symbols]
OP1, OP2 Operational amplifier
BUT output buffer
SW1 First switching element
SW2, SW3 Second switching element
C1, C2 capacitors

Claims (3)

An operational amplifier, a capacitor having one terminal connected to the output terminal of the operational amplifier and the other terminal connected to the output buffer, and an input terminal of the operational amplifier selectively connected to a signal input terminal or a reference potential. A first switching element, and a second switching element for selectively conducting the other terminal of the capacitor to the reference potential,
The first and second switching elements are both turned on to the reference potential side, and then the second switching element is turned off, and then the first switching element is turned on to the signal input terminal side. Amplifier circuit. Each output terminal is connected to a respective capacitor, and a plurality of cascaded operational amplifiers connected to the input terminal of the next stage via the respective capacitors, and the input terminal of the operational amplifier at the forefront stage. A first switching element for selectively conducting to a signal input terminal or a reference potential, an output buffer connected via a capacitor to the last operational amplifier, and a next stage terminal of each of the capacitors to the reference A plurality of second switching elements for selectively conducting to a potential,
The first and second switching elements are both turned on to the reference potential side, and then the second switching elements in each stage are sequentially turned off from the last stage to the foremost stage. An amplifier circuit characterized by conducting to a signal input terminal side. 3. The amplifier circuit according to claim 1, wherein the operational amplifier and the output buffer are formed of a field effect transistor.

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