JPH01272312A - Switched capacitor circuit - Google Patents

Abstract

PURPOSE:To prevent the generation of a DC offset by constituting an input capacitor so that a transistor(TR) having the same size as a TR connected to an inverted input terminal of an operational amplifier to a non-inverted input terminal. CONSTITUTION:When a clock signal phi1 is turned from a high (H) level to a low (L) level in a switched capacitor circuit, charge is drawn by the parasitic capacity of a TR M5 and charge is also drawn by that of a TR M8. Since the sizes of the TRs M5, M8 are the same and the capacity of the capacitors C2, C3 is the same, voltage changes due to charge drawn from respective TRs are applied to two input terminals of an operational amplifier A and a DC offset is not generated. When a clock signal phi2 is turned from L to H, charge is injected into TRs M4, M9 through respective parasitic capacitors. Since the sizes of the TR M4, M9 are the same, voltage changes due to the charge injected from respective TRs are applied to respective input terminals of the operational amplifier A with the same phase. Thereby, no DC offset is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a switched capacitor circuit, and particularly to a switched capacitor circuit used in an integrator that reduces the influence of clock feedthrough caused by a MOS switch.

[Conventional technology]

Conventionally, this type of switched capacitor circuit has had the configuration shown in FIG.

M1 to M5 are switches formed of n-type MOS transistors, each driven by a two-phase clock ψ1° ψ2 as shown in FIG.

When the clock signal φ1 is at high level, the transistor Ml
, M3 are turned on, the input voltage is sampled to the capacitor C1, and the transistor M5 is turned on, so that the charge stored in the capacitor C2 is discharged.

Next, clock signal ψ1. When both ψ2 are at a low level, all transistors are turned off, and when the clock signal ψ2 is at a high level, the charge on the capacitor C1 is inverted and transferred to the capacitor C2, and an output voltage of -VIN is generated.

However, in actual circuits, charge is injected or extracted when the clock is turned on or off due to the DC offset voltage inherent in the operational amplifier and the capacitance f't that exists between the gate, source, and drain of the MOS transistor. This causes a DC offset.

A circuit that improves this point is Electronics Letters (
ELECTRONIC8LETTER8) Volume 18 No. 1
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2 and output terminal ■OvT between MOS type transistor M
By connecting MOS transistor M7f between capacitor C2 and ground, clock signal ψ1 becomes
The DC offset voltage of the operational amplifier is sampled on the capacitor C2 when the clock signal ψ2 is at the blank level, and the DC offset voltage of the operational amplifier is canceled when the clock signal ψ2 is at the blank level.

Also, MO is connected between the non-inverting input terminal of the operational amplifier and the ground.
An S-type transistor M8 and a capacitor C3 are connected. At this time, by making the transistor M8Q the same size as the transistor M5, and making the capacitance f of the capacitors C2 and C3 the same, when the clock signal ψ1 changes from on to off, the gate of the transistor M5 and the inverting input terminal of the operational amplifier A charge of the same magnitude as the charge injected into the parasitic capacitance generated between them is injected from the transistor M8 into the capacitor C3, thereby canceling the offset voltage.

[Problem that @#4 attempts to solve] The conventional switched capacitor circuit described above cancels the feedthrough of the transistor M5 when the clock signal ψ1 goes from high to low level, but when the clock signal ψ2 goes low There is a drawback that an offset occurs due to charge being extracted by the gate, source, and drain amount of the transistor M4 when the voltage goes from high level to high level.

[Means to solve the problem]

In the switched capacitor circuit of the present invention, the first phase signal is connected between the input image and the ground, and the second phase signal is connected between the ground and the inverted input of the operational amplifier by inverting the polarity of the first phase signal. A first terminal is connected between the inverting input terminal of the operational amplifier and ground at the first phase signal, and is connected between the inverting input terminal and the operational amplifier at the second phase signal. a second capacitor connected between output terminals, a first terminal connected to ground and a non-inverting input terminal of the operational amplifier; a third capacitor whose first terminal is connected to a non-inverting input terminal of the operational amplifier with a phase signal of , and whose second terminal is connected to ground; a MOS transistor whose terminal and an inverting input terminal are short-circuited; and a MOS transistor whose source and drain are short-circuited and connected to the non-inverting input terminal of the operational amplifier and whose gate is applied with an on-level voltage at the second phase signal. At the time of the first and second phase signals, the first. Second. and a MOS transistor connected to a third capacitor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

Transistors M1 to M9 are N-type MOS transistors, and are driven by clocks ψ1 and ψ2 shown in FIG. 5, respectively. Cl-C5 indicates a capacitor, and Cl-C5 indicates an operational amplifier.

Transistor M5 and transistor M8 are the same size, and capacitors C2 and C3 are also the same size. Further, the transistor M9 has the same size as the transistor M4, and its source and drain are short-circuited.

Next, the circuit operation will be explained. When the clock signal ψ1 is at a high level, the input voltage is sampled to the capacitor CI, and the DC offset voltage of the operational amplifier is sampled to the capacitor C2. Also, the charge in the capacitor C3 is discharged.

Next, when the clock signal ψ1 changes from high to low level, the charge is extracted by the parasitic capacitance between the gate and source or drain of the transistor M5. Also,
Charge is extracted by the parasitic capacitance of transistor M8. At this time, since the sizes of transistors M5 and M8 are the same and the sizes of capacitors C2 and C3 are the same, the voltage change due to the charge extracted from each transistor is applied to the two input terminals of the operational amplifier in the same phase. , no DC offset occurs.

Next, when the clock signal ψ2 changes from the low level to the high level, the transistor M4 is turned on, and at this time, charges are injected through the gate-source-drain capacitance it. On the other hand, charge is injected through the parasitic capacitance between the gate, source, and drain of transistor M9. Transistor M4
Since the magnitudes of and M9 are the same, voltage changes due to charges injected from each transistor are applied to the input terminal of the operational amplifier in phase, and no DC offset occurs.

Since the feed through charge generated by the parasitic capacitance of other transistors does not affect the offset, the DC offset voltage generated in this circuit is all canceled in the above manner.

Figure 2 is a circuit diagram of a second embodiment of the present invention.

The same symbols are used for elements having the same functions as in the first embodiment. In this circuit, the number of transistor elements can be reduced by connecting it to an operational amplifier.

〔Effect of the invention〕

As explained above, the present invention provides a switched capacitor circuit with an integral capacitor connected between the input and output terminals of an operational amplifier, and a capacitor of the same size as the transistor that shorts between the input and output terminals of the operational amplifier in the reset mode. and a transistor are connected in parallel between the non-inverting input terminal of the operational amplifier and the ground, and a transistor of the same size as the transistor connected to the input capacitor t and the inverting input terminal of the operational amplifier is shorted between the source and drain to form an operational amplifier. By connecting to the non-inverting input terminal of
This has the effect of canceling the DC offset caused by clock feedthrough that occurs in each transistor.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a first embodiment of the present invention, Fig. 2 is a circuit diagram of a second embodiment of the invention, Fig. 3 is a circuit diagram showing a first conventional example, and Fig. 4 is a circuit diagram of a first embodiment of the present invention. FIG. 5, a circuit diagram showing the second conventional example, is a time chart of clock signals for driving each MOS transistor. Ml to M9...N-type MOS transistor, CI
. C2, C3... Capacitor, A... Operational amplifier, ψ1゜ψ2... Clock signal, VI
N...Input voltage, Voyr...Output voltage. Agent: Patent Attorney Uchihara Otonoka Ichido / Figure 3

Claims (1)

[Claims] a first capacitor connected between an input terminal and ground for a first phase signal, and connected to ground and an inverting input of an operational amplifier with the polarity inverted from that of the first phase signal for a second phase signal; a second capacitor connected between the inverting input terminal of the operational amplifier and ground with the first phase signal and between the inverting input terminal and the output terminal of the operational amplifier with the second phase signal; a first phase signal with a first terminal connected to ground and a non-inverting input terminal of the operational amplifier;
a third capacitor having a second terminal connected to ground, wherein the first terminal is connected to the non-inverting input terminal of the operational amplifier and the second terminal is connected to ground; , a MOS transistor whose source and drain are shorted and connected to the non-inverting input terminal of the operational amplifier, and whose gate is connected to the second MOS transistor; a MOS transistor to which an on-level voltage is applied in the phase signal;
and a MOS transistor that connects the first, second, and third capacitors at the time of first and second phase signals.