JPS6152514B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrating circuit suitable for MOS and LSI.

Figure 1 shows an example of a conventional integration circuit applied to MOS and LSI. In the figure, an analog signal V _IN is input from an input terminal 1 and is sampled by turning on a switch 11 to charge a sampling capacitor 13 . Next, by turning off the switch 11 and turning on the switch 12, the charge charged in the capacitor 13 is integrated by the integrating capacitor 14 and the operational amplifier 15. At this time, the output voltage Vout of the terminal 3 is expressed as Vout=Cs/CpV _IN , where the sampling capacitor 13 is Cs and the integrating capacitor 14 is Cp. However, the switches 11 and 12 implemented by MOS transistors have stray capacitances consisting of junction capacitance and channel capacitance, and charges accumulated in these stray capacitances are also integrated at the same time. In other words, if the stray capacitance is CΔ, the output voltage is Vout
=Cs+CΔ/CPV _IN . Therefore, in the past, the sampling capacitance Cs was estimated to be smaller by the stray capacitance CΔ. However, the stray capacitance CΔ has voltage dependence, and when estimated using the sampling capacitance Cs, there is a drawback that an integrated output with small input voltage dependence cannot be obtained. Additionally, there was a design difficulty in that the influence of estimation errors on stray capacitance CΔ was large.

In order to eliminate these drawbacks, the present invention charges the stray capacitance of a switch at a node different from the sampling capacitor with the same amount of charge as the charge accumulated in the stray capacitance, thereby removing the charge accumulated in the stray capacitance. The system is designed to correct the amount integrated by the integrator, and the drawings will be described in detail below.

FIG. 2 shows an embodiment of the present invention, in which 1 is an analog signal input terminal, 2 is a node connected to a sample capacitor, 3 is an output terminal, 4, 5, 7, and 8 are clock terminals for driving switches, 6 is switch 16,17
Nodes 11, 12, 16, and 17 are analog switches, 13 is a sampling capacitor, 14 is an integrating capacitor, and 15 is an operational amplifier. Here, a case is shown in which N-MOS is used as the switches 11, 12, 16, and 17, but P-MOS and C-MOS can be constructed in the same manner.

FIG. 3 shows a time chart of the clocks applied to the switch driving clock terminals 4, 5, 7, and 8 of FIG. First, when the switch 11 is turned on, charge is accumulated in the sample capacitor 13 and the stray capacitances on the node 2 side generated by the switches 11, 12, and 16 in accordance with the input voltage V _IN of the input terminal 1. The charge currently stored in the sample capacitor 13 is
Q ₁₃ , and the charges accumulated in the stray capacitances on the node 2 side generated by switches 11, 12, and 16 are assumed to be Q ₁₁ , Q ₁₂ , and Q ₁₆ , respectively. Next, when switch 11 is turned off and switch 16 is turned on, the charges are redistributed, and a portion of the charges accumulated in node 2 is charged to node 6. The charge charged in this node 6 is Q' ₁₇ , and due to charge redistribution, Q _{13, Q 11} , Q _{12 , and Q 16 become Q' 13 , Q 12} , and Q ₁₆ , respectively.
Suppose that they change to Q′ ₁₁ , Q′ ₁₂ , and Q′ ₁₆ . Here, change the switch size of switch 17 to switch 11 and 1.
2, the stray capacitance caused by switch 17 will be equal to the stray capacitance caused by switches 11 and 12. Therefore, the charge on node 6
Q' ₁₇ is approximately the switch 11, 12 after charge redistribution.
The stray capacitance charges Q′ ₁₁ and Q′ ₁₂ generated in the switch 1
Q′ ₁₇ ≈Q′ ₁₁ +Q′ ₁₂ +Q′ _{16 .} Here, if the stray capacitance is sufficiently small with respect to the sample capacitance, that is, if the potential drop due to charge redistribution caused by charging of node 6 is small, then Q' ₁₇ ≒ Q ₁₁ + Q ₁₂ + Q ₁₆ , and node 2's This means that an amount of charge equal to the charge accumulated in the stray capacitance is discharged (charged) to the node 6 side. next,
The switch 16 is turned off, the switch 12 is turned on, and the sampled charge is integrated by the integrating capacitor 14 and the operational amplifier 15. In this case, the input voltage V
Regardless of IN, an amount of charge equal to the charge accumulated in the stray capacitance of node 2 is always discharged to node 6, so a voltage of Vout≈Cs/CpV _IN appears at output terminal 3. Also, at this time, switch 17
is turned on to discharge the charge accumulated in node 6.

By adding a correction circuit as shown in FIG. 2, it is possible to construct an integrating circuit with very low dependence on input voltage. Further, since the transistor size of the correction transistor 17 can be given as the sum of the transistor sizes of the switches 11 and 12, the design is very easy and there is little estimation error due to the design.

FIG. 4 shows another embodiment of the invention, in which a switch 18 which is always off is added in parallel to switch 17 of the circuit of FIG. In the case of FIG. 4, the transistor size of the switch 17 is set to the minimum size capable of discharging the charge accumulated in the node 6, and the circuit configuration is such that the remaining stray capacitance is compensated for by the switch 18, which is always in an off state.

As explained above, according to the present invention, a highly accurate integrating circuit with small input voltage dependence can be constructed.
Also, since the design is very easy,
Effective for MOS analog LSI such as capacitors and filters.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional MOS integration circuit, FIG. 2 is a diagram showing an embodiment of a MOS integration circuit according to the present invention, and FIG. 3 is a timing chart of the MOS switch driving clock shown in FIG. The figure shown,
FIG. 4 is a diagram showing another embodiment of the MOS integration circuit according to the present invention. 1... Input signal terminal, 2... Node terminal, 3... Output terminal, 4, 5... Clock input terminal, 6... Node terminal, 7, 8, 9... Clock input terminal, 11, 12
... N-MOS transistor, 13 ... sampling capacitor, 14 ... integral capacitor, 15 ... operational amplifier, 1
6, 17, 18...N-MOS transistor.

Claims (1)

[Claims] 1 an integrator, a first switch that samples an input analog signal, and a sampling capacitor that is charged by the sampled analog signal;
and a second switch that supplies the charge stored in the sampling capacitor to the integrator, in which a part of the charge of the sampled analog signal is transferred between the sampling capacitor and the first and second switches. An integrating circuit comprising: a third switch that charges the stray capacitance of a switch at a node different from the connection node of the switch; and a fourth switch that stores or discharges the charged charge.