JPH04285797A - Sample-and-hold circuit - Google Patents

Abstract

PURPOSE:To provide a sample-and-hold circuit which has a fewer number of circuit elements and a lower current consumption. CONSTITUTION:A capacitor 3 is connected to a signal line 15 through an analog switch 1, a condensor 4 is connected to the capacitor 3, through the analog switch, which consists of a single P channel MOS transistor 14. BY a control signal R, a transfer 7 is turned on, the capacitor 4 is discharged and the input voltage of an operational amplifier 5 and the output voltage of a buffer 6 become a ground level. Next, the analog switch 1 is turned on by a control signal S1 and the capacitor 3 is charged up by the voltage of the signal line 15. The charge of the capacitor 3 is shifted to the capacitor 4 when the MOS transistor 14 is turned on by a control signal S2. The terminal voltage of the capacitor 4 is amplified by the operational amplifier 5 and outputted from an output terminal 16 through the buffer 6.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit used in active matrix liquid crystal display devices and the like.

0002

2. Description of the Related Art An example of a conventional sample and hold circuit is shown in FIG. In the figure, an analog input signal Y such as a video signal to be sampled is input from an input signal line 15. The capacitors 3 and 4 (including the stray capacitance of the circuit) are used to hold the voltage of the analog input signal Y from the signal input line 15, and both ends are connected to ground. The other end of the capacitor 3 is connected to the signal input line 15 via the analog switch 1, and the other end of the capacitor 4 is connected to the other end of the capacitor 3 via the analog switch 2.

[0003]A control signal S1 is applied to the analog switches 1 and 2.
, S2 are respectively input, and each analog switch is turned on when the control signal is at a low level, and is in a conductive state. The output terminal 5c of the operational amplifier 5 is connected to the input terminal 6a of the buffer 6, and the output terminal 6b of the buffer 6 is connected to the inverting input terminal 5b of the operational amplifier 5. The non-inverting input terminal 5a of the operational amplifier 5 is connected to the other end of the capacitor 4,
Further, the output terminals 6b of the buffer 6 are respectively connected to the output terminals 16 of the sample and hold circuit.

The MOS transistor 7 is for discharging the charge accumulated in the capacitor 4, and is connected between the ground and the non-inverting input terminal 5a of the operational amplifier 5. A control signal R is input to the gate of the transistor 7. Further, the MOS transistor 8 is used to short-circuit the output of the buffer 6 to the ground at a predetermined timing, and is connected between the output terminal 6b of the buffer 6 and the ground. Further, a control signal R is also input to the gate of the transistor 8.

The analog switch 2 has a circuit configuration as shown in FIG. That is, N channel MOS
Transistor 11 and P-channel MOS transistor 1
2 are connected in parallel, the control signal S2 is directly input to the gate of the transistor 12, and the control signal S2 is input to the gate of the transistor 11 via the inverter 13.

The sample and hold circuit configured in this manner has control signals R, R, and R as shown in the timing chart of FIG.
S1 and S2 are given, and the operation is as follows. That is, when a high level control signal R is applied, the transistor 7 is turned on, and as a result, the charge accumulated in the capacitor 4 is discharged, and the input voltage of the operational amplifier 5 becomes the ground level. At the same time, the transistor 8 is also turned on, and the output voltage of the buffer 6 also becomes the ground level.

[0007] At timing T1, the control signal S is at a low level.
When 1 is given, the analog switch 1 is turned on and the signal Y is applied to the capacitor 3, so that the capacitor 3 is charged. Thereafter, when the signal S1 becomes high level and the analog switch 1 is turned off, the capacitor 3 holds the voltage D1 of the signal Y just before that. Next, when the control signal S2 becomes low level at timing T2, the analog switch 2 is turned on and the charge accumulated in the capacitor 3 is transferred to the capacitor 4.
Move to. The voltage of the capacitors 3 and 4 becomes a voltage D1' determined by the ratio of their capacitances. This voltage D1' is output from the output terminal 16 via the operational amplifier 5 and the buffer 6. After that, the signal S2 changes to high level, and even if the analog switch 2 is turned off, the capacitor 4 remains at the voltage D1.
' is maintained, so a constant voltage is maintained at the output terminal 16.

Next, when the high level control signal R is applied again, the transistors 7 and 8 are turned on, the charge in the capacitor 4 is discharged, and the output of the buffer 6 is short-circuited to ground. As a result, the voltage at the output terminal 16 becomes the ground level. Thereafter, the circuit repeats the above-described operation, samples the voltages D2, D3, D4, . . . of the signal Y, and sequentially outputs the voltages D2', D3', D4', .

[0009]

[Problem to be Solved by the Invention] The potential of the capacitor 4 is kept at the ground level after the high level control signal R is applied and becomes the ground level until the signal voltage is supplied to the operational amplifier again. Therefore, the analog switch 2 only needs to function to transfer the charge in the direction from the capacitor 3 to the operational amplifier 5. In the conventional sample-and-hold circuit described above, the analog switch 2 is formed of an N-channel MOS transistor 11, a P-channel MOS transistor 12, and an inverter 13.
It is possible to perform the above functions with only one. That is, N
Channel MOS transistor 11 and inverter 13
is an unnecessary circuit element.

The present invention has been made with this point in mind, and an object of the present invention is to provide a sample-and-hold circuit that has fewer circuit elements and consumes less current than conventional circuits.

[0011]

[Means for Solving the Problems] The object of the present invention is to provide a first capacitor connected to an input signal line via a first analog switch in order to extract an input signal at a predetermined period; a second capacitor connected to the first capacitor via a second analog switch to hold an input signal; and an amplifier circuit that amplifies and outputs the input signal held in the second capacitor. and the second analog switch is achieved by a sample and hold circuit characterized in that it is formed from a single transistor.

0012

[Operation] The input signal is applied to the first capacitor via the first analog switch that is turned on when a predetermined control signal is applied, and the first capacitor has a charge corresponding to the voltage of the input signal. is accumulated. This charge is transferred to the second capacitor via a second analog switch that is turned on when a predetermined control signal is applied. The terminal voltage of the second capacitor is supplied to the amplifier circuit, amplified, and output to the outside. The second analog switch is preferably formed from a single P-channel MOS transistor.

[0013]

EXAMPLES Next, examples of the present invention will be described in detail. Figure 1
1 is a circuit diagram of an embodiment of a sample and hold circuit of the present invention. This circuit differs from the conventional sample-and-hold circuit shown in FIG. 2 in that the analog switch connecting capacitor 3 and capacitor 4 is composed of only a single P-channel MOS transistor 14. That is, in the circuit of FIG. 1, the terminals of the capacitors 3 and 4 that are not connected to the ground are connected to each other via the transistor 14, and the control signal S2 is input to the gate of the transistor 14.

The other parts of this sample and hold circuit are the same as the circuit of FIG. That is, in FIG. 1, an analog input signal Y such as a video signal to be sampled is input from the input signal line 15. One end of each of the capacitors 3 and 4 (including the stray capacitance of the circuit) is connected to ground. The other end of the capacitor 3 is connected to the signal input line 15 via the analog switch 1, and the other end of the capacitor 4 is connected to the other end of the capacitor 3 via the analog switch 2.

Control signals S1 and S2 are input to the analog switch 1 and the MOS transistor 14, respectively, and when the control signals are at a low level, each turns on and becomes conductive. The output terminal 5c of the operational amplifier 5 is connected to the input terminal 6a of the buffer 6, and the output terminal 6b of the buffer 6 is connected to the inverting input terminal 5b of the operational amplifier 5. The non-inverting input terminal 5a of the operational amplifier 5 is connected to the other end of the capacitor 4, and the output terminal 6b of the buffer 6 is connected to the output terminal 16 of the sample and hold circuit.

A MOS transistor 7 for discharging the charge accumulated in the capacitor 4 is connected between the ground and the non-inverting input terminal 5a of the operational amplifier 5, and a control signal R is applied to the gate of the transistor 7. It has been entered. Further, a MOS transistor 8 for shorting the output of the buffer 6 to ground at a predetermined timing is connected between the output terminal 6b of the buffer 6 and the ground.

Next, the operation of the above circuit will be explained using the timing chart of FIG. First, when a high-level control signal R is applied, the transistor 7 is turned on, and as a result, the charge accumulated in the capacitor 4 is discharged, and the input voltage of the operational amplifier 5 becomes the ground level. At the same time, the transistor 8 is also turned on, and the output voltage of the buffer 6 also becomes the ground level.

At timing T1, the control signal S is at a low level.
When 1 is given, the analog switch 1 is turned on and the signal Y is applied to the capacitor 3, so that the capacitor 3 is charged. Thereafter, when the signal S1 becomes high level and the analog switch 1 is turned off, the capacitor 3 holds the voltage D1 of the signal Y just before that. Next, when the control signal S2 becomes low level at timing T2, the transistor 14 is turned on, the charge accumulated in the capacitor 3 is transferred to the capacitor 4, and the voltage of the capacitors 3 and 4 is determined by the ratio of their capacitances. It becomes D1'. This voltage D1' is output from the output terminal 16 via the operational amplifier 5 and the buffer 6. After that, the signal S2 changes to high level, and even though the transistor 14 is turned off, the capacitor 4 remains at the voltage D1'.
Therefore, a constant voltage is maintained at the output terminal 16.

Next, when the high-level control signal R is applied again, the transistors 7 and 8 are turned on in the same manner as described above, the charge in the capacitor 4 is discharged, and the output of the buffer 6 is short-circuited to ground. As a result, the voltage at the output terminal 16 becomes the ground level. Thereafter, the circuit repeats the above-described operation, samples the voltages D2, D3, D4, . . . of the signal Y, and sequentially outputs the voltages D2', D3', D4', .

As described above, in the sample hold circuit of this embodiment, the analog switch connecting capacitor 3 and capacitor 4 is composed of a single P-channel MOS transistor, so the number of circuit elements is reduced and the circuit simplification is achieved.

[0021]

Effects of the Invention As explained above, the sample and hold circuit of the present invention has an analog switch that connects two capacitors for extracting and holding a signal voltage and is composed of a single transistor. Compared to a hold circuit, the number of circuit elements is smaller and current consumption is reduced. Furthermore, when the sample and hold circuit is formed as an integrated circuit, its chip area can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of a sample and hold circuit of the present invention.

FIG. 2 is a circuit diagram showing the configuration of a conventional sample and hold circuit.

FIG. 3 is a circuit diagram showing the configuration of an analog switch of the sample and hold circuit in FIG. 2;

FIG. 4 is a timing chart for explaining the operation of the sample and hold circuit of FIGS. 1 and 2;

[Explanation of symbols]

1, 2 Analog switch 3, 4 Capacitor 5 Operational amplifier 6 Buffer 7, 8, 14 MOS transistor 15 Input signal line 16 Output terminal

Claims (1)

[Claims] 1. A first capacitor connected to an input signal line via a first analog switch to extract an input signal at a predetermined period, and a second analog switch to hold the extracted input signal. The second analog switch includes a second capacitor connected to the first capacitor via a second capacitor, and an amplifier circuit that amplifies and outputs the input signal held in the second capacitor. A sample and hold circuit characterized by being formed from a single transistor.