JPS59149417A - Clock generator - Google Patents

Abstract

PURPOSE:To generate mutually opposite-phase clock signals almost without delay by specifying the amount of delay of a signal at inverters. CONSTITUTION:Inverters 4, 8, and 9 are so formed that the delay amount of the signal at the inverter 4 which generates a clock signal out of phase with a clock signal phi1 is equal to those of inverters 8 and 9 which generate the clock signals phi1. Further, inverters 7, 10, and 11 are so formed that the delay amount of the signal of the inverter 7 which generates a clock signal out of phase with a clock signal phi2 is equal to those of the inverters 10 and 11 which generate the clock signal phi2. Consequently, mutually oppsite-phase clock signals are generated almost without delay.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock generator, and more particularly to a clock generator suitable for a switched capacitor filter.

In recent years, switched capacitor filters, which can be integrated into MO8 integrated circuits, have come into use by replacing the resistive elements in active filters with analog switches and capacitors. .

In such a switched capacitor filter, MO8FnT (insulated gate field effect transistor) is used as an analog switch. However, if only one of the p-channel type or n-channel type M 08 I''E '1'' is used as an analog switch, the switch will not work properly due to the relationship between the power supply voltage and signal level and the relationship with the substrate effect. There is a risk that the signal will not be transmitted because it is not turned on.

In addition, when a fast-changing signal is supplied to the gate of a MOSFET, the change in the gate input signal is transmitted to the signal line via the capacitance between the gate and the source or drain, causing noise. It is known that a through phenomenon occurs.

Therefore, in general, a pair of p-channel type and n-channel type MOSFEs arranged in parallel on the signal line are used as analog switches for switched capacitor filters.
A CMOS analog switch consisting of T is used. Clock signals φ and φ having mutually opposite phases are supplied to the gates of each of the p-MOSFET and n'-MOSFET constituting this CMOS analog switch to turn them on and off simultaneously. This ensures signal transmission. Also, p-MOSFET and n-MO8
Since the noise generated by the feedthrough at Fh;T is positive and negative, respectively, they cancel each other out. As a result, the effects of feedthrough were offset.

FIG. 1 shows a pair of clock signals φ1. A conventional example of a clock generator for generating φ1 is shown below. Note that the switched capacitor filter is provided with a pair of CMOS analog switches that are turned on and off alternately in order to switch the connection of one terminal for each terminal of the capacitor. Therefore, the clock generator of FIG. 1 uses the clock signal φ1. In addition to φl, clock signals φ2 . φ2 is generated.

However, in the clock generator of FIG. 1, the clock signal F(d)l is provided in the final stage to form clock signals (φl and φ2) of opposite phases. and φ2 have a slight delay T with respect to φl and φ2, as shown in FIG. Therefore, the p-MOSFET and n-MOSFET that constitute the CMOS analog switch
T (D, t 7, off, (7) The timing is shifted and the noise due to feedthrough cannot be completely canceled out. As a result, the problem is that the gain of the switched capacitor e-filter is fluctuated. I was disappointed.

Therefore, the present invention can generate clock signals having opposite phases to each other to be supplied to CMOS analog switches with almost no delay between them. The purpose is to reduce the gain variation of switched capacitor filters.

Specifically, it is an object of the present invention to make it possible to reduce gain fluctuations of a filter due to fluctuations in process fluctuations, power supply, temperature, etc.

The present invention will be explained below using the drawings.

FIG. 3 shows an embodiment of a clock generator according to the present invention.

In the figure, 1 is an inverter that inverts a clock CLK of an appropriate period, and 2 is an NAND circuit that uses the clock CLK as one input signal. The output of NAND circuit 2 is inverted by inverter 3 and further inverted by inverter 4, thereby forming clock signal φl. Further, in this embodiment, the output of the inverter 3 is inverted by the inverter 8, and further inverted by the inverter 9, so that the clock signal φ1
is formed.

5 is an NA whose input signals are the clock CLK inverted by the inverter 1 and the output signal φ1 of the inverter 4.
Ruru with ND circuit. The output of NAND circuit 5 is inverted by inverter 6 and further inverted by an inverter, thereby forming clock signal φ2.

Further, the output of the inverter 6 is inverted by an inverter 10, and further inverted by an inverter 11, thereby generating a clock signal φ2.

The output signal φ2 of the inverter is the NAND circuit 2.
is supplied to the other input terminal of As a result, clock signals φ1 and φ2 whose high level periods do not overlap with each other, and signals φ1 and φ2 having opposite phases thereto are formed.

In this embodiment, the amount of signal delay in the inverter 4 that forms the clock signal φ1 is
The MO8IT forming the inverters 4, 8 and 9 is formed so as to be equal to the signal delay amount in the inverters 8 and 9 for forming the inverter 1.

Similarly, inverters 7 and 10, 11' M 081'' JJ T is formed.

Specifically, the dimensions of the MOSFETs forming inverters 8, 9 and 1o, 11 are larger than those of the MOSFETs forming inverters 4 and 7! <L-r, just make the signal speeds match.

As a result, the clock signals φ1 and φ2 become completely opposite phase signals of the clock signals φ1 and φ2, respectively, and the delay T is made almost zero.

Furthermore, in this case, in particular, the dimensions of MO8FgT constituting inverters 8 and 10 are increased so that inverters 8 and 1
Preferable results can be obtained by increasing the operating speed of 0 and by forming inverters 9 and 11 to have the same element dimensions as inverters 4 and 7 as much as possible.

In other words, if the rise time tr and fall time tf of the clock signals φ1 (φ2) and v1 (72) differ, the amount of feedthrough will change even if the delay T is zero.
In the end, there is a possibility that noise will be added to the signal line. However, if the final stage inverters 4 and 9 (7 and 11) that form the signals φ1 (φ2) and φl (φ2) have the same configuration, their driving capabilities will be the same, so the rising edge of the signals φ1 and ii will be the same. The time t' and the fall time tf are made equal.As a result, the feedthroughs completely cancel each other out,
The gain fluctuations of the swissotide capacitor filters operated by these signals φ1*(1'l and φ2*d2 are reduced. Also, the inverters 4 and 9 and 7 and 1
1 have substantially the same configuration, process variations, power supply, and temperature fluctuations will have the same effect on the MOSFETs forming inverters 4 and 9 and 7 and 11. Therefore, the amount of signal delay due to these fluctuation factors is minimized, and the gain fluctuation of the switched capacitor filter due to feedthrough is reduced.

Moreover, by appropriately designing the characteristics of the final stage inverter, the clock signal φl and φ1 or φ2
Since it is possible to set the rate of change (rise and fall slopes) of 755 and 72 to a specific value, the design of the switched capacitor filter becomes easy. In other words, since the rate of signal change is known in advance, the amount of variation from the desired gain of the designed filter (the deviation between the gain determined from the transfer function and the actual filter gain) can be known in advance.

Therefore, the design of the filter becomes easy.

FIG. 4 shows the clock signal φ1. generated by the clock generator. φ1 and φ2. This is an example of an integrator constituting a switched cano filter that operates in response to the supply of φ2.

, this integrator has analog switches 8a1, Sa2
- Consists of a switched capacitor 21 consisting of 8b, Sb2 and a capacitor Cs, an operational amplifier 22, and an integrating capacitor 23.

Analog switch Sal forming switched capacitor 21, 8a2. sbl and sb each consist of a CMOS analog switch in which a p-MO8F'ET and an n-MOSFET are connected in parallel. The analog switch 8al and S
a2 is arranged. Further, the analog switches Sb2 and Sb1 are connected between the other terminal of the capacitor Cs and the inverting input terminal 22a of the operating switch 1220 and the ground point.
are arranged respectively.

The analog switches 8a1 and sb,1 receive a clock signal φ supplied from the clock generator.
1. The analog switches 8a2 and Sb2 are simultaneously turned on and off by the clock signal φ2. φ2
is turned on and off at the same time.

When the clock signal φl is set to high level and φ1 is set to low level, switches Sal and Sb1 are turned on, one terminal of the capacitor Cs is connected to the input terminal 24, and the other terminal is connected to the ground. Therefore, capacitor C
A charge proportional to the input voltage Vin is accumulated in s. Next, when the clock signal φl changes to low level and φ1 changes to high level, switches Sa1 and Sb1 are turned off.

Subsequently, when the clock signal φ2 changes to high level and φ2 changes to low level, the terminal connected to the input terminal 24 of the capacitor Cs is connected to the ground, and the terminal connected to the ground is connected to the operational amplifier 220. It is connected to the input terminal 22a. However, since the non-inverting input terminal 22b of the operational amplifier 22 is always connected to the ground, the transition of the inverting input terminal 22a is also brought to the ground level due to the imaginary short. As a result, the charge proportional to the input voltage Vin stored in the capacitor Cs is transferred to the integrating capacitor 23 with its sign reversed. As a result, the output terminal of the operational amplifier 22 outputs an integral output Vout proportional to the input voltage Vin.

Furthermore, since the high level periods of the clock signals φ1 and φ2 do not overlap, there is no risk that the charge in the capacitor Cs will be released by turning on the analog switch when switching the signals.

In the clock generator of the embodiment (FIG. 3), the clock signal j1 is generated by one stage of inverter 4 based on the output signal of inverter 3. Two stages of inverters may be connected, and the chronograph signal φ1 may be formed by three stages of inverters. In this case, the final stage inverter on the inverter 4 side is made to have exactly the same configuration as the final inverter 9 that forms the ripple signal φ1, and the amount of signal delay in the inverter 8 and the amount of signal delay in the inverter 4 and the inverter in the next stage. I will configure it so that it matches. In this way, the final stage inverter can have the same configuration and drive capacity.

As a result, the feet φ- can be completely canceled out, and the gain fluctuation of the swissotide capacitor filter can be minimized.

Furthermore, the gain fluctuations of the filter due to process variations, power supply and temperature fluctuations are also minimized.

[Brief explanation of the drawing]

Fig. 1 is a circuit configuration diagram showing an example of a conventional lock generator for a suinotide capacitor filter, Fig. 2 is a timing chart of a clock signal generated by the clock generator, and Fig. 3 is a diagram illustrating a clock signal according to the present invention. FIG. 4 is a circuit diagram showing an embodiment of such a clock generator, and FIG. be. 4.7, 8.11... Inverter, 21... Switched capacitor, φ1eat, φ2,1□10. Quack signal, Sal, Sa2. SJ, Sb2
・CMOS analog switch. Agent Patent Attorney Akio Takahashi - Figure 1 Figure 2 Figure 3 Figure 4 (-1--□□-1--□---)

Claims (1)

[Claims] 1. In a clock generator in which the final stage is constituted by an inverter and is configured to form a set of clock signals having opposite phases to each other based on the same clock, the first clock signal is formed. The sum of the signal delay times in one or more inverter circuit strings to form a second clock signal having an opposite phase to the second clock signal is A clock generator characterized in that each inverter is configured to have the same sum as the sum. 2. A patent claim characterized in that the final stage inverter that forms the first clock signal and the final stage inverter that forms the second clock signal are constituted by MO8 transistors having substantially the same dimensions and characteristics. The clock generator according to item 1.