JP3156323B2 - Oscillator circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation circuit utilizing a hysteresis characteristic of a Schmitt circuit and a charge / discharge characteristic of a CR time constant circuit.

[0002]

2. Description of the Related Art Conventionally, an oscillation circuit utilizing the hysteresis characteristic of a Schmitt circuit and the charging / discharging characteristic of a CR time constant circuit is described in, for example, a patent pulse circuit technology dictionary p55 published by Ohmsha in 1980, and has a CMOS logic circuit. The configuration of a Schmitt circuit using gates is also described in Patent Pulse Circuit Technical Dictionary p120.

FIG. 4 is a circuit diagram showing a configuration of an oscillation circuit in which a Schmitt circuit is formed using CMOS logic gates. The oscillation circuit includes a Schmitt circuit 10 and a capacitor 14 that is charged by an output voltage of the Schmitt circuit 10 via a resistor 12.
0 indicates the inverter 16 having the threshold value V _L and the threshold value V
_H (V _H > V _L ), and an AND NOR gate 20 receiving the outputs of the inverters 16 and 18
And an inverter 22 for inverting the output of the AND NOR gate 20.

Next, the operation will be described with reference to FIG.

[0005] oscillation period of the circuit is determined by the between thresholds V _H threshold V _L and the inverter 18 in the inverter 16 potential at point C is vertically accordance charge-discharge characteristics of the resistor 12 and capacitor 14. _VL and _VH are inverter 1
The threshold voltages V _L and V _H of the input inverters 16 and 18 are affected by the change of V _th because the threshold voltages V _th of the P-channel and N-channel MOS transistors constituting the transistors 6 and 18 are determined. . If this effect acts to change the value of ( _VH - _VL ), the oscillation cycle will fluctuate.

Generally, the threshold value of a CMOS inverter is given by the following equation.

[0007]

(Equation 1) Now, when it is desired to set the threshold values of the input inverters 16 and 18 to V _L ≠ V _H , the variables W _N and L
_It is common to operate _N , W _P , and L _P. In other words, other variables are fixed to values expected from use conditions, manufacturing conditions, semiconductor characteristics, and the like, and W _N , L _N , W _P , and L _P are adjusted so as to obtain a desired V _T ^* . Therefore, it is assumed that V _thP and V _thN are TYP values expected in manufacturing as shown in equation (2), and the first equation is modified as V _T ^* = V _{H to obtain} equation (3).

V _thN = −V _thP = V _th (2) (K _N / K _P ) ^1/2 = (V _DD −V _H −V _th ) / (V _H −V _th ) (3) _Same as above. If _VT ^* = _VL , then equation (4) results from the transformation of equation (1).

(K _N / K _P ) ^1/2 = (V _DD −V _L −V _th ) / (V _L −V _th ) (4) Here, equations (3) and (4) are used. V _th is the TYP value assumed in the equation (2), and the value itself in the equation is a constant for realizing the ratio between the channel width and the channel length of each inverter. On the other hand, V _thN , V
_thP is the actual threshold voltage of the transistor, requires attention to the point at which the variable of in considering the threshold voltage dependence of V _T ^*. Therefore, when the circuit threshold difference ( _VH - _VL ) _a between the two input inverters in FIG. 4 is determined in consideration of the actual _Vth variation of the transistor, the following equation is obtained.

[0010]

(Equation 2) That is, coefficient threshold difference intended in the design _{(V H -V L) (V} DD - | V thP | + V thN) / (V DD -2V th) the threshold difference during operation multiplied by (V _H - _VL ) _a .

For example, when V _DD is 5 V, V _th is 0.8 V, |
When the variation width between V _thP | and V _thN is ± 0.3 V,
Coefficient (V _DD − | V _thP | + V _thN ) / (V _DD −2V _th )
Takes values as shown in Table 1. As can be seen from Table 1,
Threshold voltage V of P-channel MOS transistor
_{When thP} and the threshold voltage V _thN of the N-channel MOS transistor take TYP values, respectively, the coefficient (V _DD
− | V _thP | + V _thN ) / (V _DD −2V _th ) is 1, and the coefficient is 1 even when the change of | V _thP | is −0.3 V and the change of V _{th N} is +0.3 V. Become.

[0012]

[Table 1] In these cases, the V
The change in _th does not affect the value of (V _H -V _L ),
Therefore, the oscillation frequency of the oscillation circuit shown in FIG. 4 hardly changes. Looking at the details, _VthP and V
_Except when both _thN take the TYP value, _VH and _VL move up and down in a range of ± 0.3 V while maintaining the interval, but _VH and _VL become V _DD or GND level. In addition to the case where the voltage is set to a very close voltage and the case where V _H and _VL are set to the voltage values shown in FIG. 5, for example, there is almost no influence on the oscillation frequency.

[0013]

SUMMARY OF THE INVENTION However, | V _thP |
When the change of V _thN is +0.3 V and the change of V _thN is +0.3 V, as shown in Table 1, the coefficient (V _DD − | V _thP | + V
_thN ) / (V _DD -2V _th ) is 0.824, and |
The change in V _thP | is _-0.3 V and the change in V _thN is -0.
In the case of 3 V, the value of the coefficient is 1.176, which causes a change in the oscillation frequency that is equal to or greater than the rate of change of the coefficient itself, and there is a problem that the oscillation frequency fluctuates.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has as its object to provide an oscillation circuit capable of reducing fluctuations in oscillation frequency.

[0015]

SUMMARY OF THE INVENTION The present invention includes two CMOS inverters each having a different threshold value, and outputs a high-level signal when an input signal becomes smaller than the threshold value of the first CMOS inverter, and outputs a high-level signal when the input signal becomes second. A Schmitt circuit that outputs a low-level signal when the threshold voltage of the CMOS inverter is exceeded, and two CMOs included in the Schmitt circuit
When the difference between the threshold values of the S inverter is small, the threshold value is large, and when the difference is large, the threshold value is small. The threshold value is subtracted from the high-level signal output from the Schmitt circuit. It is characterized by comprising a level switching circuit for adding and outputting, and a capacitor which is charged via a resistor by an output voltage of the level switching circuit and supplies an input voltage to the Schmitt circuit.

[0016]

In the oscillation circuit according to the present invention, a high-level output signal (H) or a low-level output signal (L) is output from the Schmitt circuit according to an input signal. Further, the capacitor is charged by the output of the level switching circuit. 1st C
When the difference between the threshold value of the MOS inverter and the threshold value of the second CMOS inverter fluctuates so as to decrease, the threshold value of the level switching circuit increases, so that the charging of the capacitor becomes slower. Become. As a result, the fluctuation of the oscillation cycle is reduced.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of an oscillation circuit according to one embodiment of the present invention.

The oscillation circuit of the present embodiment is a Schmitt circuit 1
0, a level at which an output signal smaller than the high-level output signal of the Schmitt circuit 10 by the third threshold value and an output signal larger than the low-level output signal of the Schmidt circuit by the third threshold value are output. inverter having an exchange circuit 30 is constituted by a capacitor 14 that is charged via the resistor 12 by the output voltage level exchange circuit 30, Schmitt circuit 10 includes an inverter 16 having a threshold V _L, a threshold V _H 18 and inverters 16 and 18
, And an inverter 22 for inverting the output of the AND NOR gate 20, and an inverter 24 for inverting the output of the inverter 22.

The level switching circuit 30 is a P-channel MOS
Transistors 32 and 34 and N-channel MOS transistors 36 and 38 are provided.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG. In addition, the signal name A in FIG.
B and C correspond to the node names given in FIG.

As described above, when the threshold voltages of the P-channel transistor and the N-channel transistor are a combination that changes the value of (V _H -V _L ), for example, | V _thP | Is +0.3 V and V _thN is +0.
In the case of 3 V, the values of V _H and V _L are V _H ⁺ and V in FIG.
_As shown by _L ⁺ , the amplitude of the waveform C changes so as to decrease. At this time, the amplitude of the waveform B also changes so as to decrease as | V _thP | and V _thN change.

| V _thP | has a difference of -0.3 V from its TYP value and V _thN has a difference of -0.3 V from its TYP value.
In the case of V, the values of V _H and V _L are V _H ⁻ and V _{L in} FIG.
^As shown by-, the amplitude of the waveform C changes so as to increase. At this time, the amplitude of the waveform B also changes so as to increase as | V _thP | and V _thN change.

By the way, the waveform C changes according to the charging / discharging characteristics of the time constant circuit composed of the resistor 12 and the capacitor 14 of the oscillation circuit shown in FIG.
just because repeated charge and discharge portion sandwiched between the V _H and V _L Of xponential curve, a combination of setting the level of the constant and V _H, V _L when the resistor 12 and the capacitor 14 in accordance with the oscillation period by choosing the appropriate operating waveforms in FIG ^C +, C ^- as in (V _H -V
_{Even if} the value of _L ) changes, there is almost no effect on the oscillation cycle.

When an oscillation circuit is used for an integrated circuit,
As shown in FIG. 3, it is common practice to externally connect a resistor 12 and a capacitor 14 using nodes B and C as input and output of the integrated circuit.
Is designed to have a sufficiently low impedance as a charging / discharging power supply for the CR time constant circuit, and may become a radiation source of electromagnetic noise and cause a failure in an external device. However, in the oscillation circuit of the present invention, the waveform shown in FIG. As shown in FIG. B, the amplitude is smaller by about 2 _{Vth than} the operation waveform B (see FIG. 5) of the conventional example. Therefore, the total amount of energy of the electromagnetic noise radiated from the node B is correspondingly reduced, and the radiation noise can be reduced.

[0026]

As described above, according to the oscillation circuit of the present invention, when the threshold difference between the first and second CMOS inverters fluctuates so as to be small, the third threshold is increased to increase the charging curve. In the case where the variation is made gentle and the difference between the first and second thresholds becomes large, the third threshold is made small and the charging curve is made steep, so that the fluctuation of the oscillation cycle can be made small.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an oscillation circuit according to one embodiment of the present invention.

FIG. 2 is a timing chart showing voltages of respective parts of the oscillation circuit according to the embodiment.

FIG. 3 is a diagram showing a configuration when the oscillation circuit according to the present embodiment is used for an integrated circuit.

FIG. 4 is a circuit diagram showing a configuration of a conventional oscillation circuit.

FIG. 5 is a timing chart showing voltages of respective parts of a conventional oscillation circuit.

[Explanation of symbols]

 10 Schmitt circuit 12 resistor 14 capacitor 30 level exchange circuit

Claims (1)

(57) [Claims] 1. A high-level signal is output when an input signal is smaller than a threshold value of a first CMOS inverter, including two CMOS inverters having different threshold values, and is low when an input signal is larger than a threshold value of a second CMOS inverter. A Schmitt circuit that outputs a level signal has a threshold value that increases when a difference between threshold values of two CMOS inverters included in the Schmitt circuit decreases and increases when the difference increases, and is output from the Schmitt circuit. A level switching circuit that subtracts the threshold from the high-level signal and adds the low-level output signal and outputs the added signal; a capacitor that is charged via a resistor by an output voltage of the level switching circuit and provides an input voltage to the Schmitt circuit; An oscillation circuit comprising: