JPH0622318B2 - Pulse delay circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse delay circuit used in a digital circuit device or the like, and more particularly to a pulse delay circuit suitable for varying the delay time.

[Background of the Invention]

A conventional example of the pulse delay circuit is disclosed in Japanese Patent Laid-Open No. 59-50610. In this example, the delay time is variable by one control voltage, and the duty of the output pulse (the ratio of the high level output period or the low level output period to the repetition period) is detected and fed back, so that it is constant. This is effective for delaying an input pulse having a repeating cycle while maintaining its duty strictly, or for shaping the waveform so as to have a desired duty.

However, a voltage comparator is required as a circuit component,
The circuit scale becomes large. In addition, it is difficult to use it for delaying a pulse whose repeating period is not constant.

[Object of the Invention]

The object of the present invention is to provide a pulse having a variable delay time with a single control voltage and a pulse having a constant repetition period, as well as a pulse having a non-constant period, with a simple circuit configuration excluding the above-mentioned drawbacks of the prior art. Another object of the present invention is to provide a pulse delay circuit capable of delaying while maintaining its pulse width (high level output time or low level output period) with high precision even when used for delaying.

[Outline of Invention]

In order to achieve this object, the present invention provides a pulse control circuit that connects a plurality of logic gates in series and that controls the pulse delay time by varying the line resistance of the pulse transmission line from one logic gate to the next logic gate input. In the delay circuit, by using only one of the P-channel MOS transistor and the N-channel MOS transistor as the variable element of the line resistance, the delay time can be varied with a single control voltage, and the MOS transistor is used. Variable resistance is applied to an even number of pulse transmission lines, so that half of these lines control the delay time of the rising phase of the input pulse, and the remaining half of the lines control the delay time of the rising phase of the input pulse. The feature is that the pulse width of the input and output of the delay circuit can be saved by the configuration.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a pulse delay circuit according to the present invention, in which 1 is an input pulse, 2 and 3 are variable output resistance inverters, 4 is an inverter used as a waveform shaping gate, and 5 is delayed. Output pulse, 6 delay voltage control voltage, 21, 31, 41 P-channel MOS transistor (hereinafter abbreviated as P-MOST) which is a constituent element of the inverter, 22, 32, 42 are also constituent elements of the inverter N-channel MOS transistors (hereinafter abbreviated as N-MOSTs) which are elements, 23 and 33 are N-MOSTs for varying the output resistance values of the inverters 2 and 3, and 7 and 8 are inverters 3 and 4.
It is a capacitor arranged at the input part of.

In the figure, MOSTs 21 and 22, 31 and = 32, 41 and 42 form complementary MOS (C-MOS) inverters, respectively.
N-MOST 23, 33 is a voltage 6 applied to the gate terminal.
Since the conduction resistance value of the conductive path can be controlled by the voltage value of, the low level output of the inverter 2 or 3, that is, the N-MOST 22 or 32 is ON (low resistance state, at this time, the P-MOSTs 21 and 31 are OFF, that is, In the high resistance state), the output line resistance value is changed.
As the capacitors 7 and 8, stray capacitances parasitic on the input part of the inverter can be used, and in this case, it is not necessary to add capacitors.

The voltage waveform of each part in FIG. 1 is shown in FIG. In FIG. 2, when the input pulse 1 is at the logical level "0", P
-MOST21 is turned on, N-MOST22 is turned off, and the input terminal of the inverter 3 is connected to the power supply line 10 having a voltage value of the logic level "1" level, so that the input pulse 9 of the inverter 3 is "1". Become a level.

At this time, P-MOST31 turns off and N-MOST32 turns off.
Therefore, the input terminal of the inverter 4 is connected to the "0" level power supply line (ground in FIG. 1) through the N-MOST 33, and the input pulse 11 of the inverter 4 becomes "0" after the level fluctuation transient time described later. "It will be a level. Further, at this time, the P-MOST 41 is turned on and the N-MOST 42 is turned off, and the output pulse 5 becomes "1" level.

Next, when the input pulse 1 changes from "0" level to "1" level, the P-MOST21 is turned off and the N-MOST22 is turned on, and the pulse 9 is a discharge curve determined by the capacitor 7 and the conduction resistance of the N-MOST23. Draw and drop from "1" level to "0" level. When the level of the pulse 9 passes through the threshold level of the inverter 3 (generally, the C-MOS has a voltage level near the center value of the "1" level and the "0" level), the P-MOST 31 is turned on, NM
The OST32 is turned off, and the pulse 11 becomes "1" level. At the same time, the pulse 5 becomes "0" level. By the above operation, the pulse 5 obtained by delaying the rising edge of the pulse 1 (level change portion from the “0” level to the “1” level) by the time t ₁ is obtained.

After that, when the pulse 1 changes from "1" level to "0" level, P-MOST21 is turned on and N-MOST22 is turned on.
When turned off, the pulse 9 immediately changes from the "0" level to the "1" level. At this time, P-MOST31 is OFF, N-MO
ST32 is turned on, pulse 11 is for capacitor 8 and NM
Draw a discharge curve that is determined by the conduction resistance of OST33 and set it to "1".
From the level to the "0" level. When the level of the pulse 11 passes the threshold level of the inverter 4, the pulse 5 changes from the “0” level to the “1” level. By this operation, the falling edge of the pulse 1 (the level changing portion from the “1” level to the “0” level) is output to the pulse 5 with a delay of the time t ₂ . N-MOST23,33 is because it has a conduction resistance decreases characteristics higher the applied voltage 6 of the gate terminal, t ₁ and increased to discharge curve of applied voltage by a steep slope, t ₂ It is possible to perform variable control of the delay time such that t ₁ and t ₂ are increased by decreasing or decreasing the applied voltage to make the slope of the discharge curve gentle.

If MOS transistors manufactured by using the semiconductor manufacturing mask pattern having the same geometrical shape are used as the N-MOSTs 23 and 33, the conduction resistance values thereof are the same when the same control voltage 6 is applied. Are almost the same. Therefore,
If the capacitors 7 and 8 are appropriately set by using an external capacitor or the like, the configuration shown in FIG. 1 allows the single control voltage 6 to be used and the amount of time for which t ₁ and t ₂ are kept the same. Can be controlled.

In addition, in FIG. 1, a configuration is shown in which a polarity reversal pulse of the input pulse is obtained as the output pulse 5 obtained by delaying the input pulse 1. However, an inverter similar to 4 is provided after the inverter 4 (but the capacitor 8 is not necessary) It is also easy to obtain a delayed output pulse having the same polarity as that of the input pulse by adding, or by using a known inverting logic gate instead of the inverter 4.

FIG. 3 shows a configuration example of an output line resistance variable logic gate circuit which can be used in place of the inverters 2 and 3 in FIG.

FIG. 3 shows an inverter composed of P-MOST121 and N-MOST122, which is provided when P-MOST121 is ON (at this time, N
-MOST 122 is OFF) and the output line resistance of P-MOS
It is designed to be variable with T123. With the pulse input terminal 13 and the output terminal 14 and using 2 circuits of the structure of FIG. 3 instead of 2 and 3 of FIG. 1, the common applied voltage 6 is given to the 2 structures and the same as in FIG. It is possible to control the pulse delay time. In this case, in place of the discharge curves of the pulses 9 and 11 in FIG. 2, change the charging curve (transient waveform characteristic of the portion where the pulses 9 and 11 change from "0" level to "1" level). Controls the delay time. Further, since the P-MOST123 has a characteristic that its conduction resistance value becomes lower as the voltage applied to the gate terminal becomes lower,
The delay time is controlled such that the lower the applied voltage 6 is, the shorter the delay time is.

As explained above, P-MOS transistor or N-M
The delay time can be controlled with one control voltage by using only one of the OS transistors as the line resistance control element. However, in this case, in the line resistance control of one output line, only the delay control of one pulse edge of the input pulse is effectively executed,
Since the delay control of the other pulse edge is not possible, in the above-mentioned embodiment, the line resistance control is performed at two points of the output line, and one line resistance is possible and the rising edge of the input pulse is made to fall by changing the other line resistance. It is configured to delay-control the edge so that pulse delay can be performed while preserving the pulse width of the input pulse.

FIG. 4 is a circuit diagram showing another embodiment of the pulse delay circuit according to the present invention, in which 18 and 19 are logic gates with variable output line resistance, as shown in FIGS. 2 and 3 of FIG. It is a circuit block diagram.

The difference between this embodiment and the embodiment shown in FIG. 1 is that a non-inverting gate 20 is inserted between the output line resistance variable logic gates 18 and 19. FIG. 5 shows operation waveforms when the logic gates 18 and 19 of FIGS. By inserting the non-inverting gate 20, the pulse 9 ', which is a waveform-shaped pulse 9, is input to the output line resistance variable logic gate 19 in the second stage. Other operations are shown in FIG. And the rising edge of the input pulse 1 at the output line resistance variable logic gate 18 is
At 19, the falling edge is controlled for delay time.

The configuration shown in FIG. 4 is particularly suitable when the circuit of the present invention is integrated in an LSI having a C-MOS structure. The reason for this will be described below.

The circuit diagram of the non-inverting gate 20 of FIG.
Shown in the figure. 201 and 203 are P-MOST, 202 and 204 are N-MO
ST, which is configured by connecting inverters in series.

Here, if the input section of the non-inverting gate, that is, the inverter section composed of the P-MOST 201 and N-MOST 202 is designed to have the same geometrical shape as the inverter of FIG. 1 or FIG. Since the input stray capacitance of the non-inverting gate 20 and the input stray capacitance of the inverter 4 shown in FIG. 4 can be made to have substantially the same capacitance value, a capacitor is connected outside the LSI to adjust the capacitance value. It is possible to realize a pulse delay in which the pulse width of the input pulse is accurately maintained without the need for the above.

FIG. 7 is a circuit diagram showing still another embodiment of the pulse delay circuit of the present invention, in which 71 and 72 are voltage comparison amplifiers, 73 and 74 are reference voltages, 75 and 76 are P-MOSTs, and 77 and 78. Is a diode.

In FIG. 7, as the voltage comparison amplifiers 71 and 72, commercially available bipolar transistors may be used. As is well known, the voltage comparison amplifiers 71 and 72 operate as non-inverting gates by connecting reference voltages 73 and 74 to their negative input terminals and applying an input pulse to their positive input terminals. Voltage comparison amplifier 71, P-MOST75,
The line resistance variable logic gate of the first stage in which the line resistance at the time of "1" level output is variable by the diode 77, the voltage comparison amplifier 7
2, the P-MOST 76, and the diode 78 constitute a second-stage line resistance variable logic gate in which the line resistance at the time of "1" level output is variable.

FIG. 8 shows the operation waveform of each part of the embodiment shown in FIG.
The voltage comparator amplifier outputs a pulse having the same polarity as the input pulse 1, but since the conduction resistance of the P-MOST75 is inserted in the output line only when the "1" level is output, this resistance and the stray capacitance of the input section of the inverter 4 '. Due to the integration characteristics of and, the input terminal pulse 79 of the inverter 4'has a waveform with a blunt rising portion as shown in FIG. This delay of the rising edge of the inverter 4 'is output pulse 80 to the waveform shaping obtained at the input pulse 1 (time t ₁₎ is realized.

Similarly, the input terminal pulse 81 of the inverter 4 has a waveform obtained by blunting the rising edge of the input pulse 80 of the voltage comparison amplifier 72.
The falling edge delay of the input pulse 1 (time t ₂ ) is realized, and the output pulse 5 has the waveform shown in FIG.

Even in the configuration example of FIG. 7, since only the P-MOST can be used for variable line resistance, delay control can be performed with a single control voltage 6. It should be noted that N-MOST is used instead of P-MOST 75 and 76 as the variable line resistance element,
It is also possible to insert the diodes 77 and 78 in the opposite direction to that shown in FIG. 7, or to use the parallel connection of N-MOST and P-MOST shown in FIG. 3 (b).

The embodiments of FIGS. 1, 4, and 7 described above are examples in which two output line resistance variable logic gates are used, but an even number of output line resistance variable logic gates of 2 or more is used. If it is configured such that the rising edge of the input pulse is delayed by half and the rising edge of the input pulse is delayed by the remaining half, the P-MOS can be used as a variable line resistance element.
Using either T or N-MOST, that is, with a single delay time control voltage, pulse delay control in which pulses are preserved becomes possible.

〔The invention's effect〕

As described above, according to the present invention, when a MOS transistor is used, the output at the time of transmission of one pulse edge of the input pulse on the output line of half of the even number of output lines in which the MOS transistor is inserted. Since the line resistance value is set so that the output line resistance value during transmission of the other pulse edge of the above input pulse is changed in the remaining half of the output lines, the pulse delay is maintained while maintaining the pulse width of the input pulse with high accuracy. Therefore, it is possible to control the pulse delay time by a single control voltage, and it is possible to realize with a simple circuit configuration without using a voltage comparator as an essential component.
It can be realized by a MOS process, is particularly advantageous for integration in a C-MOS structure LSI, and can provide a pulse delay circuit having an excellent function except for the above-mentioned drawbacks of the prior art.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a pulse delay circuit according to the present invention, FIG. 2 is an operation waveform diagram of each part of FIG. 1, and FIG. 3 is an embodiment of an output line resistance variable logic gate different from FIG. An example circuit diagram, FIG. 4 is a block diagram of another embodiment of the pulse delay circuit according to the present invention, FIG. 5 is an operation waveform diagram of each part of FIG. 4,
6 is a circuit diagram of the non-inverting gate of FIG. 4, FIG. 7 is a block diagram of still another embodiment of the pulse delay circuit according to the present invention, and FIG. 8 is an operation waveform diagram of each part of FIG. . 1 …… Input pulse 2,3,18,19 …… Output line resistance variable logic gate 4,4 ′ …… Inverter 5 …… Output pulse 21,31,41 …… P-channel MOS transistor 22,32,42 …… N-channel MOS transistor

Claims (1)

[Claims] 1. At least three logic gates are connected in series, and the first-stage logic gate has the first logic of an input pulse composed of a first logic level and a second logic level. When the application of the level is started, a unidirectional current from the latter to the former flows as a negative current between the logic gate of the first stage and the logic gate of the next stage, and then the logic gate of the next stage and the like one after another. A unidirectional current from the former to the latter flows between the logic gates of the stages as a positive direction current, and thereafter, the current flows in the same manner between the subsequent stages while reversing the current direction. At the output of the logic gate of the first stage, when the application start timing of the first logic level is delayed and the application of the second logic level of the input pulse is started to the logic gate of the first stage, the logic gate of the first stage is started. And the next logic A unidirectional current from the former to the latter flows as a positive current between the former and the latter, and then a unidirectional current from the latter to the former between the logic gate of the next stage and the logic gate of the next stage. The current flows as a negative direction current, and thereafter, between the subsequent stages, the current flows in the same manner while reversing the current direction, so that at the logic gate output of the final stage, the application start timing of the second logic level In a pulse delay circuit configured to obtain a delay and, as a result, to output a delayed output pulse from a logic gate output of a final stage, an N-channel MOS transistor is provided in a path between the even-numbered stages in which the negative direction current flows. Is connected in series, or a P-channel MOS transistor is inserted in series and connected in series in the path between the even number of stages in which the positive current flows, By connecting the gate terminals of all the MOS transistors to a common voltage and controlling the value of the common voltage, among the even-numbered interstage paths in which the MOS transistors are inserted and connected in series, Resistance value control for application start timing delay control of the first logic level of the input pulse is performed on half of the paths, and the remaining half of the paths,
A pulse delay circuit, wherein a delay value of the delayed output pulse is controlled by performing resistance value control for application start timing delay control of the second logic level of the input pulse.