JPH0345577B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is mainly used in an A/D converter etc. that implements a complementary insulated gate configuration on a semiconductor integrated circuit, and compares two voltages with a slight difference, and generates logic according to the magnitude. The present invention relates to a voltage comparison circuit suitable for outputting voltage.

Conventionally, a voltage comparator circuit used in a semiconductor integrated circuit with a complementary insulated gate configuration has been configured with M1 as a constant current source, M2 and M3 as input transistors, and M4 and M5 as current mirror type loads, as shown in Figure 1. A two-stage amplifier circuit that extracts an output voltage from terminal 6 that is proportional to the difference between the voltages applied to terminals 2 and 3 by a differential amplifier circuit, and further amplifies this by an inverting amplifier 11 with M6 as a constant current load. was using.

Symbols used in this application, including FIG. 1, define a p-channel transistor as shown in FIG. 2a, and an n-channel transistor as shown in FIG. 2b. The gate is denoted by G, the source is denoted by S, and the drain is denoted by D. This 2
A staged amplifier circuit usually provides a gain of 2,000 to 5,000 times, but one additional stage of inverting amplifier 12 is usually added to provide extra gain margin. Reference numeral 13 denotes a bias voltage supply device for operating M1 and M6 in a constant current region, which is realized, for example, by the circuit shown in FIG. The circuit shown in FIG. 3 divides the power supply voltage applied between terminals 1 and 9 by connecting three so-called diode-connected transistors in series, in which the gate and drain electrodes of MOS transistors are connected.

When the input voltage difference decreases, such a voltage comparator circuit must increase the number of amplification stages to cope with the decrease.
This results in an increase in the area occupied by the integrated circuit and an increase in power consumption. Furthermore, the common-mode voltage rejection of the first-stage differential amplifier is not perfect, and if the common-mode component of the input voltage changes, the output voltage at node 6 changes, and this voltage is amplified by the inverting amplifier, so the input voltage is several mV.
In the case of the following voltage difference, depending on the common mode voltage, the logic "1" state and the logic "0" state may be switched at the output of the final stage. The same phenomenon also occurs when the power supply voltage fluctuates. Therefore, such a voltage comparison circuit has a drawback that it is impossible to distinguish between differences of several mV or less when the common mode component of the input voltage is large.

The present invention aims to eliminate such drawbacks and realize a voltage comparator circuit with very high sensitivity using a small number of elements.

The present invention provides a differential amplifier having as a load a transistor whose gate electrode and drain electrode are connected to each other with a different polarity from that of the signal input transistor, and two transistors having the same polarity as the load transistor, which are cross-coupled to have a common source electrode. a flip-flop circuit having means for intermittently lowering the voltage to the ground potential of the load transistor; a flip-flop circuit configured using complementary insulated gate transistors, and two drain electrodes of the flip-flop connected to the drain electrodes of the differential amplifier load, respectively; It has the characteristics of connecting,
The voltage comparator circuit is configured to obtain an output voltage sufficient as a logic output at the output end of the differential amplifier in response to the magnitude of the input voltage of the differential amplifier when the potential intermittently decreases.

Hereinafter, the present invention will be described in a fourth section showing an example of a specific circuit.
This will be explained using FIG. 5, which shows an example of the timing of pulses applied to the terminal 17.

What is shown in FIG. 4 is an example of the implementation of the first invention. P-channel transistors are used as signal input transistors M2, M3 and constant current source M11, and the drain electrode of p-channel transistor M1 is similarly connected to the source electrodes of M2 and M3.
The source electrode of M1 is connected to a positive power supply, and the gate electrode of M1 is connected to a bias voltage supply device 1 via node 4.
3 are connected to apply a constant voltage to constitute a constant current source. So-called diode-connected n-channel transistors M13 and M14 are connected as loads to the drain electrodes of M2 and M3, respectively, and these constitute a differential amplifier. The drain electrodes of M13 and M14 are taken out to the outside as output ends 5 and 6, and
The gate electrode of the n-channel transistor M10 and the drain power supply of the n-channel transistor M11 are connected to the output terminal 5, and the drain electrode of M10 and the gate electrode of M11 are connected to the output terminal 6 to form a cross-coupling. and M11
The common source electrode of M12 is connected to the drain electrode of the n-channel transistor M12, the source electrode of M12 is connected to the negative power supply, the source electrode of M12 is connected to the negative power supply, and the gate of M12 is connected to the terminal 17.
It is connected to a device for generating a pulse wave shown in FIG. 5 via a .

A differential amplifier circuit loaded with diode-connected transistors as shown in FIG. This circuit configuration has not been considered in the past in semiconductor integrated circuits with complementary insulated gate configurations because the fact that the removal ratio is also poor is considered to be a drawback.

However, the flip-flop of the present invention, shown in FIG. 4, has an infinite gain because it is subjected to positive feedback, and the common-mode rejection effect is also very large, so the inventor believes that the above-mentioned drawbacks are no longer a problem. This is an idea, and in fact, as a result, as will be described later, we have obtained a great advantage that had not been anticipated in the past: that the return to the differential amplifier after voltage comparison is faster.

The description will now be made starting from the state at time _t0 shown in FIG.

It is assumed that at time _t0 , the pulse I is in a zero state, and the voltage at input terminals 2 and 3 in FIG. 4 is higher than the voltage at input terminal 3. Then, the current flowing through M3 becomes larger than that flowing through M2. Therefore, the voltage at the output end 6 becomes higher than the voltage at the output end 5.

This voltage difference is typically on the order of several to ten times the input voltage difference. At this time, if the difference between the voltages 5 and 6 is smaller than the threshold voltage of the n-channel transistor, the voltage at node 16 will be lower than the voltage at the higher output terminal 6 by the threshold voltage of the n-channel transistor. There is. When this difference becomes larger than the threshold voltage, it becomes equal to the voltage at the output terminal 5, which has the lower voltage among 5 and 6. This is because M10 and M11 each serve as a source follower circuit for the voltages at the output terminals 5 and 6. Next, when the pulse I rises at time _t1 , M12 becomes conductive and the voltage at node 16 drops. Then, the flip-flop composed of M10 and M11 is activated, and M11 becomes conductive first, causing the voltage at the output terminal 6 to drop. As the node 16 falls, the output end 6 falls, so the current flowing through M10 is gradually smaller than the current flowing through M11, so the output end 5 maintains almost the voltage before the pulse I was applied. . Here, in order to make the final voltage on the low voltage side sufficiently lower than the threshold voltage of the n-channel transistor, M10 and M12
It is desirable that the quotient (W/L) obtained by dividing the channel width by the channel length for M4 and M5 is five times or more the value similarly obtained for M4 and M5. In the voltage comparison circuit shown in FIG. 4, the differential amplifier 14 must be a pure differential amplifier or the output terminals 5 and 6 must be at the same potential before applying the pulse I. When the pulse I falls at time _t2 , M12 turns off and no current flows through the flip-flop. Since M14 is off at this time,
All current flowing through M3 is provided for charging.
Even if M14 becomes conductive when the output terminal 5 exceeds the threshold voltage, M14 has a property that its resistance decreases as the voltage at the output terminal 5 rises, so it can be assembled into a differential amplifier in a shorter time than using M14 as a load. can be restored to the state of Even if the input voltages are reversed, the circuit operates in the same way because it is symmetrical.

Now, in the case of such a voltage comparison circuit, not only is it possible to quickly return to a state in which it operates as a differential amplifier after voltage comparison, but there are cases where it is desired to operate at even higher speed. The idea according to the first invention can be further adapted to such cases as well. What is shown in FIG. 6 is an example of the implementation of the second invention thus obtained, which is constructed by connecting the source and drain of the transistor M15 to the output terminals 5 and 6, respectively, in the circuit shown in FIG. Gate terminal 18 of M15
The pulse C shown in FIG. 5 is applied to . As shown in FIG. 5, at the timing of time _t2 , when pulse I falls and pulse C rises to make M15 conductive, the voltages at output terminals 5 and 6 become equal, and the terminals 5 and 6 just before M15 becomes conductive. The voltage is approximately the average voltage. Next, when the pulse V falls, the difference between the currents flowing into terminals 5 and 6 from M2 and M3 is proportional to the difference between the voltages input to terminals 2 and 3, so connect it to the transistor with the lower input voltage. Since the voltage of the output terminal that has been changed increases first, the next voltage comparison can be performed immediately.

[Brief explanation of drawings]

Figure 1 shows a voltage comparison circuit using a conventionally used differential amplifier 10 and inverting amplifiers 11 and 12.
3 is a bias voltage supply device. Figure 2 a, b
is an explanatory diagram of the symbol of a transistor. Third
The figure shows a circuit example of a bias voltage supply device. Fourth
The figure shows an embodiment of the invention as set forth in claim 1, and FIG. 6 shows an embodiment of the invention as set forth in claim 2. 5A, 5B, 5C and 5D are diagrams showing examples of pulse timing and output waveforms supplied to FIGS. 4 and 6. In the figure, MXX indicates a transistor, and only numbers indicate nodes or terminals.

Claims (1)

[Claims] 1. A differential amplifier having as a load a transistor whose gate electrode and drain electrode are connected to each other with a different polarity from that of the input transistor, and a transistor whose polarity is the same as that of the load transistor, and whose common source electrode is cross-coupled. a flip-flop circuit having means for intermittently lowering the voltage to the ground potential of the load transistor; a flip-flop circuit configured using complementary insulated gate transistors, and two drain electrodes of the flip-flop connected to the drain electrodes of the differential amplifier load, respectively; A voltage comparison circuit characterized in that: 2 A differential amplifier having a transistor as a load whose gate electrode and drain electrode are connected to each other with a different polarity from the input transistor, and two transistors having the same polarity as the load transistor are cross-coupled and their common source electrode is connected to the load transistor. a flip-flop circuit having means for intermittently lowering the potential to the ground potential of the differential amplifier load, and comprising complementary insulated gate transistors, two drain electrodes of the flip-flop are connected to the drain electrodes of the differential amplifier load, and A voltage comparator circuit comprising means for forcing the drain potential of the load transistor to be equal to the potential in synchronization with the common source electrode potential of the flip-flop which intermittently decreases.