JPH065092A - Sample-and-hold circuit - Google Patents

Abstract

PURPOSE:To prevent an overshoot and an undershoot in an output signal and to sample and hold a prescribed input signal at high speed in a sample-and-hold circuit. CONSTITUTION:An input signal VIN10 is supplied to input ends, on one side, of a plurality of differential voltage-to-current conversion means 11, 12 in which output current values I1, I2 with reference to the voltage difference between signals VIN10 VOUT10 supplied respectively to one pair of input ends are different from each other; the output signal VOUT10 through a current accumulation means CHD0 is supplied to input terminals on the other side. An added electric current I which has added the output current values I1, I2 of the plurality of differential voltage-to-current conversion means 11, 12 is accumulated by the current accumulation means CHD0 according to the timing of a sample-and-hold pulse PSH. Thereby, it is possible to prevent an overshoot and an undershoot by means of the characteristic difference between the plurality of differential voltage-to- current conversion means 11, 12, and a prescribed input signal can be sampled and held at high speed.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial Application Conventional Technology (FIG. 5) Problem to be Solved by the Invention (FIG. 5) Means for Solving the Problem (FIGS. 1 and 2) Action (FIGS. 1 and 2) Example (FIG. 1) ~ Fig. 4) Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, for example, a solid-state image pickup device (CCD (charge coupled
vice) can be applied to those which sample and hold the video detection signal.

[0003]

2. Description of the Related Art Conventionally, in a television camera device using a CCD, image information collected by a lens forms an image on the CCD, and as a result, an image detection signal obtained from the CCD is C.
Input to a DS (co-related double sampling) circuit. The CDS circuit samples the video detection signal at a predetermined timing and holds the video detection signal to generate a video signal, which is sent to a signal processing circuit in a subsequent stage.

As described above, when the video detection signal is sampled and held to generate the video signal, the hold period is controlled so that the sampling output is held only for a period of 2/3 of the sampling period. There is one that is designed to prevent the deterioration of image quality due to the occurrence of (Japanese Patent Publication No. 61-39784).

The sample and hold circuit 1 in such a case
5 has a general sample and hold configuration as shown in FIG. 5, and the input voltage V _IN that actually corresponds to the video detection signal is input to the voltage-current conversion circuit 2 having a differential amplifier configuration, resulting in the output voltage V _{IN. The} charging current I _CG corresponding to the error voltage between _OUT and the input voltage V _IN is output.

The charging current I _CG is input to the holding capacitor C _HD through the switch circuit 3 and the resistor R0 to be charged while the switch circuit 3 is turned on in response to the sampling pulse P _SH . Further, while the switch circuit 3 is turned off in response to the sampling pulse P _SH , the hold capacitor C _HD is discharged, and thereby the output voltage V _OUT corresponding to the charging current is sent out.

[0007]

By the way, when the sample hold circuit 1 having such a structure is to be used in, for example, a television camera of a high-definition television system, image detection is performed at high speed because the frequency of the horizontal synchronizing signal becomes high. You need to sample and hold the signal.

As described above, in order to increase the speed of the sample and hold circuit, it is essential to increase the charging current. However, if the charging current is increased in this way, the held output voltage V _OUT is overshot or undershot. A short circuit tends to occur, and as a result, there is a problem of weakening against noise.

It is also conceivable to reduce the value of the holding capacitor C _HD without increasing the charging current in this way, but even in this case the held output voltage V _{OUT is held.}
In addition, there is a problem that overshoot and undershoot are likely to occur, and similarly to the above, it becomes weak against noise.

The present invention has been made in consideration of the above points, and provides a sample and hold circuit which can prevent overshoot and undershute in an output signal and can sample and hold a predetermined input signal at high speed. It is a proposal.

[0011]

In order to solve such a problem, in the first invention, a pair of sample and hold circuits 10 for sampling and holding a predetermined input signal V _IN10 at the timing of the sample and hold pulse P _SH are provided. And an input signal V _IN10 is supplied to one of the input ends, and output current values I ₁ and I corresponding to the voltage difference between the signals supplied to the pair of input ends.
_A plurality of differential voltage-current conversion means 11, each of which is different from each other,
12 and the added current I obtained by adding the output currents I ₁ and I ₂ of the plurality of differential voltage-current converters 11 and 12 according to the timing of the sample hold pulse P _SH are accumulated, and the accumulated added current I is held. And outputs it as an output signal V _OUT10 , and at the same time, a plurality of differential voltage-current conversion means 11, 12
The current accumulating means C _HD0 to be supplied to the other input terminal is provided.

In the second aspect of the invention, the input voltage difference V _IN10 -V of the plurality of differential voltage-current conversion means 11 and 12 is changed.
Proportional coefficient g _m1 , g of output currents I ₁ and I _{2 to OUT10
m2} is sequentially selected to be a large value, and maximum output current values I _1max and I _{2max of the} plurality of differential voltage-current conversion means 11 and 12 are _selected.
Was selected in order of smaller value.

[0013]

The output current values I ₁ and I _{corresponding to} the voltage difference between the signals V _IN10 and V _OUT10 supplied to the pair of input terminals, respectively.
_A plurality of differential voltage-current conversion means 11, each of which is different from each other,
12, an input signal V _IN10 is supplied to one input terminal and an output signal V _OUT10 is supplied to the other input terminal through the current accumulating means C _HD0, and a plurality of differential signals are supplied in accordance with the timing of the sample hold pulse P _SH. Voltage-current conversion means 11, 12
The addition current I obtained by adding the output currents I ₁ and I ₂ of the above is stored in the current storage means C _HD0 , so that due to the characteristic difference between the plurality of differential voltage-current conversion means 11 and 12, the _overshoot And undershoot can be prevented in advance to sample and hold a predetermined input signal at high speed.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, reference numeral 10 indicates a sample and hold circuit according to the present invention as a whole, and an input signal V _{IN10, which} is a video detection signal, is input to voltage-current conversion circuits 11 and 12 each having a differential amplifier configuration. The voltage-current conversion circuits 11 and 12 _receive the input signal V _IN10 and the output signal V _IN during the rising period of the sampling pulse P _SH.
The error voltage of _OUT10 is converted into currents I ₁ and I ₂ , respectively.

In practice, the currents I ₁ and I ₂ output from the voltage-current conversion circuits 11 and 12 are added, and the resulting added current I is charged in the holding capacitor C _HD0 through the resistor R1 and the buffer 13 is also added. _Is output as an output signal V _OUT10 . Further, during the predetermined period following the rising period of the sampling pulse P _SH , the added current charged in the holding capacitor C _HD0 is discharged and sent as the output signal V _OUT10 .

In the case of this embodiment, the transconductances g _m1 and g _{m2 of the} voltage-current conversion circuits 11 and 12 and the maximum current values I _1max and I _2max are respectively _expressed by the following equations.

[Equation 1] And the following equation

[Equation 2] It has been selected to have the relationship shown in.

In the above configuration, in the sample hold circuit 10, as shown in FIG. 2, a sampling pulse having a large error between the input signal V _IN10 (FIG. 2 (A)) and the output signal V _OUT10 (FIG. 2 (D)). During the period from time t ₁ immediately after the rise of P _SH (FIG. 2 (B)) to time t ₂ , a large sum of current I (FIG. 2 (C)) is sent out by the first voltage-current conversion circuit 11. The current I ₁ occupies the majority, and the holding capacitor C _HD0 is rapidly charged by the added current I.

Next, the error between the input signal V _IN10 (FIG. 2 (A)) and the output signal V _OUT10 (FIG. 2 (D)) is _calculated by the following equation.

[Equation 3] As shown in, the addition current I for charging decreases during the period from time t ₂ to time t ₃ that becomes gradually smaller, and the following equation is obtained during the period from time t ₃ to time t _4.

[Equation 4] The final value I stabilizes at the current shown in.

Here, the parameters represented by the equations (1) and (2) have the characteristics as shown in FIG. 3, and in practice, the time between the times t ₁ , t ₂ , t ₃ and t ₄ described above. Alternatively, it may be set according to the devices of the current-voltage conversion circuits 11 and 12, or may be determined by the S / N of the entire sample hold circuit 10.

In the case of this embodiment, the sample and hold circuit 10 has a circuit configuration as shown in FIG. 4, and the input signal V _IN10 is the differential pair, and the first and second voltage-current conversion circuits 11 and 12 are provided. Is input to the bases of the transistors Q1 and Q3, which are one of the transistors Q1 and Q2, and Q3 and Q4.

The collectors of the transistors Q1 and Q2, Q3 and Q4 are connected to a current mirror, and the collectors are connected to the power source V _CC through resistors R2 and R3, respectively, and the emitters of the transistors Q5 and Q6 forming a constant current source are connected. ing.

Further, the transistors Q1 and Q2, Q3
The emitters of Q4 and Q4 are respectively connected in common, and are connected to the collectors of the transistors Q7 and Q9, which are one of the transistors Q7 and Q8, Q9 and Q10 which perform a switching operation in response to the sample hold pulse P _SH .

Transistors Q7 and Q8, Q9 and Q1
The emitters of 0 are connected in common, and are connected to the collectors of the transistors Q11 and Q12, which form a current source, by the first control signal IN1 input to their respective bases. The emitters of the transistors Q11 and Q12 are grounded (G
ND).

In practice, the resistors R5 and R6 are selected to have a higher resistance value than that of the resistor R5, so that the transistor Q forming the first and second voltage-current conversion circuits 11 and 12 is formed.
1 and Q2, and Q3 and Q4 satisfy the condition of the expression (2).

The base of the transistor Q7, Q9 has a emitter of the transistor Q13 which voltage the collector by dividing the inter-power supply V supply connected to base _CC V _CC and the ground GND by a resistor R7 and R8 is applied, the base The second control signal IN2 is input to the emitter of the emitter of the transistor Q14, which is grounded through the resistor R10.

The collector of the transistor Q8 is connected to the power supply V _CC, and the collector of the transistor Q10 is connected to the power supply V _CC through the resistor R3, and the sample-hold pulse P _SH is applied to the respective bases thereof, and as shown in FIG. As described above, the sample hold pulse P
During the rising period of _SH , the transistors Q1 and Q2 forming the first and second voltage-current conversion circuits 11 and 12,
It is designed to operate Q3 and Q4.

In practice, the first and second voltage-current conversion circuit 1
Transistors Q1 and Q2, Q3 forming 1 and 12
And Q4 are configured to add and output collector currents of the transistors Q2 and Q4, respectively, and this outputs a resistor R10, transistors Q15, Q16, Q17 and Q18.
It is sent as an output signal V _OUT10 through the buffer 13 composed of and is supplied to the bases of the transistors Q2 and Q4.

In addition, the output signal V _OUT10 is supplied to the holding capacitor C _HD0 through the resistor R1 and charged. The holding capacitor C _HD0 is a resistor R
The power source V1 is connected through the switch 4, and the maximum value of the charging voltage is regulated by this. The output signal V _OUT10 is _divided and supplied to the base of the transistor Q2 through the resistors R12 and R13, which allows the charging control as shown in FIG. 3 to be performed while satisfying the condition shown in the equation (1). It is made possible.

The emitter of the transistor Q16 of the buffer 13 is grounded through the emitter resistor R11 to the second
Is connected to the collector of a transistor Q19 controlled by the control signal IN2, and the operation of the entire sample hold circuit 10 can be controlled by the first and second control signals IN1 and IN2.

According to the above configuration, in the differential amplifier configuration, the mutual conductance gradually increases, and the maximum current value with respect to the input voltage difference sequentially decreases. One input of the first and second voltage-current conversion circuits 11 and 12 Input signal V _IN10 at the end
_And the output signal V _OUTQ0 of the hold capacitor C _HD0 is supplied to the other input terminal, and the output currents I ₁ and I of the first and second voltage-current conversion circuits 11 and 12 are supplied at the timing of the sample hold pulse. _{Since the} holding capacitor C _HD0 is charged with the added current I obtained by adding ₂ , a sample hold circuit 10 capable of preventing the _overshoot and undershoot in advance and sample-holding the input signal V _IN10 at high speed. Can be realized.

In the above embodiment, two voltage-current conversion circuits having a differential amplifier configuration are used to obtain a desired charging current, but the present invention is not limited to this, and three or more voltage-current conversion circuits are used. A conversion circuit may be used. Incidentally, also in this case, if the mutual conductance of the voltage-current conversion circuit is successively increased and the maximum output current value with respect to the input voltage difference is selected so as to be gradually decreased, the same effect as that of the above-described embodiment can be obtained. In addition to the above-described embodiment, the rising characteristics of the output signal and the like can be set more finely.

Further, in the above embodiment, the case where the sample hold circuit of the present invention samples and holds the image detection signal sent from the CCD has been described, but the present invention is not limited to this, and various signals are sampled and held. It is suitable for a wide range of applications.

[0034]

As described above, according to the present invention, a plurality of differential voltage-current converting means having different output current values with respect to the voltage difference between the signals respectively supplied to the pair of input terminals,
An input signal is supplied to one input terminal and an output signal is supplied to the other input terminal through the current accumulating means, and the output currents of a plurality of differential voltage-current converting means are added according to the timing of the sample hold pulse. By storing the current in the current storage means, overshoot and undershoot are prevented in advance due to the characteristic difference of the plurality of differential voltage-current conversion means, and a predetermined input signal is sampled and held at high speed. It is possible to realize a possible sample and hold circuit.

[Brief description of drawings]

FIG. 1 is a connection diagram showing a sample hold circuit according to the present invention.

FIG. 2 is a signal waveform diagram for explaining the operation of the sample hold circuit of FIG.

FIG. 3 is a characteristic curve diagram for explaining the operating characteristics of the voltage-current conversion circuit of the sample hold circuit of FIG.

FIG. 4 is a connection diagram showing a circuit configuration example of the sample hold circuit of FIG.

FIG. 5 is a connection diagram showing a conventional sample hold circuit.

[Explanation of symbols]

1, 10 ... Sample and hold circuit, 2 ... Differential amplifier circuit, 3 ... Switch circuit, 11, 12 ... Voltage-current conversion circuit, 13 ... _Buffer , C _HD , C _HD0 ... Hold capacitor, V _IN , V _IN10 …… Input signal, V _OUT , V
_OUT10 …… Output signal, P _SH …… Sample and hold pulse.

Claims (2)

[Claims] 1. A sample and hold circuit for sampling and holding a predetermined input signal at the timing of a sample and hold pulse, each of which has a pair of input terminals, one input terminal being supplied with the input signal, A plurality of differential voltage / current converting means having different output current values with respect to the voltage difference of the signals respectively supplied to the input terminals, and output currents of the plurality of differential voltage / current converting means according to the timing of the sample hold pulse. Is accumulated, the accumulated additional current is held and sent as an output signal, and the current accumulating means supplies the other input terminal of the plurality of differential voltage-current converting means. A sample and hold circuit characterized in that 2. The proportional coefficient of the output current with respect to the input voltage of the plurality of differential voltage / current converting means is selected to be a sequentially larger value, and the maximum output current value of the plurality of differential voltage / current converting means is sequentially smaller value. The sample-hold circuit according to claim 1, wherein the sample-hold circuit is selected.