JPH06164263A - Operational amplifier - Google Patents

Abstract

PURPOSE:To provide an operational amplifier with high phase margin and slew rate in an operational amplifier to which a discrete signal is applied. CONSTITUTION:This amplifier is the one including plural amplification stages(Amp1, Amp2), and is provided with a feedback means(FB) connected between input and output and turned on/off by a first switching means(SW1), and a phase compensation means(PC) connected between the output of adjacent amplifier stages(Amp1, Amp2) and which includes the serial connection of a capacitor means(Cc) for phase compensation and a second switching means(SW2).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier, and more particularly to an operational amplifier having a large phase margin and a high slew rate.

[0002]

2. Description of the Related Art FIG. 3 shows a basic circuit of an operational amplifier (op amp) and its characteristics. FIG. 3A shows an operational amplifier circuit including a feedback loop. The operational amplifier OP has an amplification factor Av, and has an inverting input terminal (−), a non-inverting input terminal (+), and an output terminal. The reference voltage Vr is applied to the non-inverting input terminal, and the sum of the input signal vi and the feedback output is added by the adder AD is input to the inverting input terminal.

The operational amplifier OP generates an output signal at the output terminal which is Av times the difference between the input voltages applied to the both input terminals. The output terminal is also connected to the adder AD via the feedback circuit FB having the transfer rate k to feed back the output to the input side. The voltage at the output terminal is vo.

The transfer characteristic of the operational amplifier system provided with this feedback is expressed by Avf (s) = vo / vi = [-Av (s) / {kAv (s) +1}]. The stability condition is that the solution of the characteristic equation, that is, sp that satisfies kAv (sp) + 1 = 0 is not on the right half surface on the s-plane.

In the frequency characteristic (Bode diagram) of the loop gain kAv (s), this is [loop gain T (jω)
| T (jω) | <1 at the frequency at which the phase of -180 degrees
That is] is a stable condition.

As a measure of stability, the phase margin φM is defined as follows. When | T (jωo) | = 1, φM = {angle of T (jωo)} + 180 ° For example, it is assumed that the operational amplifier internal circuit has a configuration as shown in FIG. The first-stage differential input stage Amp1 and the second-stage amplification stage Amp2 are connected in series, and the resistor R1 is connected between the first-stage Amp1 output and the next-stage Amp2 input terminal.
The capacitor C1 is connected between the input terminal of Amp2 and ground.

A resistor R2 and a capacitor C2 are connected in series to the output terminal of the amplification stage Amp2, and the other end of C2 is grounded. In the current circuit, R1 and R2 are impedances of the output nodes of the amplification stages, and C1 and C2 are composed of parasitic capacitances connected to the output nodes of the amplification stages.

When one such RC integrating circuit is connected, the signal transfer characteristic is 90 when considering a sufficiently wide frequency range.
Causes a phase delay of one degree. The pole frequency corresponding to 1 / RC has a phase delay of 45 degrees. If two RC integrating circuits are connected in series, the total phase delay is 180
The phase delay up to the second pole is 135 degrees.

Now, R1 = 1k, C1 = 1p, R2 = 10
When 0k and C2 = 1p, the gain G and the phase delay φd of the operational amplifier shown in FIG. 3 (B) are as shown in FIG. 3 (C). That is, from the values of R2 and C2, the pole f _P1 =
1.6 × 10 ⁶ is determined, and f _P2 = 1.6 from R1 and C1
× 10 ⁸ is determined. The value at the center of the steep part of the phase delay curve φd corresponds to this pole. Gain G is 1
One pole has an attenuation of 6 dB / oct and the second pole has an attenuation of 12 dB / oct.

When the phase delay φd becomes 180 degrees, the above-mentioned transfer characteristic becomes ∞ and the circuit oscillates.
However, if the gain G is sufficiently attenuated before φd reaches 180 degrees, oscillation does not substantially occur. The position of each pole is controlled by the values of the resistance component R and the capacitance component C inserted between the adjacent amplification stages. 1 / R of the smaller one
C is made smaller, 1 / RC of the larger one is made larger, R1 = 1k, C1 = 0.1p, R2 = 100k, C
If 2 = 10p, then f _P1 = 1.6 × 10 ⁵ f _P2 = 1.6 × 10 ⁹ and the poles s1 and s2 are separated. FIG. 3D shows the gain characteristic G and the phase delay characteristic φd in this case.

At the frequency where the gain G is 0 (amplification factor 1), the difference between the phase delay φd and 180 degrees is the phase margin. In the case of FIG. 3C, the phase margin φM
Is about 20 degrees, and the phase margin φM in the case of FIG. 3 (D) is about 80 degrees. In order to prevent oscillation, the phase margin is preferably about 60 degrees or more.

As can be seen from the characteristics shown in FIGS. 3C and 3D, it is preferable to make the pole s _P1 small and the pole s _P2 large in order to increase the phase margin. This method is called pole splitting.

However, it is often the case that the values of R and C which are circuit constants cannot be arbitrarily selected. If the values of R and C are determined by other requests, the position of the pole is also determined.

As a technique for increasing the phase margin, there is known a technique for connecting a phase compensation capacitor between amplification stages of an operational amplifier. The operation of the phase compensating capacitor will be described below in comparison with the case without the phase compensating capacitor.

FIG. 4 shows an example of a specific internal circuit of an operational amplifier. FIG. 4A shows a configuration example of the internal circuit of the operational amplifier without the phase compensation as shown in FIG. 3B. Transistors T1 and M1 form a differential amplifier pair and are connected to load transistors T2 and M2, respectively.

The sources of the transistors T1 and M1 are connected to each other and to the transistor T3 which serves as a constant current source. It is assumed that the transistor T3 carries the current Ib. The output signal obtained from the interconnection point of the transistors M1 and M2 is directly connected to the gate of the transistor M3 of the next stage amplifier. A load transistor M4 is connected to the transistor M3. The input signal V _i is applied to the gate of the transistor T1 and the output signal V _o is provided from the interconnection point of the transistors M3 and M4.

FIG. 4B shows an equivalent circuit of the operational amplifier circuit shown in FIG. In this case, the poles s _P1 and s _P2
Is expressed by the following equation.

[0018]

[Equation 1]

FIG. 5 shows the structure of the internal circuit of a specific operational amplifier having phase compensation. FIG. 5A shows a specific structure of the internal circuit of the operational amplifier. Compared to FIG. 4A, the output terminals of the preceding amplification stage (transistors M1 and M
2) and a phase compensation capacitor Cc is connected between the output terminal (interconnection point of the transistors M3 and M4) of the subsequent amplification stage.

FIG. 5B shows an equivalent circuit of the operational amplifier circuit of FIG. 5A. Compared with FIG. 4B, the difference is that a phase compensating Cc is connected between the input terminal and the output terminal. In this case, the pole s _P1 and the pole s _P2 are

[0021]

[Equation 2]

It is represented as Note that these expressions are practical approximate solutions, and C1, go3, etc. are omitted. Due to the addition of the phase compensation capacitor Cc, the pole s _P1 is small and the pole s _P2 is large. In this way
The phase margin can be increased by connecting the phase compensation capacitor.

On the other hand, the slew rate of the transient characteristic index of the operational _{amplifier, SR = | dV o / dt} | = - | (1 / Cc) (dQc / dt) | = represented by Ib / Cc. That is, when the phase compensating capacitor Cc becomes large, the slew rate decreases. In this way, the phase compensation and the slew rate are in an opposite relationship.
Therefore, obtaining oscillation stability by phase compensation and obtaining steep transient characteristics are incompatible.

[0024]

The operational amplifiers include not only those to which an input signal is continuously applied but also those to which a signal is applied discretely or intermittently such as a switched capacitor circuit.

An object of the present invention is to provide an operational amplifier to which a discrete signal is applied, which has a large phase margin and a large slew rate.

[0026]

The operational amplifier of the present invention comprises:
An operational amplifier including a plurality of amplification stages (Ampl, Amp2), which is connected between an input and an output, and is provided with a feedback unit (FB) which is turned on / off by a first switch unit (SW1) and an adjacent amplification stage. It is connected between the outputs of (AmP1, Amp2), and is connected to the phase compensation capacitance means (Cc) and the second
And a phase compensation means (PC) including a series connection with the switch means (SW2).

[0027]

The phase compensating capacitance means connected between the outputs of the adjacent amplifying stages is turned on / off by the second switch means. Therefore, when the second switch means is turned on, the phase compensation capacitor is connected, and when the second switch means is turned off, the phase compensation capacitor is not provided.

When a discrete input signal is applied, the feedback means connected between the operational amplifier input and output is
It need not always be formed, and may be formed only when necessary.

When the first switch means is open and the feedback means is off, it is not necessary to consider the phase margin. Therefore, the second switch means can also be turned off, and the phase compensation capacitance means can be separated from the adjacent amplification stage. When the feedback means is connected, the phase compensation capacitance means may also be connected to perform the phase compensation.

Thus, by selectively connecting the phase compensating capacitance means, the phase margin and the slew rate can be kept high.

[0031]

1 shows a switched capacitor type operational amplifier according to an embodiment of the present invention. FIG. 1A shows a specific circuit configuration, and FIG. 1B shows its equivalent circuit.

In FIG. 1A, transistors T1 and M1 form a differential amplifier and are connected to load transistors T2 and M2, respectively. Transistors T1 and M1
Sources are coupled to each other and connected to a transistor T3 that serves as a constant current source. A constant bias voltage Vb is applied to the gate electrode of the transistor T3 of the constant current source.

An input signal is applied to the gate electrode of the transistor T1 via the switch SW3, and a constant reference voltage Va is applied to the gate electrode of the transistor M1. The interconnection point of the transistors M1 and M2, which is the output terminal of the pre-stage amplifier Amp1, is directly connected to the gate of the transistor M3, which is the input terminal of the next-stage amplifier Amp2. The transistor M3 is connected in series with the load transistor M4.

Further, a phase compensation circuit PC including a series connection of a phase compensation capacitor Cc and a switch means SW2 is connected between the output terminal of the front stage amplifier Amp1 and the output terminal of the rear stage amplifier Amp2.

A feedback circuit FB is connected between the output terminal of the amplifier Amp2 at the rear stage and the input terminal of the amplifier Amp1 at the front stage. The feedback circuit FB is
It includes a parallel connection of the capacitor Cs and the switch means SW1.

The switch means SW1 and SW2 are synchronously controlled by the same control signal φrs. The control signal φrs is supplied from the control circuit CTL. When φrs is turned on, the switch means SW1 and SW2 are closed to form a feedback loop and the phase compensation circuit P
A C capacitor Cc is connected between the output terminals of the front stage and the rear stage. In this way, the phase compensating capacitor Cc is connected between the adjacent amplification stages only when the feedback loop is formed.

As compared with the prior art operational amplifier circuit shown in FIGS. 4 and 5, the circuit of FIG. 1 (A) corresponds to the circuit of FIG. 4 in which the switch SW2 is always open. The circuit in which SW2 is always closed corresponds to the circuit in FIG. The switches SW1, SW2, SW
Each of 3 can be composed of a transistor.

FIG. 6 shows the characteristic of the operational amplifier shown in FIG. FIG. 6A shows a response characteristic when the switches SW1 and SW2 are controlled in synchronization. FIG. 6B shows a response characteristic when the switch SW2 is always open and the phase compensation capacitor is not present, that is, the circuit corresponds to the circuit of FIG. 6C shows a state in which the switch SW2 is always closed and the phase compensation capacitor Cc is always connected, that is, the characteristics of the circuit shown in FIG.

FIG. 6 in which there is no phase compensation capacitor.
The response characteristic of (B) shows a voltage waveform in which the signal rises quickly and the slew rate is high, but oscillation stability is lacking, and the signal waveform swings (oscillates) after the fall.

On the other hand, the response characteristic of FIG. 6C provided with the phase compensating capacitor shows stable characteristics by sufficiently suppressing the oscillation after the fall of the signal waveform, but slowing the rising edge of the signal. Low slew rate.

On the other hand, the response characteristic of FIG. 6A corresponding to the operational amplifier of FIG. 1 has a fast signal rise, a high slew rate, and an extremely stable characteristic after the signal fall. It also has excellent oscillation stability.

Under a certain condition, FIG. 6 (B)
6C, the phase margin φm is 51 degrees, the phase margin φm in FIG. 6C is 57 degrees, and the phase margin φm in FIG. 6A is
Is 64 degrees.

FIG. 2 shows an example of a concrete circuit of a CCD solid-state image pickup device using the operational amplifier shown in FIG. CC
In the D solid-state imaging device, photoelectric conversion elements such as photodiodes are arranged in a matrix, and a plurality of vertical charge transfer paths VCCD are arranged adjacent to each column of photoelectric conversion elements. One horizontal charge transfer path H is provided at the output end of each VCCD.
CCDs are arranged, and charges supplied from each VCCD are converted into parallel / serial signals and output to the output end.

The circuit shown in FIG. 2 shows an output part of the HCCD and an amplifier connected to the output end thereof. H1 and H2 are
The output portion of the HCCD driven by two phases is shown, and charges are supplied to the n ⁺ region 3 via the overflow gate OG. This charge charges the capacitor Cs connected between the input and output ends of the first stage operational amplifier OP1.

A constant reference voltage is applied to the non-inverting input terminal of the operational amplifier OP1. Further, the phase compensation capacitor Cc and the series connection of the transistor T5 are connected to the phase compensation capacitor connection terminal of the operational amplifier OP1. At the gate of this transistor T5,
The control signal φrs is applied similarly to the gate of the transistor T4.

That is, the transistors T4 and T5 are controlled in synchronization with the signal φrs. The transistors T4 and T5 are switch means SW1 and SW shown in FIG.
Make up 2.

While the capacitor Cs is being charged, the transistors T4 and T5 forming the switch means are kept off. The charge Q from the HCCD is the capacitor Cs
Is supplied to the capacitor Cs, a voltage of Q / Cs is generated in the capacitor Cs. In this way, an output signal is formed at the output terminal of the operational amplifier OP1.

At this time, since the transistor T5 is off, the phase compensating capacitor Cs is not connected and the rising edge of the output signal (that is, the slew rate) is fast. The output terminal of the first stage operational amplifier is connected to the non-inverting input terminal of the second stage operational amplifier OP2 via the transistor T6.
A capacitor C3 is connected to the non-inverting input terminal with the ground potential. When the transistor T6 is turned on, the capacitor C3 is quickly charged to the output voltage of the first stage operational amplifier. The output terminal of the operational amplifier OP2 is directly connected to the inverting input terminal to form a feedback loop and an impedance converter having an amplification factor of 1.

When the sampling is completed, the reset signal φrs becomes high, and the transistors T4 and T5 are turned on. The charge on the capacitor Cs is discharged through the transistor T4. At this time, the phase compensation capacitor Cc is connected to the operational amplifier OP1 through the transistor T5 to prevent oscillation.

The signals T1 and T shown on the HCCD are shown.
Reference numeral 2 indicates a control signal for controlling each stage of the HCCD. Also,
The diagram below each stage of the HCCD shows the potential diagram and the accumulated charge at each stage of the HCCD.

T1 indicates the potential at the timing T1, and T2 indicates the potential at the timing T2. In such a switch and capacitor type amplifier, the operational amplifier is not used continuously but is used intermittently by the switch T4. Therefore, the phase compensation capacitor Cc is also connected intermittently in synchronization. As described with reference to the circuit of FIG. 1, a high slew rate and a wide phase margin can be obtained at the same time.

Although the example of the CCD type solid-state image pickup device has been described, the operational amplifier shown in FIG. 1 can be used for any operational amplifier to which an input signal is discretely applied. Although the present invention has been described above with reference to the embodiments, the present invention is not limited thereto. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations and the like can be made.

[0053]

As described above, according to the present invention,
In an operational amplifier to which an input signal is applied intermittently, it is possible to simultaneously provide a high slew rate and a wide phase margin.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an operational amplifier according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific circuit configuration example using the operational amplifier of FIG.

FIG. 3 is a circuit diagram and a characteristic diagram showing an operational amplifier according to a conventional technique.

FIG. 4 is a circuit diagram of a conventional operational amplifier.

FIG. 5 is a circuit diagram of a conventional operational amplifier.

FIG. 6 is a graph showing the characteristics of the operational amplifier circuit shown in FIG. 1 in comparison with the characteristics of a conventional operational amplifier circuit.

[Explanation of symbols]

 T, M transistor SW switch means Amp amplifier PC phase compensation circuit FB feedback circuit CTL control circuit OP operational amplifier C capacitor R resistance

Claims (3)

[Claims] 1. An operational amplifier including a plurality of amplification stages (Ampl, Amp2), the operational amplifier being connected between an input and an output, the first switch means (SW).
Feedback means (FB) turned on / off in 1)
And a phase compensation means (PC) connected between the outputs of the adjacent amplification stages (Amp1, Amp2) and including a series connection of the phase compensation capacitance means (Cc) and the second switch means (SW2).
An operational amplifier having: 2. The operational amplifier according to claim 1, further comprising a control circuit (CTL) which generates a control signal for synchronously controlling the first and second switch means (SW1, SW2). 3. A method of controlling an operational amplifier having a feedback loop and a phase compensation capacitor, wherein a feedback loop is selectively formed, and the phase compensation capacitor is provided in the operational amplifier while the feedback loop is formed. A method of controlling an operational amplifier that connects and also disconnects the phase compensation capacitor when the feedback loop is disconnected.