JP2898160B2 - Transversal filter amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transversal filter (delay line filter) using a charge-coupled device (hereinafter, referred to as a CCD) of a floating gate detection system (hereinafter, referred to as an FGA system). The present invention relates to a transversal filter amplifier provided.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a configuration of a conventional general transversal filter. The transversal filter has a transfer stage 10 ₁ to 10 _n in a plurality of stages consisting of CCD delay line for successively delaying an input voltage V _in, they are connected in cascade. The output voltages V _{1 to} V _n of the transfer stages 10 ₁ to 10 _n are weighted by a weight coefficient h _k (where k; 1
1, 2,..., N) are multiplied and input to the addition circuit 20. The addition circuit 20 has a function of adding the output voltages h _k and V _k of the transfer stages 10 ₁ to 10 _n multiplied by the weight coefficient h _k and outputting the result as an output voltage V _out . In this type of transversal filter, the input voltage V _in is inputted in the form of a signal charge Q _s, the signal charges Q _s is sequentially delayed by each transfer stage 10 ₁ to 10 _n, the delay output of the respective stages The voltages V _{1 to} V _n are multiplied by a weight coefficient h _k and input to the addition circuit 20. The adding circuit 20 adds the output voltages K _k and V _k after multiplying the weight coefficients of the respective stages, and
Output as _out .

FIG. 3 is a schematic circuit diagram of the transversal filter of FIG. In this transversal filter, each transfer stage 10 ₁ is placed on the surface of a semiconductor substrate (not shown).
The transfer electrodes 11 and 12 constituting 10 to 10 _n are sequentially arranged, and a floating gate (hereinafter, referred to as FG) 13 of each stage as a detection electrode is arranged between them. The FG 13 of each stage is divided into two by the length ratio of (1 + h _k ) :( 1−h _k ), and the weight coefficient h _{k of} each stage is determined by the difference h between the two electrode lengths. Clock pulses φ1 and φ2 are applied to the transfer electrodes 11 and 12 of each stage, respectively. One FG 13 a of the FG 13 divided into two in each stage is connected to the detection line 14, and the other FG 13 b is connected to the detection line 15. The detection lines 14 and 15 include an amplifier 20a constituting the addition circuit 20.
Is connected, and the output voltage _Vout is output from the amplifier 20a.

[0004] The amplifier 20a, the DC bias voltage V _a
(For example, 2.5 V) is applied, and its + input terminal is connected to the detection line 14, and its − input terminal is connected to the detection line 15. Between the positive input terminal of the differential amplifier circuit 21 and the bias voltage Va, _a reset capacitor 22 and a reset switch 24 constituting reset means are connected in parallel. A reset capacitor 23 constituting reset means is provided between the output terminal of the differential amplifier circuit 21 and its negative input terminal.
And the reset switch 25 are connected in parallel.

[0005] The transversal filter, both the input voltage V _in is inputted in the form of a signal charge Q _s, the clock pulse .phi.1, when φ2 is sequentially applied to the transfer electrodes 11 and 12 in each stage, the transfer electrodes The depth of the potential wells formed below 11 and 12 changes. Therefore, the signal charge Q _s entered, the transfer electrodes 11 and 12 in each stage, and FG1
3 is transferred along the transfer direction X in the lower potential well. Then, FG1 of each stage by a signal charge Q _s
Image charges are induced in 3a and 13b, and are sent to the + input terminal and the − input terminal of the differential amplifier circuit 21 through the detection lines 14 and 15.

In the charge detection period, the reset switch 2
4 and 25 are turned off, and the differential amplifier circuit 21
The difference between the image charges of the FGs 13a and 13b is obtained,
An output voltage V _out is output from the output terminal of the differential amplifier circuit 21. The output voltage V _{ou t} is expressed by the following equation (1). In the reset period after the elapse of the charge detection period, the reset switches 24 and 25 are turned on, the differential amplifier 21 operates as a voltage follower circuit, and the gain A of the differential amplifier 21 becomes 0 dB. In this type of transversal filter, the weight coefficient h _k is determined by the electrode length difference h, so that a small weight coefficient h _k can be obtained with high accuracy. In addition, since the output voltage _Vout can be obtained by determining the difference between the image charges by the differential amplifier circuit 21, the circuit configuration of the adder circuit 20 is simplified.

[0007]

However, the conventional transversal filter amplifier 20a has the following problems. FIG. 4 is a diagram showing a charge detection period Ta and a reset period Tb of the transversal filter of FIG. FIG. 5 is a frequency-gain characteristic diagram of FIG. In the conventional transversal filter, as shown in FIG. 4 and FIG. 5, when the reset period Tb is reached after the elapse of the charge detection period Ta, the reset switches 24 and 25 are turned on, and the gain A of the differential amplifier circuit 21 is increased. To 0 dB. When the gain A is set to 0 dB, the frequency f2 at that time
, Ringing (peaking) P occurs. Therefore, there is a problem that the group delay time in the frequency band becomes longer, and the charge detection operation after the lapse of the reset period Tb cannot be accelerated.

Further, between the reset period Tb and the next charge detection period Ta, the voltage of the FG 13 becomes unstable, and the characteristic of the frequency f shifts. Therefore, there is a problem that highly accurate signal detection cannot be performed. The present invention provides a transversal filter for a transversal filter which solves the problems of the prior art that ringing P is generated, so that the charge detection operation after reset cannot be performed quickly and signal detection cannot be performed with high accuracy. An amplifier is provided.

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is directed to a difference between image charges induced in a plurality of stages of FGs of a divided structure arranged between a plurality of stages of transfer electrodes for signal charge transfer. A differential amplification stage that amplifies the signal and outputs a weighted signal; and a reset unit that sets the gain of the differential amplification stage to 0 dB at the time of reset after charge detection. Means are provided. This phase compensating means is configured to connect a phase compensating capacitor to the output side of the differential amplification stage via a switch that is turned on only at the time of reset.

[0010]

According to the present invention, since the amplifier for a transversal filter is configured as described above, the difference between the image charges induced in the FG is amplified by the differential amplifier stage during the charge detection period. In the reset period, the gain of the differential amplifier stage is set to 0 dB by the reset means. At this time, the switch in the phase compensation means is turned on, and the phase compensation capacitance is connected to the output side of the differential amplification stage. Therefore, the maximum frequency when the gain is 0 dB decreases, and ringing at the time of resetting is eliminated.

[0011]

FIG. 1 is a block diagram of a transversal filter amplifier according to an embodiment of the present invention. Elements common to those shown in FIGS. 2 and 3 are denoted by the same reference numerals. . This amplifier is a circuit connected to the detection lines 14 and 15 in place of the conventional amplifier 20a shown in FIG. 3, and includes a differential amplifier circuit 30 and reset means including switches 41, 42, 43 and 44 and the like. A capacitor 61 for compensating the phase of the output of the differential amplifier circuit 30; and a phase compensating means 62 that is turned on only at the time of reset. That is,
To the detection line 14, a DC bias voltage V _b (for example, 2.5 V) is applied via a switch 41, and a negative input terminal of the differential amplifier circuit 30 is connected via a capacitor 52. . Further, the detection line 14 has a capacity 51
Is connected to the output terminal of the differential amplifier circuit 30 through the capacitor 51 and to the negative input terminal of the differential amplifier circuit 30 via the capacitor 51 and the switch 43 connected in series.

A bias voltage _Vb is applied to the detection line 15 via a switch 42, and the + input terminal of the differential amplifier circuit 30 is connected via a capacitor 54. In addition, a DC bias voltage VLA (for example, 2.5 V) is applied to the detection line 15 via a capacitor 53, and the capacitor 53 and the switch 44 connected in series are connected.
Is connected to the + input terminal of the differential amplifier circuit 30 via. An output phase compensation capacitor 61 is connected between the output side of the differential amplifier circuit 30 and the ground potential V _ss .
The phase compensator 62 which is turned on only at the time of reset is connected. The phase compensating means 62 includes a switch 62a that is turned on only at the time of reset and a phase compensating capacitor 62b.
And a series circuit.

FIG. 6 is a circuit diagram showing a configuration example of the amplifier shown in FIG. In this amplifier, each switch 41, 4
Reference numerals 2, 43, 44, and 62a each include an analog switch in which a P-channel MOS transistor (hereinafter, referred to as a PMOS) and an N-channel MOS transistor (hereinafter, referred to as an NMOS) are connected in parallel. These analog switches are turned on when the reset signal RS is at the “H” level and the inverted reset signal RS / is at the “L” level, and when the reset signal RS is “L” level and the inverted reset signal RS /
At "H" level. Further, the differential amplifier circuit 30 includes a differential amplifier stage and an output stage.

The differential amplification stage includes an input NMOS 31 that is turned on and off by a voltage of a positive input terminal, and an input NMOS that is turned on and off by a voltage of a negative input terminal.
32, the NMOS31,32 a power source and a current mirror circuit consisting of PMOS33,34 connected between the voltage V _cc, DC bias voltage connected to the gate between the ground potential V _ss and the NMOS31,32 VGS (for example,
1.1V) to which a current source NMOS 35 is applied. The output stage includes a power supply voltage _Vcc and an output voltage V
_out , connected between the output terminal V _out and the ground potential V _ss, and a current source connected between the output terminal V _out and the ground potential V _ss to apply the bias voltage VGS to the gate. And the NMOS 37 for use. FIG. 7 shows the charge detection period Ta and the reset period T of FIG.
FIG. 8B is an operation waveform diagram, and FIG. 8 is a frequency-gain characteristic diagram of FIG. 6, and the operation of FIGS. 1 and 6 will be described with reference to these diagrams.

First, in the charge detection period Ta of FIG.
Reset signal RS goes low and the inverted reset signal RS / goes high, and the switches 41, 42,
43, 44 and 62a are turned off. As before,
Each stage of the FG13a the signal charge Q _s in Fig. 3, 13b
Image charge is induced on the detection lines 14, 1
5 to the amplifier of FIGS. 1 and 6, the image charges from the detection lines 14 and 15 are input to the input NMOSs 31 and 32 in the differential amplifier circuit 30 via the capacitors 52 and 54. Then, according to the difference between the input image charges, the input NMOS 3
1 and 32 are turned on and off complementarily, the difference is amplified and the output MOS 36 is turned on and off, and the output N
The output voltage V _out is output from the MOS 36.

Next, the reset signal RS in FIG. 6 goes high and the inverted reset signal RS / goes low, turning on the switches 41, 42, 43, 44, and 62a. It becomes Tb. During the reset period Tb, the switches 41, 42, 43, and 44 are turned on, so that the differential amplifier circuit 30 operates as a voltage follower circuit, and the gain A thereof becomes 0 dB. When the gain A is 0 dB, the ringing P occurs in the conventional circuit because the frequency f2 is high as shown in FIG. In order to solve this, in the present embodiment, the phase compensating means 62 is provided, so that the capacitance 62b therein is connected to the output side of the differential amplification stage, and the capacitance value for phase compensation increases. frequency f2 as shown in drops to the frequency f2 _a.

As a result, as shown in FIG. 7, the ringing P at the time of resetting is eliminated. Therefore, the group delay time in the frequency band is reduced, and the charge detection operation in the charge detection period Ta after the reset period Tb has elapsed can be accelerated.
Further, the reset period Tb and the subsequent charge detection period T
Since the voltage of the FG 13 between the FG 13 and the signal a is stable and the frequency characteristics do not shift as in the related art, highly accurate signal detection can be performed.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, there are the following modifications. (A) The amplifiers of FIGS. 1 and 6 may have other transistor configurations. Further, in the above embodiment, the fixed phase compensation capacitor 61 and the phase compensation capacitor 62b connected only at the time of resetting are provided. However, the capacity and the number thereof may be arbitrarily set, or the capacitor 61 may be omitted. Phase compensation means 6
Alternatively, the phase compensation may be performed only by using two. (B) The electrode structure to which the amplifiers of FIGS. 1 and 6 are connected may be changed to a configuration other than that of FIG.

[0019]

As described above in detail, according to the present invention, since the phase compensating means is provided, the phase compensating capacitor is connected to the output side of the differential amplifier stage only at the time of resetting, In the case where the gain of the amplifier is 0, phase compensation is performed by the phase compensation capacitor, and the frequency is reduced, so that ringing as in the related art can be prevented. Therefore, the group delay time in the frequency band is shortened, and the charge detection operation after reset can be speeded up. In addition, the voltage of the FG is stable between the reset period and the subsequent charge detection period, and high-precision signal detection can be performed without a shift in frequency characteristics.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an amplifier according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a conventional transversal filter.

FIG. 3 is a schematic circuit diagram of the transversal filter shown in FIG. 2;

4 is an operation waveform diagram of the amplifier shown in FIG. 3 during a charge detection period and a reset period.

FIG. 5 is a frequency-gain characteristic diagram of the amplifier shown in FIG.

FIG. 6 is a circuit diagram illustrating a configuration example of the amplifier illustrated in FIG. 1;

7 is an operation waveform diagram of the amplifier shown in FIG. 6 during a charge detection period and a reset period.

8 is a frequency-gain characteristic diagram of the amplifier shown in FIG.

[Explanation of symbols]

11, 12 Transfer electrode 13, 13a, 13b Floating gate (FG) 14, 15 Detection line 20 Addition circuit 30 Differential amplification circuit 52, 54, 61, 62b Capacity 41, 42, 43, 44, 62a Switch 62 Phase compensation means

Claims (1)

(57) [Claims] 1. A differential amplifier stage for amplifying a difference between image charges induced in a plurality of floating gates of a divided structure arranged between a plurality of signal charge transfer transfer electrodes and outputting a weighted signal. And the gain of the differential amplification stage is set to 0d at the time of reset after detecting the electric charge.
B. A transversal filter amplifier comprising: a reset unit for setting the phase compensation capacitor to B. A phase compensation unit configured to connect a phase compensation capacitor to an output side of the differential amplification stage via a switch that is turned on only at the time of the reset. And a transversal filter amplifier.