JPH0456506A - Offset component elimination circuit - Google Patents

Abstract

PURPOSE:To realize an offset component elimination circuit whose S/N is excellent by providing a capacitor between an inverted input of a 2nd differential amplifier and an output. CONSTITUTION:For a period when an input signal does not stay in a reference level, that is, in the hold mode, a signal is fed to a control input terminal 13 to open a source and a drain of a FET 8, a voltage having been fed to a capacitor 6 during the sample mode is fed to a 2nd differential amplifier 7 as an input signal, the signal is amplified and fed to a noninverting input terminal of a 1st differential amplifier 3. Thus, when the capacitance of the capacitor 6 is large, the voltage across the capacitor is kept almost constant for the hold mode period. Thus, a signal output from which a bias offset level is eliminated is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an analog signal processing circuit, and particularly to an amplifier circuit that removes offset components contained in a signal.

[Conventional technology]

For example, an amplifier circuit shown in FIG. 3 has been conventionally used to remove the bias offset component of an input signal that has a bias offset component as shown in FIG. 2 and includes a reference signal as information.

The input signal is applied to an inverting amplifier circuit composed of an amplifier 11, a resistor 1, and a resistor 2, where it is amplified and output.

In this amplifier circuit, a constant voltage power supply 9 provided on the input side of the amplifier 11 applies a voltage of opposite polarity equal to the bias offset component together with the input signal to remove the bias offset component. However, the level of the bias offset component typically changes over time.

For example, the level of the bias offset component of a signal output from a photodiode varies depending on the ambient temperature.

Therefore, it has been impossible to completely eliminate the bias offset component unless the voltage of the constant voltage power supply 9 is changed in accordance with the bias offset level.

Therefore, the amplifier circuit shown in FIG. 4 has been conventionally used.

In the amplifier circuit shown in FIG.
1 is applied to one input of the differential amplifier 10 through a buffer amplifier configured by 1.

This input signal is also applied to the amplifier 1 via the source and drain electrodes of the FET (field effect transistor) 8.
The connection part of the FET 8 which is applied to the input of the FET 6 and the amplifier 11 is grounded through the capacitor 6.

The output of the amplifier 16 mentioned above is connected to the other input of the differential amplifier 10.

During the period when the reference signal is input as an input signal, that is, during the reference level period, a control signal of logic "'1", for example, is applied from the control input terminal 13 to the gate terminal of FET 8, and the source terminal and drain terminal of FET 8 are When the bias offset component of the input signal is applied to the differential amplifier 10 via the amplifier 16, the bias offset component of the input signal is applied to the differential amplifier 10 via the amplifier
Only the difference component between the output signal from the amplifier 16 and the output signal from the amplifier 16 is amplified by the differential amplifier 10 and output.

Therefore, if the frequency characteristics and gains of the amplifiers 11 and 16 are made equal, the output of the differential amplifier 10 can be set to O.

Furthermore, when the input signal is outside the above-mentioned reference level period, for example, a signal "0" is applied to the control input terminal, and the FET8
When the source and drain terminals of the amplifier 16 are opened, the voltage applied between both terminals of the capacitor 6 during the reference level period is maintained and applied to the input terminal of the amplifier 16.

Therefore, during periods other than the reference level period, the bias offset component outputted by the amplifier 16 is subtracted from the signal component outputted by the amplifier 11 by the differential amplifier 10 and output.

That is, the bias offset component is removed, and a signal output having the reference level O can be obtained.

[Problem to be solved by the invention]

The conventional amplifier circuit for removing offset components described above requires at least three amplifiers, and requires gain adjustment of each of these amplifiers and level adjustment of the two input signals of the differential amplifier 10.

That is, there are drawbacks that the circuit configuration is complicated and that it takes a lot of time to electrically adjust the circuit.

Regarding the amplifier that detects the reference level, since the reference level period is shorter than the period in which signals other than the reference level are input, the capacitor 6 and the input terminal 12 when the source and drain terminals of the FET 8 are in a conductive state It is necessary to set the time constant formed by the internal resistor 15 of the external signal supply source 14 connected to a small value so that the input circuit operates up to a high frequency when the reference level is input.

Generally, the internal resistance of a signal source that supplies signals to the circuit shown in FIG. 4 is not small, so when considering the internal resistance 15 and the time constant of the capacitor 6, it is necessary to minimize the capacitance of the capacitor 6.

On the other hand, the period during which a signal outside the reference level period is input is longer than the reference level period, so if the capacitance of capacitor 6 is made small, the charge accumulated by this capacitor 6 during the reference level period will exceed the above-mentioned reference level period. During periods other than the reference level period, the voltage across the capacitor 6 gradually decreases as it is discharged through an internal resistance (not shown) of the amplifier 16.
The disadvantage is that the offset bias component cannot be completely removed from the signal output from 0, and the remaining offset signal becomes a noise component and deteriorates the signal-to-noise ratio of the circuit.

An object of the present invention is to provide an offset component removal circuit that does not require as many amplifiers as conventional ones and has a good signal-to-noise ratio.

[Means to solve the problem]

The offset component removal circuit of the present invention has a first resistor into which a signal is input from one end, a polarity inversion input part and a positive input part, and the other end of the first resistor is connected to the polarity half-inversion input part. a first differential amplifier connected to the first differential amplifier; a second resistor connected between the polarity inverting input section and the output section of the first differential amplifier;
a third differential amplifier whose one end is connected to the output section of the first differential amplifier;
and a resistor having a resistance value sufficiently larger than the resistance value of the third resistor, one end of which is connected to the other end of the third resistor, and the other end of which is connected to the positive input of the first differential amplifier. a fourth resistor connected to the output section; the output section has a polarity inverting input section and a positive input section connected to the positive input section of the first differential amplifier; the positive input section is held at a reference potential; one of a source or a train terminal is connected to a polarity inverting input portion of the second differential amplifier, and the other is connected to a connection point between the third and fourth resistors; The present invention is characterized in that it includes a field effect transistor to which an external control signal is applied to its gate terminal, and a capacitor connected between the polarity inverting input section and the output section of the second differential amplifier.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

The input signal is applied from the input terminal 12 via the resistor 1 to the polarity inverting input section of the first differential amplifier 3, where it is amplified to become an output signal, via the resistor 5, and then to the FET.
8 and is applied to the inverting input section of the second differential amplifier 7.

A polarity inverting input section and an output section of the first differential amplifier 3 are connected through a resistor 2.

One end of the resistor 5 connected to the FET 8 is further connected to one end of the resistor 4, and the other end of the resistor 4 is connected to the output part of the second differential amplifier 7 and the positive terminal of the first differential amplifier 3. Connected to the input section.

A capacitor 6 is connected to the polarity inverting input of the second differential amplifier 7 and the output of this differential amplifier.

A control input signal from the outside is inputted through the control input terminal 13 and then inputted to the gate terminal of the FET 8 .

Further, the positive input terminal of the second differential amplifier 7 mentioned above is grounded, and a ground potential is applied to this positive input terminal as a reference potential.

When the input signal is at the reference level, that is, in the sample mode, an external signal, for example, a control signal "1" is applied to the control input terminal 13 as shown in FIG.
Make the source and drain terminals conductive.

Therefore, in the sample mode, the signal amplified by the first differential amplifier 3 is input to the second differential amplifier 7 via the FET 8, the polarity is inverted and amplified, and the signal is amplified by the first differential amplifier 3. Applied to the positive input terminal.

In addition, during a period other than the reference level period, that is, in the hold mode, an o'' signal, for example, is applied from the outside to the control input terminal 13, and the source of FET 8 and the train terminal are opened, so that during the sample mode period. The voltage applied to the capacitor 6 in the second differential amplifier 7
is applied as an input signal to , the polarity is inverted, amplified, and applied to the positive input terminal of the first differential amplifier 3 .

The input signal voltage applied to the input terminal 12 from the outside is Vs.
, the output signal voltage is 0, the output voltage of the second differential amplifier 7 is vh, and the resistance values of resistors 1 and 2 are Rs and Rf, respectively, then the output voltage Vo is expressed by the following formula. It will be done.

Vo= −(Rf/Rs) Vs+ (1+R
f/Rs)Vh・・・・・・・・・・・・・・・・・・
(1) Here, when the input signal voltage Vs is expressed by a bias offset level voltage Vr and a relative voltage component Vi with respect to this bias offset level, the following is obtained.

Vs=Vi+Vr・・・・・・・・・・・・・・・・
(2) Also, the output voltage vh of the second differential amplifier 7 is expressed as a function of t, where t is the elapsed time from arbitrary time to. , Vh(t)=
[(Vr-Rf/Rs)/(1+R1s/R1f)J
・[1exp (t/ (Ch-R1f/ (1+R
1f/RIS)))]・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・(3)

Here, Rlf and Rls are the resistance values of the resistors 4 and 5, respectively, and ch is the capacitance value of the capacitor 6.

From the above-mentioned equations (1) to (3), the output signal (1)0 is expressed by the following equation.

Vo=-(Rf/Rs)Vi-(Rf/Rs)-Vr
[1-(1/ (1+R1s/R1f))[1-ex
p (-t/ (Ch -R1f/ <1+RIf/R
15))l]]・・・・・・・・・・・・・・・・・・
(4) The output voltage from the second differential amplifier 7 in the hold mode depends on the voltage between the terminals of the capacitor 6, but the electrical energy stored between the terminals of the capacitor 6 Although it is consumed in the input resistance (not shown) of the differential amplifier 7 of No. 2 and decreases over time, Equation (4)
As is clearer, the capacitance value of the capacitor 6 is not limited in terms of frequency characteristics, so this capacitance value can be made sufficiently large for the hold mode period.

If the capacitance value of capacitor 6 is large, the voltage across this capacitor can be held almost constant during the hold mode.

In this formula (4), R1f/R1s>>1,
When t is sufficiently large, the term Vr becomes O.

Therefore, the output voltage ■0 is as follows.

Vo=-(Rf/Rs)Vi・・・・・・・・・・・・
(5) That is, it is possible to obtain the signal output Vo from which the bias offset level has been removed.

In the embodiment shown in FIG. 1, the positive input section of the second differential amplifier 7 is grounded, and the ground potential is the reference potential.
If the voltage representing the desired reference signal is not 0 but, for example, 10E, the second input is connected to the voltage (R1f/R1
5) The reference potential of the positive input part of the second operational amplifier 7 can be set by installing it via a constant voltage power supply with E and connecting the positive side of this constant voltage power supply to the above-mentioned second input part. of(
R1f/R15) is 1, and the reference signal level is +
An output signal with E can be obtained.

〔Effect of the invention〕

As explained above, according to the present invention, the offset component that is included in the reference signal and fluctuates over time can be removed from the input signal by using a circuit configuration that uses fewer amplifiers than the conventional circuit for removing this type of offset level. Therefore, it is possible to obtain an offset component removal circuit with a good signal-to-noise ratio.

Further, according to the present invention, it is possible to obtain an offset component removal circuit that has a simpler configuration and can perform adjustment in a shorter time than conventional circuits of this type.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the relationship between input and output signals of the present invention, and FIGS. 3 and 4 are block diagrams of conventional circuits of this type. . 1-2...Resistor, 3...First differential amplifier, 4-
5... Resistor, 6... Capacitor, 7... Second differential amplifier, 8... FET, 9... Constant voltage power supply, l
O... Differential amplifier, 12... Input terminal, 13...
Control input terminal.

Claims (1)

[Claims] 1. A first resistor to which a signal is input from one end, a polarity inversion input part and a normal input part, and the first resistor is connected to the polarity half-inversion input part.
a first differential amplifier connected to the other end of the resistor; a second resistor connected between the polarity inverting input section and the output section of the first differential amplifier; a third resistor having one end connected to the output section of the dynamic amplifier; and a third resistor having a resistance value sufficiently larger than the resistance value of the third resistor and having one end connected to the other end of the third resistor. a fourth resistor whose other end is connected to the positive input section of the first differential amplifier;
A second differential amplifier is connected to the positive input part of the differential amplifier, has a polarity inverting input part and a positive input part, and the positive input part is held at a reference potential.
a differential amplifier, one of the source or drain terminals is connected to the polarity inverting input section of the second differential amplifier, the other is connected to the connection point of the third and fourth resistors, and the other is connected to the gate terminal. An offset component removal circuit comprising: a field effect transistor to which an external control signal is applied; and a capacitor connected between the polarity inverting input section and the output section of the second differential amplifier. 2. In the offset component removal circuit according to claim 1,
An offset component removal circuit characterized in that the reference potential is a ground potential. 3. In the offset component removal circuit according to claim 1,
An offset component removal circuit characterized in that the reference potential is an output potential of a constant voltage power supply.