JP2004222018A - Switched capacitor amplifier circuit - Google Patents

Switched capacitor amplifier circuit Download PDF

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Publication number
JP2004222018A
JP2004222018A JP2003007857A JP2003007857A JP2004222018A JP 2004222018 A JP2004222018 A JP 2004222018A JP 2003007857 A JP2003007857 A JP 2003007857A JP 2003007857 A JP2003007857 A JP 2003007857A JP 2004222018 A JP2004222018 A JP 2004222018A
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Prior art keywords
voltage
input
reference voltage
offset
capacitor
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JP2003007857A
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Japanese (ja)
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JP4094436B2 (en
Inventor
Hirokazu Yoshizawa
浩和 吉澤
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Seiko Instruments Inc
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Seiko Instruments Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a switched capacitor amplifier circuit capable of solving the problem that, when, in a conventional switched capacitor amplifier circuit, an input voltage itself has an offset DN pressure, the offset voltage is amplified and of reducing influences of the offset voltage. <P>SOLUTION: It is possible to cancel the offset voltage included in an input signal by constituting the circuit such that, in a sampling phase, a capacity connected to an input terminal is connected to a reference voltage in a reset phase and a difference between the reference voltage and a standard voltage given to a switch is controlled. Thus, it is possible to amplify just a signal element by canceling the offset voltage which the input voltage has. Also, when the offset voltage, which the input voltage has, has a temperature characteristic, it is possible to cancel the offset voltage including the temperature characteristic. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は、オフセット電圧をキャンセルするスイッチトキャパシタ増幅回路に関する。
【0002】
【従来の技術】
従来のオフセットキャンセル型スイッチトキャパシタ増幅回路は、オペアンプの持っているオフセット電圧を容量に蓄えることで、オフセット電圧を出力に生じないように構成されている(例えば、特許文献1参照)。
【0003】
【特許文献1】
米国特許第4543534号明細書(第1−3項、第1図)
従来のオフセットキャンセル型スイッチトキャパシタ増幅回路の回路構成の例を図4に示す。
【0004】
リセットフェーズΦ1においてスイッチ回路123、124、125、128、129、132が閉じる。このとき容量101、102、103、104は、スイッチ回路123、124、125、129を通じて放電される。一定の時間の後、スイッチ回路123、124、125、128、129、132が開いて、リセットフェーズΦ1が終了する。
【0005】
次にサンプリングフェーズΦ2に移る。スイッチ回路121、122、126、130、128、132が閉じる。入力端子141の電圧は容量101に、入力端子142の電圧は容量102に電荷として蓄えられる。容量101の電荷の変化分に等しいだけ容量103の電荷が変化する。同時に容量102の電荷の変化分に等しいだけ容量104の電荷が変化する。これによって、出力端子151の電圧が変化する。出力端子151の電圧は、式(1)で与えられる。
【0006】
Vout= −(C1/C2)*(Vin1−Vin2)・・・(1)
オペアンプの持っている入力オフセット電圧はリセットフェーズ?1において容量101、102に蓄えられる。サンプリングフェーズΦ2のときの容量101の両端間の電位の変化分は入力端子141の電圧とスイッチ123に与えられる基準電圧の差となる。同様にサンプリングフェーズΦ2のときの容量102の両端間の電位の変化分は入力端子142の電圧とスイッチ124に与えられる基準電圧の差となる。したがって、容量101、102の両端間に蓄えられる電圧の変化分は、入力電圧と基準電圧の差となり、オフセット電圧は含まれない。そのため、オペアンプの持つオフセット電圧は増幅されず、キャンセルされる。
【0007】
【発明が解決しようとする課題】
しかし従来のスイッチトキャパシタ増幅回路では、オペアンプの持つオフセット電圧はキャンセルできるものの、入力電圧それ自身がオフセット電圧をもつとき、そのオフセット電圧を増幅して出力してしまうという欠点を有していた。
【0008】
【課題を解決するための手段】
上記問題点を解決するために、この発明は、基準電圧の他に参照電圧を用い、これら参照電圧と基準電圧の差を制御することによって、入力電圧のもつオフセット電圧をキャンセルできる構成とした。上記のように構成されたスイッチトキャパシタ増幅回路では、入力電圧のもつオフセット電圧がキャンセルされるため、出力にオフセットを誤差を生じない。
【0009】
また、2つの参照電圧を設けて、それら参照電圧の差が入力電圧のもつオフセット電圧と等しくなるような構成にしても、出力にオフセット誤差を生じない。これら2つの参照電圧を与えるノードを互いに入れ替えることにより、オフセット電圧の極性が正のとき、負のとき両方に対応させることが可能である。
【0010】
【発明の実施の形態】
本願発明にかかるスイッチトキャパシタ増幅回路は、第1の入力信号が入力される第1の入力端子と、第2の入力信号が入力される第2の入力端子と、第1の入力端子の出力に基づいた信号が入力される第1の容量と、第2の入力端子の出力に基づいた信号が入力される第2の容量と、第1の容量の出力に基づいた信号と前記第2の出力に基づいた信号を比較し、信号を出力する演算増幅器と、を有する。さらに、第1及び第2の容量に電荷を供給する第1の参照電圧が印加される第1の参照電圧端子と、第1及び第2の容量に電荷を供給する第2の参照電圧が印加される第2の参照電圧端子と、を有する。そして、第1の参照電圧と第2の参照電圧の電圧値の差が、第1の入力端子と第2の入力端子間のオフセット電圧に一致するように、前記第1又は2の参照電圧の一方又は両方を調整することを特徴とする。これにより、入力電圧の持つオフセット電圧をキャンセルして、信号成分のみを増幅することができる。
【0011】
さらに、本願発明にかかるスイッチトキャパシタ増幅回路は、第1の参照電圧は温度特性を有し、第1の入力端子と前記第2の入力端子間のオフセット電圧が温度特性を有する場合に、第1の参照電圧と第2の参照電圧の電圧値の差が、第1の入力端子と第2の入力端子間のオフセット電圧に一致するように、第1の参照電圧は温度特性を設定することを特徴とする。これにより、入力電圧の持つオフセット電圧が温度特性を持つ場合、温度特性を含めてオフセット電圧をキャンセルすることができる。
【0012】
【実施例】
以下に、この発明の実施例を図面に基づいて説明する。図1は、この発明によるスイッチトキャパシタ増幅回路の構成図の一例である。リセットフェーズΦ1においてスイッチ回路123が閉じ、容量101は参照電圧111に接続され、スイッチ回路124が閉じ、容量102は参照電圧112に接続される。同時にスイッチ回路125、129が閉じ容量103、104は電荷が放電される。一定の時間の後、スイッチ回路123、124、125、129が開いて、リセットフェーズΦ1が終了する。リセットフェーズΦ1の間に、容量101に蓄えられた電荷はq=C1*VREF1容量102に蓄えられた電荷はq=C1*VREF2となる。
【0013】
次にサンプリングフェーズΦ2に移る。スイッチ回路121、122、126、130、128、132が閉じる。入力端子141の電圧は容量101に、入力端子142の電圧は容量102に電荷として蓄えられる。容量101の電荷の変化分に等しいだけ容量103の電荷が変化する。同時に容量102の電荷の変化分に等しいだけ容量104の電荷が変化する。
【0014】
これによって、出力端子151の電圧が変化する。サンプリングフェーズΦ2において容量101に蓄えられた電荷はq=C1*Vin1容量102に蓄えられた電荷はq=C1*Vin2となる。
【0015】
したがって、リセットフェーズΦ1からサンプリングフェーズΦ2に変わった後の容量101の電荷量の変化分は、Δq=C1*(Vin1−VREF1)となり、容量102の電荷量の変化分は、Δq=C1*(Vin2−VREF2)となる。
【0016】
入力端子141の電圧Vin1が信号電圧Vinpとオフセット電圧Vosから成り、入力端子142の電圧Vin2が信号電圧Vinnのみから成るとき、出力端子151の電圧は、
Vout = −(C1/C2)*{(Vin1−Vin2)−(VREF1−VREF2)}
= −(C1/C2)*{(Vinp + Vos −Vinn)−(VREF1−VREF2)}
= −(C1/C2)*{(Vinp−Vinn)+ (Vos−(VREF1−VREF2))}
で与えられる。
【0017】
Vos= VREF1−VREF2となるように、VREF1、VREF2を調整することで、
Vout =−(C1/C2)*(Vinp−Vinn)となり、入力信号Vin1のもつオフセット電圧Vosをキャンセルすることができる。
【0018】
このように本発明の回路方式では、入力電圧の持つオフセット電圧をキャンセルして、信号成分のみを増幅することができる。
【0019】
この例では、2つの参照電圧111、112を用いているが、図2、図3に示すように2つの参照電圧のうちの1つを基準電圧に置き換えて、1つの参照電圧と、基準電圧の差を用いて入力電圧の持つオフセット電圧をキャンセルすることが可能であることは明白である。たとえば、図3の例では、出力端子151の電圧は、
Vout =−(C1/C2)*{(Vinp−Vinn)+ (Vos−VREF)}となる。
【0020】
参照電圧111をVosと等しくなるように調整することで、Vout =(C1/C2)*(Vinp−Vinn)となり、入力信号Vin1のもつオフセット電圧Vosをキャンセルすることができる。
【0021】
ここで言う基準電圧は、通常アナロググラウンドと呼ばれるものであり、他のスイッチにも接続されている。出力電圧はこの基準電圧を中心にして、振幅する。上述した例では、説明を簡単にするため、基準電圧を0Vとして計算を行っている。
【0022】
図1のように2つの参照電圧を持つことの利点を以下に示す。たとえば、参照電圧111は温度特性をもたない参照電圧で、参照電圧112は温度特性をもつものとする。このようにすることで、入力電圧のオフセット電圧が温度特性をもつ場合、温度特性をもつ参照電圧112を用いて、入力電圧のオフセット電圧の温度特性をキャンセルし、参照電圧111を用いて、入力電圧のオフセット電圧と参照電圧112を与えることで生じるオフセット電圧の絶対値を合わせこむことができるようになる。
【0023】
図7に示すように、2つの入力電圧に対し、2つの参照電圧111、112を与えるノードをスイッチで切り替えることで参照電圧112の温度特性の極性と逆向きの極性の温度補正を与えることが可能になる。たとえば図7の参照電圧112が図8に示すような負の温度特性をもっているとする。入力電圧のオフセット電圧が正の温度特性をもっている場合は、図9(a)に示すようにクロック1aを用いて、入力電圧のオフセット電圧の正の温度特性をキャンセルする。逆に入力電圧のオフセット電圧が負の温度特性をもっている場合は、図9(b)に示すようにクロック1bを用いて、入力電圧のオフセット電圧の負の温度特性をキャンセルする。
【0024】
図7の回路は、図10に示すように2段増幅回路構成にして用いることもできる。このときは、入力電圧のもつオフセット電圧の温度特性は1段目の増幅回路の利得倍される。入力電圧のもつオフセット電圧の温度特性が、参照電圧の温度特性に比べて小さい場合はこのような2段増幅構成をとることにより、温度特性の合わせこみを行いやすくなる。
【0025】
本発明の記述において用いられるスイッチは、N型MOSFETやP型MOSFET、またはこれら2つを並列に接続したCMOSトランスミッションゲートで構成される。
【0026】
図1の回路は、図5に示すような2入力2出力を持つ完全差動回路においても、実施することができる。また図1の回路に限らず本発明の記述に用いた回路は図1の回路と同様に2入力2出力を持つ完全差動回路においても実施することができることは明白である。完全差動回路構成をとることにより、同相ノイズを低減する効果が得られる。
【0027】
図6の回路は、スイッチトキャパシタ増幅回路を2段構成にし、2段目でオフセットキャンセルを行っている例である。
【0028】
また、この実施例に示した回路はスイッチトキャパシタ増幅回路の一例であり、他の形式のスイッチトキャパシタ増幅回路においても、実施することが可能である。
【0029】
入力電圧に含まれるオフセット電圧の値があらかじめわかっており、一定の場合は、参照電圧は、固定電圧でもよいが、入力電圧に含まれるオフセット電圧の値が不明の場合は、参照電圧を入力電圧のオフセット電圧に合わせて調整できる可変電圧とすることで、出力電圧を見ながらオフセット電圧の調整を行うことが可能である。
【0030】
この調整可能な可変電圧をつくるひとつの例として次の方法が考えられる。電源電圧間を抵抗分割した抵抗ラダーを構成する抵抗のいくつかに並列にスイッチを接続し、そのスイッチを、EEPROMに書き込んだデータを元に開閉することで、所望の電圧を得ることができる。
【0031】
以上のようなスイッチトキャパシタ増幅回路を有する電子機器は、信号のノイズが低減されるため、正確な動作が可能となる。
【0032】
【発明の効果】
入力電圧の持つオフセット電圧をキャンセルして、信号成分のみを増幅することができる。また入力電圧の持つオフセット電圧が温度特性を持つ場合、温度特性を含めてオフセット電圧をキャンセルすることができる。
【図面の簡単な説明】
【図1】本発明のスイッチトキャパシタ増幅回路の構成図である。
【図2】本発明のスイッチトキャパシタ増幅回路の構成図である。
【図3】本発明のスイッチトキャパシタ増幅回路の構成図である。
【図4】従来のスイッチトキャパシタ増幅回路の構成図である。
【図5】本発明のスイッチトキャパシタ増幅回路の構成図である。
【図6】本発明のスイッチトキャパシタ増幅回路の構成図である。
【図7】本発明のスイッチトキャパシタ増幅回路の構成図である。
【図8】参照電圧のもつ温度依存性の一例である。
【図9】本発明のスイッチトキャパシタ増幅回路で用いるクロック波形を示す。
【図10】本発明のスイッチトキャパシタ増幅回路の構成図である。
【符号の説明】
100 演算増幅器
101、102、103、104、105、106 容量
111、112 参照電圧
123、124 スイッチ回路
141、142 入力端子
151、152出力端子
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a switched capacitor amplifier circuit for canceling an offset voltage.
[0002]
[Prior art]
A conventional offset-cancelled switched-capacitor amplifying circuit is configured to store an offset voltage of an operational amplifier in a capacitor so that an offset voltage is not generated in an output (for example, see Patent Document 1).
[0003]
[Patent Document 1]
U.S. Pat. No. 4,543,534 (section 1-3, FIG. 1)
FIG. 4 shows an example of a circuit configuration of a conventional offset cancellation type switched capacitor amplifier circuit.
[0004]
In the reset phase φ1, the switch circuits 123, 124, 125, 128, 129, 132 are closed. At this time, the capacitors 101, 102, 103 and 104 are discharged through the switch circuits 123, 124, 125 and 129. After a certain time, the switch circuits 123, 124, 125, 128, 129, 132 open and the reset phase Φ1 ends.
[0005]
Next, the process proceeds to the sampling phase Φ2. The switch circuits 121, 122, 126, 130, 128, 132 are closed. The voltage of the input terminal 141 is stored in the capacitor 101 and the voltage of the input terminal 142 is stored in the capacitor 102 as electric charge. The charge of the capacitor 103 changes by an amount equal to the change in the charge of the capacitor 101. At the same time, the charge of the capacitor 104 changes by an amount equal to the change in the charge of the capacitor 102. As a result, the voltage of the output terminal 151 changes. The voltage at the output terminal 151 is given by equation (1).
[0006]
Vout = − (C1 / C2) * (Vin1-Vin2) (1)
Is the input offset voltage of the operational amplifier reset phase? 1 and stored in the capacitors 101 and 102. The change in the potential between both ends of the capacitor 101 during the sampling phase Φ2 is the difference between the voltage at the input terminal 141 and the reference voltage supplied to the switch 123. Similarly, the change in the potential between both ends of the capacitor 102 during the sampling phase Φ2 is the difference between the voltage at the input terminal 142 and the reference voltage supplied to the switch 124. Therefore, a change in the voltage stored between both ends of the capacitors 101 and 102 becomes a difference between the input voltage and the reference voltage, and does not include the offset voltage. Therefore, the offset voltage of the operational amplifier is not amplified and is canceled.
[0007]
[Problems to be solved by the invention]
However, in the conventional switched capacitor amplifier circuit, although the offset voltage of the operational amplifier can be canceled, when the input voltage itself has the offset voltage, there is a disadvantage that the offset voltage is amplified and output.
[0008]
[Means for Solving the Problems]
In order to solve the above problem, the present invention uses a reference voltage in addition to the reference voltage, and controls the difference between the reference voltage and the reference voltage to cancel the offset voltage of the input voltage. In the switched capacitor amplifier circuit configured as described above, since the offset voltage of the input voltage is canceled, no error occurs in the output offset.
[0009]
Even if two reference voltages are provided and the difference between the reference voltages is equal to the offset voltage of the input voltage, no offset error occurs in the output. By exchanging the nodes for providing these two reference voltages with each other, it is possible to correspond both when the polarity of the offset voltage is positive and when the polarity of the offset voltage is negative.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
The switched capacitor amplifier circuit according to the present invention includes a first input terminal to which a first input signal is input, a second input terminal to which a second input signal is input, and an output of the first input terminal. A first capacitor to which a signal based on the output of the first capacitor is input, a second capacitor to which a signal based on the output of the second input terminal is input, a signal based on the output of the first capacitor, and the second output And an operational amplifier that compares the signals based on the signals and outputs the signals. Further, a first reference voltage terminal to which a first reference voltage for supplying charges to the first and second capacitors is applied, and a second reference voltage for supplying charges to the first and second capacitors are applied. And a second reference voltage terminal. Then, the first or second reference voltage is changed so that the difference between the voltage values of the first reference voltage and the second reference voltage matches the offset voltage between the first input terminal and the second input terminal. It is characterized in that one or both are adjusted. Thereby, the offset voltage of the input voltage can be canceled, and only the signal component can be amplified.
[0011]
Further, in the switched capacitor amplifier circuit according to the present invention, when the first reference voltage has a temperature characteristic and the offset voltage between the first input terminal and the second input terminal has a temperature characteristic, the first reference voltage has a temperature characteristic. The first reference voltage sets the temperature characteristic such that the difference between the reference voltage of the second reference voltage and the voltage value of the second reference voltage matches the offset voltage between the first input terminal and the second input terminal. Features. Thus, when the offset voltage of the input voltage has a temperature characteristic, the offset voltage including the temperature characteristic can be canceled.
[0012]
【Example】
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an example of a configuration diagram of a switched capacitor amplifier circuit according to the present invention. In the reset phase φ1, the switch circuit 123 is closed, the capacitor 101 is connected to the reference voltage 111, the switch circuit 124 is closed, and the capacitor 102 is connected to the reference voltage 112. At the same time, the switch circuits 125 and 129 are closed and the capacitors 103 and 104 are discharged. After a certain period of time, the switch circuits 123, 124, 125, and 129 open, and the reset phase Φ1 ends. During the reset phase Φ1, the charge stored in the capacitor 101 is q = C1 * VREF1. The charge stored in the capacitor 102 is q = C1 * VREF2.
[0013]
Next, the process proceeds to the sampling phase Φ2. The switch circuits 121, 122, 126, 130, 128, 132 are closed. The voltage of the input terminal 141 is stored in the capacitor 101 and the voltage of the input terminal 142 is stored in the capacitor 102 as electric charge. The charge of the capacitor 103 changes by an amount equal to the change in the charge of the capacitor 101. At the same time, the charge of the capacitor 104 changes by an amount equal to the change in the charge of the capacitor 102.
[0014]
As a result, the voltage of the output terminal 151 changes. In the sampling phase Φ2, the electric charge stored in the capacitance 101 is q = C1 * Vin1. The electric charge stored in the capacitance 102 is q = C1 * Vin2.
[0015]
Therefore, the change in the charge amount of the capacitor 101 after the change from the reset phase Φ1 to the sampling phase Φ2 is Δq = C1 * (Vin1−VREF1), and the change in the charge amount of the capacitor 102 is Δq = C1 * ( Vin2-VREF2).
[0016]
When the voltage Vin1 of the input terminal 141 is composed of the signal voltage Vinp and the offset voltage Vos, and the voltage Vin2 of the input terminal 142 is composed of only the signal voltage Vinn, the voltage of the output terminal 151 becomes
Vout =-(C1 / C2) * {(Vin1-Vin2)-(VREF1-VREF2)}
= − (C1 / C2) * {(Vinp + Vos−Vinn) − (VREF1-VREF2)}
= − (C1 / C2) * {(Vinp−Vinn) + (Vos− (VREF1−VREF2))}
Given by
[0017]
By adjusting VREF1 and VREF2 so that Vos = VREF1-VREF2,
Vout =-(C1 / C2) * (Vinp-Vinn), and the offset voltage Vos of the input signal Vin1 can be canceled.
[0018]
As described above, in the circuit system of the present invention, it is possible to amplify only the signal component by canceling the offset voltage of the input voltage.
[0019]
In this example, two reference voltages 111 and 112 are used, but one of the two reference voltages is replaced with a reference voltage as shown in FIGS. It is clear that the offset voltage of the input voltage can be canceled using the difference between the input voltages. For example, in the example of FIG. 3, the voltage of the output terminal 151 is
Vout = − (C1 / C2) * {(Vinp−Vinn) + (Vos−VREF)}
[0020]
By adjusting the reference voltage 111 to be equal to Vos, Vout = (C1 / C2) * (Vinp−Vinn), and the offset voltage Vos of the input signal Vin1 can be canceled.
[0021]
The reference voltage mentioned here is usually called analog ground, and is also connected to other switches. The output voltage swings around this reference voltage. In the above-described example, the calculation is performed with the reference voltage set to 0 V to simplify the description.
[0022]
The advantages of having two reference voltages as in FIG. 1 are as follows. For example, the reference voltage 111 is a reference voltage having no temperature characteristics, and the reference voltage 112 is assumed to have a temperature characteristic. In this way, when the offset voltage of the input voltage has a temperature characteristic, the temperature characteristic of the offset voltage of the input voltage is canceled by using the reference voltage 112 having the temperature characteristic, and the input voltage is changed by using the reference voltage 111. The absolute value of the offset voltage generated by applying the voltage offset voltage and the reference voltage 112 can be matched.
[0023]
As shown in FIG. 7, for two input voltages, a node that applies two reference voltages 111 and 112 is switched by a switch, so that the temperature correction of the polarity opposite to the polarity of the temperature characteristic of the reference voltage 112 can be performed. Will be possible. For example, assume that the reference voltage 112 in FIG. 7 has a negative temperature characteristic as shown in FIG. When the offset voltage of the input voltage has a positive temperature characteristic, the positive temperature characteristic of the offset voltage of the input voltage is canceled using the clock 1a as shown in FIG. Conversely, when the offset voltage of the input voltage has a negative temperature characteristic, the negative temperature characteristic of the offset voltage of the input voltage is canceled using the clock 1b as shown in FIG.
[0024]
The circuit of FIG. 7 can be used in a two-stage amplifier circuit configuration as shown in FIG. At this time, the temperature characteristic of the offset voltage of the input voltage is multiplied by the gain of the first-stage amplifier circuit. When the temperature characteristics of the offset voltage of the input voltage are smaller than the temperature characteristics of the reference voltage, the temperature characteristics can be easily matched by adopting such a two-stage amplification configuration.
[0025]
The switch used in the description of the present invention is constituted by an N-type MOSFET, a P-type MOSFET, or a CMOS transmission gate in which these two are connected in parallel.
[0026]
The circuit of FIG. 1 can be implemented in a fully differential circuit having two inputs and two outputs as shown in FIG. It is obvious that not only the circuit of FIG. 1 but also the circuit used in the description of the present invention can be implemented in a fully differential circuit having two inputs and two outputs similarly to the circuit of FIG. By using a fully differential circuit configuration, an effect of reducing common-mode noise can be obtained.
[0027]
The circuit in FIG. 6 is an example in which the switched capacitor amplifier circuit has a two-stage configuration and offset cancellation is performed in the second stage.
[0028]
The circuit shown in this embodiment is an example of a switched-capacitor amplifier circuit, and can be implemented in other types of switched-capacitor amplifier circuits.
[0029]
If the value of the offset voltage included in the input voltage is known in advance and the value is constant, the reference voltage may be a fixed voltage.If the value of the offset voltage included in the input voltage is unknown, the reference voltage is set to the input voltage. By using a variable voltage that can be adjusted in accordance with the offset voltage, the offset voltage can be adjusted while observing the output voltage.
[0030]
The following method is considered as one example of creating this adjustable variable voltage. A desired voltage can be obtained by connecting switches in parallel to some of the resistors constituting the resistance ladder obtained by dividing the power supply voltage between the power supply voltages and opening and closing the switches based on data written in the EEPROM.
[0031]
An electronic device having the above-described switched-capacitor amplifier circuit can operate accurately because signal noise is reduced.
[0032]
【The invention's effect】
By canceling the offset voltage of the input voltage, only the signal component can be amplified. When the offset voltage of the input voltage has a temperature characteristic, the offset voltage including the temperature characteristic can be canceled.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a switched capacitor amplifier circuit of the present invention.
FIG. 2 is a configuration diagram of a switched capacitor amplifier circuit of the present invention.
FIG. 3 is a configuration diagram of a switched capacitor amplifier circuit of the present invention.
FIG. 4 is a configuration diagram of a conventional switched capacitor amplifier circuit.
FIG. 5 is a configuration diagram of a switched capacitor amplifier circuit of the present invention.
FIG. 6 is a configuration diagram of a switched capacitor amplifier circuit of the present invention.
FIG. 7 is a configuration diagram of a switched capacitor amplifier circuit of the present invention.
FIG. 8 is an example of the temperature dependence of a reference voltage.
FIG. 9 shows a clock waveform used in the switched capacitor amplifier circuit of the present invention.
FIG. 10 is a configuration diagram of a switched capacitor amplifier circuit of the present invention.
[Explanation of symbols]
100 operational amplifiers 101, 102, 103, 104, 105, 106 capacitances 111, 112 reference voltages 123, 124 switch circuits 141, 142 input terminals 151, 152 output terminals

Claims (3)

第1の入力信号が入力される第1の入力端子と、
第2の入力信号が入力される第2の入力端子と、
前記第1の入力端子の出力に基づいた信号が入力される第1の容量と、
前記第2の入力端子の出力に基づいた信号が入力される第2の容量と、
前記第1の容量の出力に基づいた信号と前記第2の出力に基づいた信号を比較し、信号を出力する演算増幅器と、
前記第1及び第2の容量に電荷を供給する第1の参照電圧が印加される第1の参照電圧端子と、
前記第1及び第2の容量に電荷を供給する第2の参照電圧が印加される第2の参照電圧端子と、を有し、
前記第1の参照電圧と第2の参照電圧の電圧値の差が、前記第1の入力端子と前記第2の入力端子間のオフセット電圧に一致するように、前記第1又は2の参照電圧の一方又は両方を調整することを特徴とするスイッチトキャパシタ増幅回路。
A first input terminal to which a first input signal is input;
A second input terminal to which a second input signal is input;
A first capacitor to which a signal based on an output of the first input terminal is input;
A second capacitor to which a signal based on the output of the second input terminal is input;
An operational amplifier that compares a signal based on the output of the first capacitor with a signal based on the second output and outputs a signal;
A first reference voltage terminal to which a first reference voltage for supplying charges to the first and second capacitors is applied;
A second reference voltage terminal to which a second reference voltage for supplying a charge to the first and second capacitors is applied;
The first or second reference voltage such that a difference between the voltage values of the first reference voltage and the second reference voltage matches an offset voltage between the first input terminal and the second input terminal. A switched capacitor amplifier circuit that adjusts one or both of the following.
前記第1の参照電圧は温度特性を有し、
前記第1の入力端子と前記第2の入力端子間のオフセット電圧が温度特性を有する場合に、前記第1の参照電圧と第2の参照電圧の電圧値の差が、前記第1の入力端子と前記第2の入力端子間のオフセット電圧に一致するように、前記第1の参照電圧は温度特性を設定することを特徴とする請求項1に記載のスイッチトキャパシタ増幅回路。
The first reference voltage has a temperature characteristic;
When an offset voltage between the first input terminal and the second input terminal has a temperature characteristic, a difference between a voltage value of the first reference voltage and a voltage value of the second reference voltage is equal to the first input terminal. 2. The switched-capacitor amplifier circuit according to claim 1, wherein the first reference voltage sets a temperature characteristic so as to coincide with an offset voltage between the first reference voltage and the second input terminal.
請求項1ないし2に記載のスイッチトキャパシタ増幅回路を有することを特徴とする電子機器。An electronic apparatus comprising the switched capacitor amplifier circuit according to claim 1.
JP2003007857A 2003-01-16 2003-01-16 Switched capacitor amplifier circuit and electronic device Expired - Fee Related JP4094436B2 (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006070697A1 (en) * 2004-12-27 2006-07-06 Fab Solutions, Inc. Current measuring apparatus and current measuring method
JP2008104197A (en) * 2006-10-20 2008-05-01 Samsung Electronics Co Ltd Switched capacitor amplifier without dependency on variations in capacitance elements, and method for operating same
CN100386964C (en) * 2005-03-04 2008-05-07 清华大学 Amplifier of power supply by AC power supply in switch condenser circuit
JP2008534962A (en) * 2005-04-01 2008-08-28 フリースケール セミコンダクター インコーポレイテッド Device for detecting current
US7612699B2 (en) 2007-05-17 2009-11-03 Denso Corporation A/D converter circuit and A/D conversion method
WO2010004455A2 (en) * 2008-06-16 2010-01-14 Nxp B.V. A switched-capacitor pipeline adc stage
JP2017526247A (en) * 2014-07-11 2017-09-07 クゥアルコム・インコーポレイテッドQualcomm Incorporated Current sensing circuit using single operational amplifier with DC offset auto-zeroing

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006070697A1 (en) * 2004-12-27 2006-07-06 Fab Solutions, Inc. Current measuring apparatus and current measuring method
CN100386964C (en) * 2005-03-04 2008-05-07 清华大学 Amplifier of power supply by AC power supply in switch condenser circuit
JP2008534962A (en) * 2005-04-01 2008-08-28 フリースケール セミコンダクター インコーポレイテッド Device for detecting current
JP2008104197A (en) * 2006-10-20 2008-05-01 Samsung Electronics Co Ltd Switched capacitor amplifier without dependency on variations in capacitance elements, and method for operating same
US7612699B2 (en) 2007-05-17 2009-11-03 Denso Corporation A/D converter circuit and A/D conversion method
WO2010004455A2 (en) * 2008-06-16 2010-01-14 Nxp B.V. A switched-capacitor pipeline adc stage
WO2010004455A3 (en) * 2008-06-16 2010-02-25 Nxp B.V. A switched-capacitor pipeline adc stage
US8362939B2 (en) 2008-06-16 2013-01-29 Integrated Device Technology, Inc. Switched-capacitor pipeline ADC stage
JP2017526247A (en) * 2014-07-11 2017-09-07 クゥアルコム・インコーポレイテッドQualcomm Incorporated Current sensing circuit using single operational amplifier with DC offset auto-zeroing

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