JP3237517B2 - Delta-sigma data converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit configuration of a delta-sigma type data converter which suppresses deterioration of output characteristics caused by element variations and obtains a highly accurate output result.

[0002]

2. Description of the Related Art The characteristics of circuit elements (transistors, capacitors, resistors, etc.) on an LSI vary due to size variations due to processes. Particularly, in an analog circuit, the characteristic deterioration due to the variation is a serious problem. For example, in a filter including an operational amplifier, an offset of several mV occurs in the output due to element variation. When a signal with this offset is input to the delta-sigma type AD converter, the output has a direct current (0 Hz) or a specific frequency (f3,
..., fm). If this noise occurs in the signal band, the output characteristics will be significantly degraded. Conventionally, a method of applying dither has been adopted to solve this problem.

FIG. 5 shows an example of a conventional delta-sigma AD converter. In FIG. 5, 1 is dither, 3 is an integrator,
4 is a delay unit, 5 is a quantizer, and 7 is a filter. Here, 3 to 5 constitute the delta-sigma AD converter 2. An input signal 10 is connected to a first input of the integrator 3 and a dither 1 is connected to a second input. The output of the integrator 3 is
Connected to the quantizer 5. The output of the quantizer 5 is input to the filter 7 and to the integrator 3 via the delay unit 4. Then, the output of the filter 7 becomes the output signal 11.
Here, assuming that the maximum amplitude value of an external input signal is 1,
The relationship between the input of the quantizer 5, the comparison value, and the digital value is set as follows. The comparison value is set to -2/7, -1/32, 1/32, 2/7, and the amplitude value of the input signal to the quantizer 5 is 2/7 of the maximum amplitude value of the input signal. 1 or 2/7
1/7 when the value is less than 1/32 or more, 0 when the value is less than 1/32 and more than -1/32, less than -1/32 and -2 /
If the value is 7 or more, -1/7 is output as an input to the filter 7, and if it is less than -2/7, -1 is output.

Here, the circuit operation of the delta-sigma converter will be omitted. 6 and 7 show simulation results of the SN characteristic with respect to the input gain. FIG.
9 and FIG. 9 show simulation results of frequency characteristics at an input gain of -52 dBm0. FIG. 6 shows the SN characteristic of the delta-sigma AD converter when dither 1 is not applied. The SN characteristic deteriorates at a low input amplitude (around -52 dBm0). This is because, from FIG. 8, the specific frequency noise caused by the offset is within the band (the signal band is 10 Hz to 4 kHz).
This is because On the other hand, FIG. 7 shows the SN characteristic when dither 1 is applied, and there is no deterioration at a low amplitude as shown in FIG. The frequency characteristic at this time is shown in FIG. 9, and the power of the specific frequency noise is lower than that in FIG. These simulations are based on a sampling frequency of 768 kHz, offset 1 /
500, input signal frequency (f1) 1030Hz, dither signal amplitude 1
/ 32, the dither signal frequency is 500kHz. The filter 7 uses a BPF for removing signals of 10 Hz or less and 4 kHz or more.

[0005]

However, since the conventional circuit configuration requires dither, the number of elements constituting the circuit increases. Moreover, although the characteristic degradation due to the input offset can be improved by the dither, the characteristic degradation due to the element variation in the delta-sigma converter cannot be improved. For example, when the maximum input amplitude is 1 V, offsets of -0.005 to 0.005 occur in the operational amplifier of the integrator constituting the delta-sigma data converter due to element variations. When such an offset occurs, even if dither is added, the characteristics are degraded at a low input amplitude (around -50 dBm0) as shown in FIG. FIG. 10 is a simulation result of SN characteristics when dither is input at a systematic offset of 0.002.

The present invention has been made in view of the above-mentioned problems in the prior art, and does not require a dither circuit, intentionally applies DC to the input, shifts specific frequency noise out of a band, and is affected by element variations. It is intended to provide a difficult delta-sigma data converter.

[0007]

Means for Solving the Problems In order to solve the above-mentioned problems, a solution taken by the invention of claim 1 is to solve the problem by inputting an input signal .
A first filter for filtering, said first filter
A delta-sigma modulator for converting the output of the
A second filtering the output of the delta-sigma modulator
And a first filter, wherein the first filter comprises an operational amplifier.
Having a differential pair input transistor of the operational amplifier.
Asymmetric size or differential of the operational amplifier
The load of the pair input transistor in which a configuration you asymmetrically.

[0008]

A second aspect of the present invention provides an amplifier for amplifying an input signal, a delta-sigma modulator for converting the output of the amplifier, and a filter for filtering the output of the delta-sigma modulator. Wherein the amplifier has an operational amplifier, and the operational amplifier
Whether the size of the differential pair input transistor is asymmetric or
Alternatively, the load of the differential pair input transistor of the operational amplifier is made asymmetric.

A third aspect of the present invention provides a solution comprising a delta-sigma modulator and a filter for filtering an output of the delta-sigma modulator, wherein the delta-sigma modulator converts an input signal into a first signal. An integrator that receives the output of the DA converter as a second input and a quantizer that compares the output of the integrator with (n-1) reference values and converts the output into n digital data; includes the DA converter for converting the n outputs of the quantizer into n analog data, the output of the quantizer to the output of the delta-sigma modulator, n analog of the DA converter DC to data
And a DC adding means for adding

With the above configuration, DC can be applied to the input signal. Due to this DC, the specific frequency noise shifts out of the band, and the noise is improved by removing the noise with a filter. In this way, it is possible to prevent the output characteristics from deteriorating due to device variations.

[0012]

Embodiments of the present invention will be described below. The same components as those of the conventional delta-sigma data converter are denoted by the same reference numerals.

First, the basics of a delta-sigma type data converter
A configuration example will be described with reference to FIG . In the figure , 8 is an input signal 10
A DC adding means for adding a DC signal, 2 delta-sigma modulator for AD converting the output of the D C addition means 8, 7 is a filter for removing unwanted signals from the output of the delta-sigma modulator 2, the filter 7 The output is an output signal 11.

The DC adding means 8 operates between two reference voltages (Vref
An additional voltage Vo is generated by the voltage division of two resistors (R1, R2) connected to (1, Vref2), and DC (Vo) is added to the input signal by coupling with the capacitor C.

The delta-sigma modulator 2 has an integrator 3 having an output of the DC adding means 8 as a first input and an output of the delay unit 4 as a second input, and an output of the integrator 3 as (n- 1) A quantizer 5 for comparing with n reference data and converting it into n digital data, a first output of the quantizer 5 being an output of the delta-sigma modulator 2 and being delayed for a set time to a second output. Delay device 4
It is a first-order delta-sigma type including: Where n = 5
The relationship between the input of the quantizer 5, the comparison value, and the digital value is set as follows. The comparison value is set to -2/7, -1/32, 1/32, 2/7 with respect to the maximum amplitude value of the external input signal, and the amplitude value of the input signal to the quantizer 5 is set. Is greater than or equal to 2/7 of the maximum amplitude value of the input signal, 1 is less than 2/7 and 1/7 if the value is greater than 1/32, less than 1/32 and -1 /
0 if the value is 32 or more, -1/7 if the value is less than -1/32 and more than -2/7, and -1 if the value is less than -2/7. Output as input.

Hereinafter, the circuit operation will be briefly described. With the above configuration, the DC voltage (Vo) added to the input signal is (Equation 1)
It is represented as

[0017]

(Equation 1)

When this DC signal is input to the ideal delta-sigma modulator 2, a DC signal and a signal having a fixed pattern f2 represented by (Expression 2) are generated at the output. Here, fs is a sampling frequency.

[0019]

(Equation 2)

It is also assumed that specific frequency noise (f3, f4,..., Fm) is generated in the output of the delta-sigma modulator due to element variations. When DC is applied to the input signal in this state, the noise of f2 and (f3, f4, ..., fm) causes intermodulation. Then, the output of the delta-sigma modulator 2 is shown in FIG.
As shown in FIG. 1, apart from the input signal (f1 = 1030 Hz), (f3-f
2, f3 + f2,... Fm-f2, fm + f2). Here, the band is 10Hz-4kHz, fs = 768kHz, f2 = 107kHz
If z (Vo = 1/50 of the maximum amplitude of the input signal), all the specific frequency noise generated in the band can be shifted out of the band. The out-of-band noise and the DC component are removed by the filter 7. As a result, only the input signal component (f1) and its harmonics remain in the band as shown in FIG.
SN characteristics are improved. FIG. 13 shows that the integrator operational amplifier
According to the simulation result of the SN characteristic when an offset of 0 occurs, the characteristic at low amplitude (around -52 dBm0) is improved by 10 dB from 15 dB to 25 dB by applying DC. Also, FIG.
(1/50) is the offset dependence of the integrator operational amplifier at an input gain of -52 dBm0. From FIG. 15, the range (−0.05 to 0.005) wider than the offset value (−0.005 to
18 to 0.02), a good result without deterioration of the SN characteristic can be obtained.

As described above, it is possible to obtain a delta-sigma type data converter which is hardly affected by element variations due to a slight increase in elements.

[0022]

[0023] (Embodiment 1) Next, a delta-sigma data converter according to a first embodiment of the present invention will be described with reference to FIG. In FIG. 1 , reference numeral 6 denotes a first filter for filtering an input signal 10;
Is a delta-sigma modulator for AD-converting the output of the filter 6, and 7 is a filter for filtering the output of the delta-sigma modulator 2, and the output of the filter 7 is an output signal 11.

The delta-sigma modulator 2 includes an integrator 3 having an output of the first filter as a first input and an output of the delay unit 4 as a second input, and an output of the integrator 3 as (n-1). ) Quantizer for comparing with n reference values and converting into n digital data
5 and a first-order delta-sigma type including a delay unit 4 which uses the first output of the quantizer 5 as the output of the delta-sigma modulator 2 and delays the second output for a set time.

The first filter 6 includes an operational amplifier 2
0, the inverting input terminal and the output terminal of the operational amplifier 20 are connected, the capacitor C1 is connected between the non-inverting input terminal of the operational amplifier 20 and the ground, and the inverting input terminal and the input signal 10 are connected.
, Resistors (R1, R2) are connected in series, a capacitor (C2) is connected between the connection point of the resistors (R1, R2) and the output terminal of the operational amplifier 20, and the output terminal of the operational amplifier 20 is connected The first and second input transistors T which constitute the output of the filter 6 and constitute the inverting and non-inverting input terminals of the operational amplifier 20
The sizes of r1 and Tr2 are made asymmetric, and a DC signal is applied to the input signal. FIG. 14 shows a circuit configuration of the operational amplifier 20. Here, Tr3 and Tr4 are load transistors, I
b is a current source, Vdd is a reference voltage, I1 and I2 are currents flowing through the transistors Tr1 and Tr2, respectively. The quantizer 5 shown in FIG. 2 is used.

Hereinafter, the circuit operation will be briefly described. If a MOS transistor is used as the input transistor, the gate
The source-to-source voltage Vgs is simply expressed as (Equation 3) in the saturation region.

[0027]

(Equation 3)

Here, Id is the drain current, Cox is the gate oxide film capacity, L is the gate length, W is the gate width, Vt is the threshold, and μn is the electron mobility. Assuming that the transistor sizes of Tr1 and Tr2 are (W1, L1) and (W2, L2), the systematic offset voltage Vo of the operational amplifier 20 is expressed as (Equation 4). With this Vo, DC can be added to the input signal 10.

[0029]

(Equation 4)

[0030] Here, by using a 1/50 to become the transistor size of the maximum amplitude of the input signal, SN characteristics are improved as well as FIG. Here, the filter 6 is always necessary when configuring a digital sigma converter, and in this embodiment, the circuit scale does not increase at all.

The order, DC value, reference value and output value of the quantizer of the delta-sigma modulator used in the present embodiment are not limited to specific examples. Also, the filter 7 is not limited to the present embodiment, and any filter that includes an operational amplifier and can be made asymmetrical in the size of a device used for the input of the operational amplifier is within the scope of the present invention. Therefore, it is possible to suppress the deterioration of the output characteristics without increasing the number of new elements. Therefore, the present invention greatly contributes to improving the accuracy of the delta-sigma type data converter on the LSI and obtaining a high yield, and is extremely useful.

(Embodiment 2 ) Next, a delta-sigma type data converter according to Embodiment 2 of the present invention will be described with reference to FIG. In FIG. 3, reference numeral 9 denotes an amplifier for amplifying an input signal 10;
A delta-sigma modulator 7 for D-conversion is a filter for removing unnecessary signals from the output of the delta-sigma modulator 2, and the output of the filter 7 is used as an output signal 11.

The delta-sigma modulator 2 includes an integrator 3 having an output of the first filter as a first input and an output of the delay unit 4 as a second input, and an output of the integrator 3 at (n-1). ) Quantizer for comparing with n reference values and converting into n digital data
5 and a first-order delta-sigma type including a delay unit 4 which uses the first output of the quantizer 5 as the output of the delta-sigma modulator 2 and delays the second output for a set time.

Further, the amplifier 9 is provided with an operational amplifier 21 connects the non-inverting input terminal of the operational amplifier to the input signal 10 is connected to the inverting input terminal of the operational amplifier 21 and the output terminal, the output terminal A buffer amplifier that outputs the input signal 10 to the output of the amplifier as the output of the amplifier, and makes the sizes of the first and second input transistors Tr1 and Tr2 constituting the inverting and non-inverting input terminals of the operational amplifier 21 asymmetric. , A DC signal is applied to the input signal. Here, the operational amplifier 21 described in the second embodiment is used, and the quantizer 5 described in FIG. 2 is used.

Hereinafter, the circuit operation will be briefly described. If a MOS transistor is used as the input transistor, the gate
The source-to-source voltage Vgs is simply expressed as (Equation 3) in the saturation region, and the systematic offset voltage of the operational amplifier 21 is obtained.
Vo is represented as (Equation 4). This Vo makes the input signal
DC can be added to 10.

[0036] At this time, by using a 1/50 to become the transistor size of the maximum amplitude of the input signal, SN characteristics are improved as well as FIG. Here, in a system in which an amplifier is used before the delta-sigma converter, it is possible to obtain a delta-sigma AD converter that is hardly affected by element variations without increasing the circuit scale.

The order, DC value, reference value and output value of the quantizer of the delta-sigma modulator used in the present embodiment are not limited to specific examples. Further, the amplifier is not limited to the present embodiment, and any amplifier that includes an operational amplifier and can be asymmetric in size of a device used as an input of the operational amplifier is within the scope of the present invention. Therefore, it is possible to suppress the deterioration of the output characteristics without increasing the number of new elements. Therefore, the present invention greatly contributes to improving the accuracy of the delta-sigma type data converter on the LSI and obtaining a high yield, and is extremely useful.

Third Embodiment Next, a delta-sigma data converter according to a third embodiment of the present invention will be described with reference to FIG. In FIG. 4, reference numeral 2 denotes a delta-sigma modulator for AD-converting the input signal 10, and reference numeral 7 denotes a filter for removing unnecessary signals from the output of the delta-sigma modulator 2.

The delta-sigma modulator 2 includes an integrator 3 having a first input as an input signal 10 and an output of a DA converter 44 as a second input, and (n-1) outputs of the integrator 3 It has a quantizer 5 for comparing with a comparison value and converting it into n digital data, and a DA converter 44 for converting n digital data into n analog data. The output of the quantizer 5 is delta-sigma modulated. It is a first-order delta-sigma type output from the detector 2.

The DA converter 44 includes a logic circuit 43, a switch array 42, a DC addition means 41, and a reference voltage generation circuit 40. The DC addition means 41 converts the n reference values of the reference voltage generation circuit 40 into n reference values. The logic circuit 43 controls ON and OFF of n switches included in the switch array 42 by digital data output from the quantizer 5, and outputs one of the n switches. The outputs are connected to the outputs of the n DC adding means, and the other is used as the output of the DA converter 44. When the n-th switch is turned on, a value obtained by adding DC to the n-th reference value appears in the output of the DA converter 44. Here, n = 5, the maximum amplitude value of the external input signal is 1, and the comparison value of the quantizer 5 is -2/7, -1/3.
2, 1/32, 2/7, digital value "010", "001", "000", "10"
The relationship between the input, the comparison value, and the digital value is set as follows, where "1" is set to "110", and "010" is set if the amplitude value of the input signal to the quantizer 4 is 2/7 or more. If the value is less than 2/7 and greater than or equal to 1/32, "001"; if the value is less than 1/32 and greater than or equal to -1/32, then "000"; If the value is -2/7 or more, filter "101". If it is less than -2/7, filter "111".
Output as input.

The DC value of the DC adding means 41 is Vo = 1/50, and the reference values of the reference voltage generating circuit 40 are "-1", "-1/7", "0", "1 /".
7 "and" 1 ", the relationship between the input data and the output of the DA converter 44 is set as follows: When the input of the digital data to the logic circuit 43 is" 010 ", (1 + 1/50) ) For "001"
(1/7 + 1/50), if "000", (1/50), if "101", (-1 / 7 + 1/50), if "110", Outputs (-1 + 1/50).

The DC adding means 41 converts the input signal into a DC signal.
(Vo) is equivalent to that the applied, similarly to FIG. 2 S
N characteristics can be improved.

In the present embodiment, a DC adding means is newly provided, but this can be realized by slightly increasing the number of elements. In this manner, a delta-sigma data converter that is less affected by element variations can be obtained.

In this embodiment, a delta-sigma AD converter is described as an example, but the present invention can be applied to a DA converter. Further, specific examples of the order, DC value, quantizer reference value, and output value of the delta-sigma modulator used in the present embodiment are not limited. Furthermore, although a DC addition circuit is newly provided, this circuit can be realized by a simple circuit. Therefore, the present invention increases the accuracy of the delta-sigma type data converter on the LSI with a small increase in the number of elements, greatly contributes to obtaining a high yield, and is extremely useful.

(Embodiment 4 ) The overall configuration of this embodiment is the same as that of Embodiment 1 or Embodiment 1.
2 , the difference being that the load on the differential pair input transistors of the operational amplifier is asymmetric. Hereinafter, the circuit operation will be briefly described.

When a MOS transistor is used as a load transistor, currents (I1, I2) flowing through the transistors (Tr3, Tr4)
Is determined by the transistor size ratio and the current source Ib. Here, assuming that the gate length of the MOS transistor is constant and the gate width is 1: (n-1), the current becomes (Equation 5).

[0047]

(Equation 5)

Then, the differential input transistors (Tr1, Tr2)
When a MOS transistor is used, the systematic offset voltage Vo of the operational amplifier 20 is expressed as (Equation 6).

[0049]

(Equation 6)

With this Vo, DC can be added to the input signal 10. Here, 1 / of the maximum amplitude of the input signal
By using a transistor size of 50, FIG.
As in 2 , the SN characteristics are improved.

Although the size of the input transistor is limited to asymmetric in the present embodiment, it can be symmetric. Further, the operational amplifier is not limited to the present embodiment, and any device (for example, a resistor or the like) capable of making the load of a device used for the input of the operational amplifier asymmetric is within the scope of the present invention. Therefore, the present invention greatly increases the accuracy of the delta-sigma type data converter on the LSI without increasing the number of circuit elements, greatly contributes to obtaining a high yield, and is extremely useful.

[0052]

As described above, according to the configuration of the delta-sigma type data converter of the present invention, DC is applied to the input signal, and the specific frequency noise generated in the delta-sigma modulator is shifted out of the band and removed by the filter. By doing so, it is possible to realize a delta-sigma type data converter that is less affected by element variations.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a delta-sigma type data converter according to a first embodiment of the present invention.

FIG. 2 shows a basic configuration example of a delta-sigma data converter.
To diagram

FIG. 3 is a configuration diagram of a delta-sigma type data converter according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a delta-sigma data converter according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a conventional delta-sigma data converter.

FIG. 6 is an SN characteristic diagram when an input has an offset.

FIG. 7 is an SN characteristic diagram when an input has an offset and a dither.

FIG. 8 shows that the input signal level when no dither is applied is-
Frequency characteristic diagram at 51 dBm0

FIG. 9 shows that the input signal level when dither is added is −51d
Frequency characteristic diagram at Bm0

FIG. 10 is an SN characteristic diagram when a systematic offset occurs in the operational amplifier of the integrator.

FIG. 11 is a frequency characteristic diagram of the output of the delta-sigma modulator when DC is applied to the input.

FIG. 12 is a frequency characteristic diagram after a DC is applied to an input and an output of a delta-sigma modulator is filtered.

FIG. 13 is a frequency characteristic diagram when DC is applied to the input.

FIG. 14 is a circuit diagram of an operational amplifier.

FIG. 15 is a characteristic diagram showing the offset dependence of the integration operational amplifier of SN when DC is applied.

[Explanation of symbols]

 2 Delta-sigma modulator 3 Integrator 4 Delayer 5 Quantizer 6 Filter 7 Filter 9 Amplifier 10 Input signal 11 Output signal 20 Operational amplifier 21 Operational amplifier 40 Reference voltage generating circuit 41 DC adding means 42 Switch train 43 Logic circuit 44 DA converter

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-245717 (JP, A) JP-A-4-302222 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 3/02

Claims (3)

(57) [Claims] A first filter for filtering an input signal; a delta-sigma modulator for converting the output of the first filter into data; and a second filter for filtering an output of the delta-sigma modulator. , The first
Wherein the filter has an operational amplifier, and the differential pair input transistor of the operational amplifier has an asymmetric size, or the differential pair input transistor of the operational amplifier has an asymmetric load. Type data converter. 2. An amplifier for amplifying an input signal, a delta-sigma modulator for converting the output of the amplifier into data, and a filter for filtering the output of the delta-sigma modulator, wherein the amplifier has an operational amplifier. A delta-sigma data converter, wherein the size of the differential pair input transistor of the operational amplifier is asymmetric, or the load of the differential pair input transistor of the operational amplifier is asymmetric. 3. A delta-sigma modulator, comprising: a filter for filtering an output of the delta-sigma modulator;
The delta-sigma modulator compares an output of the integrator with (n-1) reference values and an integrator having an input signal as a first input and an output of a DA converter as a second input. a quantizer for converting the digital data into n digital data, and the DA for converting the n outputs of the quantizer into n analog data
A delta-sigma type data comprising: a converter; an output of the quantizer being an output of the delta-sigma modulator; and DC adding means for adding DC to n pieces of analog data of the DA converter. converter.