JPS59116997A - Sample holding circuit - Google Patents

Abstract

PURPOSE:To enable use of a low-performance amplifier and high speed operation and facilitate integration by making a circuit configuration that can obtain an output from which influences of offset of the amplifier is cancelled at the time of holding. CONSTITUTION:When sampling, switches S41, S42 are closed and a switch 43 is opened. When an input signal Vin is applied to an input terminal 41, a capacitor C41 is charged to charging voltage Vc=Vin-VOS41 when offset voltage of an amplifier A41 is VOS41. At this time, a non-inversion input terminal of the amplifier A41 works as a non-inversion amplifier of gain 1 connected to common, and output Vout from a terminal 43 becomes equal to VOS41. On the other hand, when holding, switches S41, S42 are opened and the switch S43 is closed. Output voltage at this time becomes Vout=Vc+VOS41. Substituting this in the foregoing equation it becomes Vout=Vin-VOS41+VOS41=Vin. Offset portion is cancelled and does not appear in output.

Description

DETAILED DESCRIPTION OF THE INVENTION A/l) Sample-hold, which is often used in the input section of a converter, holds and outputs a value corresponding to an input signal applied during a sample period during a hold period. It concerns circuit improvements.

1 to 6 are electrical circuit diagrams showing conventional sample and hold circuits.

Figure 1 shows an inverting one-sample hold circuit, Figure 2 shows a non-inverting sample-and-hold circuit, and Figure 3 shows a sample-and-hold circuit using the method shown in Figure 2 with a manual buffer added. .

A common problem with these is that the sample/hold circuit output is connected to an amplifier (All, A21. A31. A32
An example of this is that errors occur due to offsets such as For example, in Fig. 3, the input signal voltage of amplifier A31 is Vin, the input offset voltage is vos3□
Then, the sample-and-hold circuit output is expressed as Vout w Vin -Vos31 , and an error corresponding to the offset appears in the output during sampling and holding.

As mentioned above, in order to obtain sufficient accuracy using a sample-and-hold circuit configured to produce υ errors due to amplifier offset, an expensive amplifier with a small offset voltage and its temperature coefficient is required. There was a problem. Furthermore, it is difficult to integrate such a high-performance amplifier and a switch circuit into one unit, and for this reason, there has been no sample-and-hold IC that is simple and has good performance.

The present invention aims to solve the above-mentioned problems, and aims to realize a sample-and-hold circuit in which the offset of the amplifier does not appear as an output error even when a low-performance amplifier is used.

In order to achieve the above object, the first gist of the present invention is to provide an input terminal to which an input signal is applied, a first switch having one end connected to the input terminal, and a first switch other than the first switch. a capacitor having one end connected to its one end; an inverting amplifier having the other end connected to its input terminal; a second switch connecting the output terminal of the inverting amplifier to the input terminal; a third switch connected to the output terminal and the one end of the capacitor, the first and second switches are closed during the sample period, the sixth switch is opened, and the third switch is connected to the one end of the capacitor during the hold period. The sample and hold circuit has first and second switches open and the third switch closed.

The second gist of the present invention is an input terminal to which an input signal is applied, a first switch having one end connected to the manual input terminal, and a first switch having the other end connected to the input terminal. a first buffer; a capacitor having one end connected to the output terminal of the first buffer; an inverting amplifier having the other end connected to its input terminal; and an output terminal of the inverting amplifier and the input terminal connected to each other; a second switch connected to the output terminal of the inverting amplifier; a first sample bold circuit connected to the output terminal of the inverting amplifier; and an output terminal of the first sample hold circuit and the input terminal of the first buffer. and a third switch to connect the first and second switches, and during the sample period, the first and second switches are closed, the fifth switch is opened, and the first sample
A sample hold in which the hold circuit is set in a hold mode, the first and second switches are opened during the hold period, the third switch is closed, and the first sample and hold circuit is set in the sample mode. It exists in the circuit.

The present invention will be explained below based on the drawings.

FIG. 4 is an electrical circuit diagram showing one embodiment of the present invention. 4
An input terminal to which an input signal voltage is applied, S41, is a first switch whose one end is connected to this input terminal 41, C41.
is a charging capacitor whose one end is connected to the other end of this first switch S41, A41 is an operational amplifier whose other end is connected to its inverting input terminal and is used as an inverting amplifier, and S42 is this operational amplifier. A second switch connected to the output terminal 43 of A41 and the inverting input terminal; S43 is connected to the output terminal 4 of the operational amplifier A42;
3 and the one end of the capacitor C41.
The switches 42 are the respective switches 841.342.
This is an S/H command terminal to which an S/H (sample and hold) command signal for controlling S43 is applied.

At sample time, switch 341. When the input signal vin is applied to the input terminal 41 with S42 closed and switch 843 open, the offset voltage of amplifier A41 becomes VoS41.
At this time, the capacitor C41 is charged to a charging voltage of Vc = Vin - Vos41 (+). At this time, the non-inverting input terminal of the amplifier A41 functions as a non-inverting amplifier with a gain of 1 connected to the common, and the output from the terminal 43 becomes ■□utkevout=■0841(2).

On the other hand, when holding, switches 841 and 342 are open, and switch 843 is closed, and when sampling, capacitor C41
K charged charging voltage V. The voltage obtained by adding the offset vos41 of the amplifier A41 and the offset vos41 of the amplifier A41 is also outputted from the output terminal 43 as Vout. That is, the output voltage at this time is Vout = Vc + Vos41 (3). (
Substituting equation (1) into equation (3), Vout = Vin
-Vos + Vos = Vin
(+)41 41 , and the offset is canceled and does not appear in the output.

Figures 5 (1) to (4) show time charts of each part of the sample-and-hold circuit in Figure 4, when the input signal Vin is changing from Vin (1) to Vin (2). It shows the pattern.

According to the sample-and-hold circuit configured as above,
There is an advantage of 75g that an output can be obtained in which the influence of amplifier offset is canceled during hold. Even though an inverting amplifier is used, 11 inverting outputs can be obtained. Furthermore, since it is easy to use a high-speed inverting amplifier, a high-speed sample-and-hold circuit can be realized. In addition, 61 usable 1. Since it is not affected by , O, Y, 1°, it is easy to integrate it into an IC or the like.

FIG. 6 shows a second embodiment of the present invention, which is similar to the first embodiment (fourth embodiment).
In place of the amplifier A41 in the figure, an 0MO8 logic element A61 is used.

Components that are the same as those in FIG. 4 are designated by the same reference numerals, and their explanation will be omitted. In this case, the threshold voltage of the inverter A61 acts as an offset, but this is also canceled in the same way as described above, so it does not affect the output voltage Vout during hold.

Its features are also similar to those of the first embodiment.

FIG. 7 is an electrical circuit diagram showing a modification of the embodiment shown in FIG. 6. By dividing the output of inverter A61 through resistors R71 and R72 and feeding it back, a gain of G + R71 + R72 is obtained. (In the figure, S/
(H command signal circuit omitted).

FIG. 8 is an electrical circuit diagram showing a third embodiment of the present invention.
This is the circuit shown in the figure except that a buffer is provided on the input side and a first sample-and-hold circuit is provided on the output side. Components that are the same as those in FIG. 6 are designated by the same reference numerals and their explanation will be omitted.

Ag3 is a first buffer, SH, whose input is connected to the first switch S41 and whose output is connected to the capacitor C41.
The first sample-and-hold circuit S82 whose input terminal is connected to the output terminal of the inverter 61 is a fifth switch to which the output terminal of the first sample-and-hold circuit S82 is connected. The sample and hold circuit 5
In 1ll, S81 is a switch whose one end is connected to the output terminal of the inverter A61, C81 is a holding capacitor whose one end is connected to the other end of the switch 881 and the other end is connected to common, and A82 is a switch whose input terminal is connected to the common terminal. A second buffer connected to the other end of the switch 881 outputs its output as Vout, and the switch 881
Connect to B2.

During sampling, switch S41. S42 closes and switch 381.882 opens. The capacitor C41 is charged via the input signal Vin buffer A81. The sample-and-hold circuit 5ill is in the hold mode. Since the capacitor C81 holds the charging voltage charged during the previous hold, this is outputted as V out via the buffer A82. In addition, buffer A81
and A82 may be a simple source follower table or the like.

During hold, switches 841 and 842 open and switches 381 and 882 close, so Vout is determined based on the voltage charged in capacitor C41 during the previous sample.
is output, and at the same time, the holding capacitor C81 is also charged in the sample-and-hold circuit SHI in the sample mode.

Figure 5 (5) shows a time chart of the output of the sample and hold circuit in Figure 8.Due to the function of the sample and hold circuit SHI, when the output Vout changes from the sample period to the hold period No ripple occurs in the output, and output without offset errors can be obtained at all times. Furthermore, the presence of the input buffer A81 prevents the settling time of the output Vout from changing due to the input signal source impedance. Other features are similar to the embodiment shown in FIG.

In the embodiment shown in FIG. 8, only either the input buffer A81 or the sample-and-hold circuit SH1 may be used if necessary.

As described above, according to the present invention, it is possible to realize a sample-and-hold circuit with a simple configuration in which even if a low-performance amplifier is used, the offset of the amplifier does not appear as an output error.

In addition, since it is an inverted type, it has excellent advantages such as high-speed operation and easy integration.

[Brief explanation of the drawing]

FIGS. 1 to 3 are electric circuit diagrams showing a conventional single hold circuit, FIG. 4 is an electric circuit diagram showing a first embodiment 1 of the present invention, and FIGS. ) is a time chart for explaining the operation of the circuit in FIG. 4, FIG. 5 (5) is a time chart for explaining the operation of the circuit in FIG. 8, and FIG. 6 is a time chart for explaining the operation of the circuit in FIG. FIG. 7 is an electric circuit diagram showing an example of the circuit shown in FIG. 6, and FIG.
The figure is an electrical circuit diagram showing a third embodiment of the present invention. 41...Input terminal, Vin...Input signal, 841.
842.843°882...Switch, C41...
Capacitor, A41. A61...Inverting amplifier, 5J
II...Sample/hold circuit, A81°゛°nofa.

Claims (1)

[Claims] (1) An input terminal to which an input signal is applied, a first switch to which one end is connected to the input terminal, a capacitor to which the other end of the first switch is connected; an inverting amplifier to which the other end of the capacitor is connected to its input terminal; a second switch to connect the output terminal of the inverting amplifier to the input terminal; and the output terminal of the inverting amplifier to the one end of the capacitor. and a third switch connected, during the sample period, the first and second switches are closed and the third switch is open, during the hold period, the first and second switches are open, and the A sample and hold circuit in which the third switch is closed. (2) The sample-and-hold circuit according to claim 1, which uses an inverter as an inverting amplifier. (5) an input terminal to which an input signal is applied; a first switch having one end connected to the input terminal; a first buffer having the other end connected to the input terminal; a capacitor having one end connected to the output terminal of the buffer; an inverting amplifier having the other end connected to the input terminal of the capacitor; a second switch connecting the output terminal of the inverting amplifier to the input terminal; a first sample-and-hold circuit connected to the output terminal of the inverting amplifier; and a third switch connected to the output terminal of the first sample-and-hold circuit and the input terminal of the first buffer. During the sample period, the first and second switches are closed, the third switch is opened, and the first sample-and-hold circuit is placed in a hold mode, and during the hold period, the first and second switches are closed. A sample-and-hold circuit in which the second switch is opened, the third switch is closed, and the first sample-and-hold circuit is set in a sample mode. (4) The sample-and-hold circuit according to claim 3, which uses an inverter as the inverting amplifier.