JPH05152959A - A/d conversion circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale and power consumption and to improve the conversion accuracy by incorporating a required circuit or the like. CONSTITUTION:A serial parallel A/D converter circuit is made up of a 1st sample-and-hold circuit 1, a 1st A/D converter circuit 2, an arithmetic operation circuit 7 applying subtraction processing to an output of the circuit 1 and an output of the circuit 2 subject to D/A conversion and a 2nd A/D converter circuit 6 converting the output of the circuit 7. A switch 703 and a capacitor 704 of the circuit 7 sample an analog signal, and an A/D converter circuit having capacitors 711-71n whose capacitance ratio is 2's power connected in common to an inverting input terminal of an operational amplifier 709 converts the sampled analog signal into nc-bit digital signal. Then D/A converter processing and subtractor processing are implemented by using the operational amplifier 709 and one capacitor 707 and the analog arithmetic operation circuit incorporates each circuit. Thus, the circuit scale and power consumption are saved and the conversion accuracy is enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital conversion circuit, and more particularly to a serial / parallel type analog / digital conversion circuit.

[0002]

2. Description of the Related Art A conventional serial-parallel type analog-to-digital conversion (hereinafter referred to as "A / D conversion") circuit is a first sample-and-host for sampling an input signal as shown in FIG.
Field (hereinafter referred to as S / H) circuit 1 and the upper nc bits of the sampled analog voltage
First A / D conversion circuit 2 for digital conversion and first S / D conversion circuit 2
The conversion result of the second S / H circuit 3 which again samples and holds the output voltage of the / H circuit and the first A / D conversion circuit 2 is converted to digital / analog (hereinafter referred to as D / A conversion). Nc bit D / A conversion circuit 4, a subtraction circuit 5 for taking the difference between the output of the D / A conversion circuit 4 and the output of the second S / H circuit, and the lower nf bits from the subtraction result of the subtraction circuit 5. And a second A / D conversion circuit 6 for A / D conversion. The outputs of the first A / D conversion circuit 2 and the second A / D conversion circuit 6 are data of n = nc + nf bits.

The first A / D conversion circuit 2 and the second A / D conversion circuit
The conversion circuit 6 is composed of, for example, a parallel type A / D converter as shown in FIG. Input signal is N1 (N1 = 2, n1)
N1-1 number of correlators 211 to 211 whose reference voltage is the voltage divided by the series of resistors 201 to 20N1
21 (N1-1) converts it into a digital value, and the encoder 22 converts it into Nc-bit data.

The D / A conversion circuit 4 has resistors 401 to 40N1 and switches 411 to 4 as shown in FIG.
1 (N1-1), buffer amplifier 41 and decoder 42
Composed of. The subtraction circuit 5 is composed of resistors 51 to 54 and an operational amplifier 55 as shown in FIG. 7, for example.

[0005]

However, in the above-mentioned conventional serial-parallel type A / D conversion circuit, an operational amplifier is required for each of the D / A conversion circuit, the subtraction circuit and the S / H circuit. There is a problem that the required area becomes extremely large. Further, since the D / A conversion circuit uses voltage division by a resistor string, the D / A conversion accuracy is limited by the resistance ratio, and there is a problem that it is difficult to obtain an accuracy of 8 bits or more.

The present invention has been made in view of such problems, and in a serial / parallel type A / D conversion circuit, the circuit scale and power consumption can be reduced and the conversion accuracy can be further improved. It is an object to provide a D conversion circuit.

[0007]

An A / D conversion circuit according to the present invention comprises a first sample-and-hold circuit for sampling and holding an input signal, and an output of the first sample-and-hold circuit. A first analog / digital conversion circuit for converting the voltage into nc-bit digital data; and a second sample-and-hold circuit for sampling and holding the output voltage of the first sample-and-hold circuit. An nc-bit digital / analog conversion circuit for converting the output data of the first analog / digital conversion circuit into an analog signal, an output signal of the second sample and hold circuit and the digital / analog conversion An analog circuit having a subtraction circuit for taking a difference between output signals of the circuit and a second analog / digital conversion circuit for converting the output signal of the subtraction circuit into nf-bit digital data. In the digital / analog conversion circuit, the second sample-and-hold circuit has capacitors and switches, and the digital / analog converter circuit has nc capacitors and switches in which the ratio of the values of the capacitors is a power of two. One end of each of the nc capacitors of the digital / analog conversion circuit is connected to a reference potential or a ground potential corresponding to the output data of the first analog / digital conversion circuit, and the subtraction circuit is provided. Is a charge addition type subtraction circuit which receives the output of the second sample and hold circuit and the output of the digital / analog conversion circuit.

[0008]

In the A / D conversion circuit according to the present invention, the S / D circuit is composed of capacitors and switches, and the capacitors are composed of nc capacitors and switches whose ratio of the values of the capacitors is a power of two. By the D / A conversion circuit and the charge addition type subtraction circuit composed of one capacitance and one operational amplifier circuit, the S / H
The circuit, D / A conversion circuit and subtraction circuit can be integrally configured. Therefore, the required number of operational amplifiers in the S / H circuit, the D / A conversion circuit and the subtraction circuit is one, which simplifies the configuration and reduces the occupied area and power consumption in the conventional serial-parallel type.
It can be reduced to 1/3 or less of that of the / D conversion circuit. Further, since the capacitance series is used as the D / A conversion circuit, it is possible to improve the relative accuracy more than the D / A conversion circuit using the resistance series, and it is possible to further reduce the power consumption. ..

[0009]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1A is a block diagram showing an A / D conversion circuit according to the first embodiment of the present invention. This A / D
The analog input signal to the conversion circuit is input from the input terminal 8 to the first
Is input to the S / H circuit 1. The output of the first S / H circuit 1 is converted into a nc-bit digital value by the first A / D conversion circuit 2. The output of the first S / H circuit 1 and the first A
The output of the / D conversion circuit 2 is input to the arithmetic circuit 7. In the arithmetic circuit 7, the output of the first S / H circuit 1 is sampled again, and the output of the first A / D conversion circuit 2 is converted into an analog signal. Further, in the arithmetic circuit 7, the difference between the value obtained by re-sampling the output of the first S / H circuit 1 and the value obtained by converting the output of the first A / D conversion circuit 2 into an analog signal is output. .. The second A / D conversion circuit 6 converts the output voltage of the arithmetic circuit 7 into a digital value of nf bits. By the above circuit, the analog input signal input from the input terminal 8 is converted into a digital value of nc + nf bits.

The arithmetic circuit 7 comprises a sample-and-hold circuit,
It has three functions of D / A conversion and calculation, and is specifically configured as shown in FIG. The analog signal is applied to the input terminal 700 and is sampled by the capacitor 704 when the switch 703 is on. Capacity 704
Is connected to the inverting input terminal of operational amplifier 709 when switch 705 is on. The other input terminal of the operational amplifier 709 is grounded. A capacitor 709 and a switch 706 are connected in parallel between the inverting input terminal of the operational amplifier 709 and the output terminal 701. Capacity 711-
One of the electrodes of 71 nc is commonly connected to the inverting input terminal of the operational amplifier 709, and the other of the electrodes is connected to the switch 7 respectively.
Ground or reference voltage input terminal 7 via 21 to 72 nc
It is designed to be connected to 08. Capacity 711-71
The value of each capacitance of nc is C / 2, C / (2 squared), C /
(2 to the power of 3) ... C / (2 to the power of nc)
It is set to be a power of two ratio. Switches 721 to 72nc are arithmetic circuit digital input terminals 702.
ON / OFF is controlled by the signal.

Next, with respect to the operation of the analog / digital conversion circuit having the above-mentioned configuration, Α /
The operation will be described with reference to the timing chart showing the operation of the entire D conversion circuit. As shown in FIG. 1B, the analog signal input from the input terminal 700 in the first phase is sampled by the capacitor 704 through the switches 703 and 705, and at the same time, one of the electrodes of the capacitors 711 to 71nc is A switch 72 that is commonly connected to the inverting input terminal of the operational amplifier 709 and has the other of the electrodes operated by a digital input signal.
1 to 72 nc are grounded respectively. Further, the integrating capacitor 707 connected between the inverting input of the operational amplifier 709 and the output terminal is short-circuited by the switch 706 and discharged.

Next, when the second phase is reached, the switch 70
3, 705 switches, and in the first phase, the capacitance 70
The electric charge accumulated in 4 is inverted at the electrode and the integration capacitor 707
Transferred to. Further, the switch 721 corresponds to the nc-bit digital value which is the output of the first A / D conversion circuit 2.
.About.72 nc are connected to the reference voltage terminal 708, and charges are transferred from the capacitors 711 to 71 nc to the integrating capacitor 707, respectively. Since the switch 706 is released, the charges transferred from the capacitor 704 and the capacitors 711 to 71nc are added and accumulated in the integrating capacitor 707, and the charge accumulated in the capacitor 707 and the capacitance of the capacitor 707 are accumulated in the output terminal 701. The voltage determined by the value is output.

FIG. 3 shows A / A according to the second embodiment of the present invention.
It is a block diagram which shows a D conversion circuit. The blocks having the same functions as those in the first embodiment are designated by the same numbers. In the second embodiment, the arithmetic circuit 7 in the first embodiment is used.
The output of is sampled and held again by the arithmetic circuit 9, and D
/ A conversion and calculation are performed, and the result is converted into n1 bit digital data by the A / D conversion circuit 10. As a result, the input analog signal can be converted into a digital value of nc + nf + n1 bits, and a high-precision A /
The D conversion circuit can be realized with an extremely small number of operational amplifiers as compared with the conventional A / D conversion circuit.

[0015]

As described above, according to the series-parallel type A / D conversion circuit of the present invention, the S / H circuit, the D / A conversion circuit and the subtraction circuit are integrated, so that S
Since the required number of operational amplifiers in the / H circuit, the D / A conversion circuit and the subtraction circuit is one, the circuit configuration is simple and the occupied area and power consumption are It can be reduced to 3 or less. Also,
Since the capacitor series is used as the D / A conversion circuit, it is possible to improve the relative accuracy more than the D / A conversion circuit using the resistance series, and it is possible to further reduce the power consumption.

[Brief description of drawings]

FIG. 1 (a) is an A / D according to a first embodiment of the present invention.
FIG. 3B is a block diagram showing a conversion circuit, and FIG. 3B is a circuit diagram of an arithmetic circuit in the A / D conversion circuit according to the first embodiment of the present invention shown in FIG.

FIG. 2 shows A / D according to the first embodiment of the present invention shown in FIG.
6 is a time chart explaining the operation of the conversion circuit.

FIG. 3 is a block diagram showing an A / D conversion circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a conventional A / D conversion circuit.

5 shows a first example of the conventional A / D conversion circuit shown in FIG.
3 is a circuit diagram showing an example of the A / D conversion circuit and the second A / D conversion circuit of FIG.

6 is a diagram showing D / in the conventional A / D conversion circuit shown in FIG.
It is a circuit diagram which shows an example of an A conversion circuit.

7 is a circuit diagram showing an example of a subtraction circuit in the conventional A / D conversion circuit shown in FIG.

[Explanation of symbols]

 1; 1st S / H circuit 2; 1st A / D circuit 6; 2nd A / D circuit 7; arithmetic circuit

Claims (1)

[Claims] 1. A first sample-and-hold circuit for sampling and holding an input signal, and a first sample-and-hold circuit for converting an output voltage of the first sample-and-hold circuit into nc-bit digital data. An analog / digital conversion circuit, a second sample and hold circuit for sampling and holding the output voltage of the first sample and hold circuit, and output data of the first analog / digital conversion circuit. To an analog signal, an nc-bit digital / analog conversion circuit, a subtraction circuit for taking the difference between the output signal of the second sample-and-hold circuit and the output signal of the digital / analog conversion circuit, and the subtraction circuit Second analog / digital conversion circuit for converting the output signal of the above into nf-bit digital data. The pull-and-hold circuit has capacitors and switches, and the digital / analog converter circuit has nc capacitors and switches whose ratio of the values of the capacitors is a power of 2, and nc capacitors of the digital / analog converter circuit. One end of each of the capacitors is connected to the reference potential or the ground potential corresponding to the output data of the first analog / digital conversion circuit, and the subtraction circuit is connected to the second sample and hold circuit.
An analog / digital conversion circuit, which is a charge addition type subtraction circuit having inputs of an output of a digital circuit and an output of the digital / analog conversion circuit.