WO2018235997A1 - Successive comparison a/d converter using switched-capacitor d/a converter - Google Patents

Successive comparison a/d converter using switched-capacitor d/a converter Download PDF

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Publication number
WO2018235997A1
WO2018235997A1 PCT/KR2017/010609 KR2017010609W WO2018235997A1 WO 2018235997 A1 WO2018235997 A1 WO 2018235997A1 KR 2017010609 W KR2017010609 W KR 2017010609W WO 2018235997 A1 WO2018235997 A1 WO 2018235997A1
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capacitor
voltage
converter
output voltage
input
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PCT/KR2017/010609
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French (fr)
Korean (ko)
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진유린
조성익
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전북대학교산학협력단
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

Definitions

  • the present invention relates to a D / A converter using a switched-capacitor D / A converter, and more particularly to a D / A converter comprising a capacitor array provided according to the resolution of an A / To a slice comparator type A / D converter capable of reducing power consumption and chip area.
  • a successive approximation ADC is a conversion method that quantizes by a binary search method.
  • a comparator type analog-to-digital converter is composed of a sample hold circuit, a D / A converter, a voltage comparator, and a register.
  • the D / A converter sequentially generates voltages corresponding to the respective bits And the input voltage sampled and held is compared to obtain a digital signal.
  • Figure 1 shows a D / A converter comprising a conventional capacitor array.
  • a conventional D / A converter uses a capacitor array, so no sample-and-hold circuit is provided. Therefore, there is an advantage that power consumption is very small because current flows only when switching occurs.
  • it is difficult to implement a high-resolution A / D converter because the weight of the capacitor is large with respect to the resolution.
  • 2 n + 1 unit capacitors are required, and the size of the unit capacitors is determined by the thermal noise and the capacitance of the switch. As the capacitance increases, the area of the chip and the switching current increase, which limits the miniaturization, power consumption and high-speed operation.
  • Japanese Patent No. JP 4751667 (hereinafter referred to as " Prior Art Document ") has a sample-hold amplifier circuit for shortening the sampling time, and is capable of performing AD conversion by inputting a signal having the same signal amplitude as the power- Converter.
  • the prior art has a sample-and-hold amplifier circuit so that the sampling time can be shortened. Although the prior art has the effect of improving the processing speed of the analog-digital, the area of the chip is increased.
  • the present invention has been made in view of the above problems, and it is an object of the present invention to reduce a capacitance by replacing a D / A converter constituted by a capacitor array with a switched-capacitor D / A converter.
  • the sequential comparison type A / D converter using the switched-capacitor D / A converter of the present invention includes a reference capacitor for receiving a comparison voltage and generating a reference voltage, an input capacitor for receiving the input voltage and sampling the input voltage, And a D / A converter including an output capacitor receiving the charge charged in the reference capacitor and a signal output terminal for generating an output voltage through the input voltage.
  • the D / A converter according to the present invention has a structure in which the reference capacitor, the input capacitor, the output capacitor, and the signal output terminal are differentiated to output a positive output voltage and a negative output voltage.
  • a sequential comparison type A / D converter using a switched-capacitor D / A converter comprises a comparator for comparing the positive output voltage and the negative output voltage, And a shift register for converting the digital data to be outputted in parallel.
  • the present invention is characterized in that the reference capacitor generates the reference voltage at a reset clock and the input voltage supplied to the input capacitor is sampled and the signal output terminal outputs the positive output voltage and the negative output voltage,
  • the approximate control circuit converts the digital data according to the comparison result of the positive output voltage and the negative output voltage.
  • the charge stored in the reference capacitor is transferred to the input capacitor during the first cycle, and the reference voltage is changed as the charge charged in the reference capacitor is divided into half.
  • an amplifier for adding or subtracting the changed reference voltage to the output voltage is provided.
  • the present invention has an effect of reducing a power consumption and a chip area by reducing a capacitance by replacing a D / A converter constituted by a capacitor array with a switched-capacitor D / A converter.
  • FIG. 1 shows a D / A converter comprising a conventional capacitor array.
  • FIG. 2 is a circuit diagram of a sequential comparison type A / D converter in which a switched-capacitor D / A converter according to the present invention is used.
  • FIG. 3 is a flowchart illustrating a digital conversion process through a circuit of the switched-capacitor D / A converter according to the present invention.
  • FIG. 4 is a diagram showing an embodiment of a signal waveform used in the sequential comparison type A / D converter according to the present invention.
  • FIG. 2 is a circuit diagram of a sequential comparison type A / D converter in which a switched-capacitor D / A converter according to the present invention is used.
  • the sequential comparison type A / D converter may include a D / A converter 100, a shift approximation control circuit 200, and a shift register 300.
  • the D / A converter 100 includes signal input terminals V INP and V INN , comparison voltage supply terminals V REFP and V REFN , reference capacitors C DACP and C DACN , an input capacitor C IN , (C OUT ) consists of a differential structure,
  • the comparison voltage supply terminals V REFP and V REFN are devices to which a comparison voltage is applied. As shown in FIG. 2, compared to a voltage supply terminal (V REFP, REFN V) is a structure of the differential pair, the comparative voltage of both the V REFP, REFN V is applied to compare negative voltage.
  • a reset switch RESET is connected to one end of the comparison voltage supply terminal, and a reset switch RESET is connected to the reference capacitor.
  • the reset switch (RESET) is turned on at the reset clock.
  • a positive comparison voltage V REFP is supplied to a positive reference capacitor C DACP and a negative comparison voltage V REFN is supplied to a positive reference capacitor C DACN .
  • the amount of the reference capacitor (C DACP) the comparison voltage (V REFN) supplied to the comparison of the supplied amount of voltage (V REFP) the sound of the reference capacitor (C DACN) in is the reference voltage.
  • the signal input terminals V INN and V INP are devices to which an input voltage is applied. As shown in FIG. 2, a differential pair structure of signal input terminals V INN and V INP is applied, and a positive input voltage is applied to V INP and a negative input voltage is applied to V INN .
  • a signal input terminal to one end and a first sample-and-hold switch (SH 1) connected to a first sample-and-hold switch (SH 1) of (V INN, V INP) is connected to the input capacitor (C IN) do.
  • a first sample-and-hold switch (SH 1) are Trun-on by the reset clock. Accordingly, an input voltage is applied to the input capacitor C IN of both stages, and an input voltage applied to the input capacitor C IN is sampled.
  • One end of the input capacitor C IN is connected to the second sample hold switch SH 2 , the addition switch 2 2p , and the subtraction switch 2n .
  • the second sample and hold switch in accordance with the input capacitor (C IN) is made of an aspect of a differential pair, such as 2 (SH 2), the addition switch ( ⁇ 2P), the subtraction switch ( ⁇ 2N) of FIG differential a pair Structure.
  • a second sample-and-hold switch (SH 2), the addition switch ( ⁇ 2P), the subtraction switch ( ⁇ 2N) is connected to the amplifier 110 and the output capacitor (C OUT).
  • the second sample hold switch SH 2 is turned on at the reset clock. Therefore, the charge charged in the input reference capacitor C IN is transferred to the output capacitor C OUT , and a positive output voltage V P and a negative output voltage V N are output.
  • the comparator 200 is a device for comparing the magnitudes of the positive output voltage V P and the negative output voltage V N.
  • the shift approximation control circuit 300 is a device for converting digital data from higher bits according to the comparison result.
  • the shift register 400 is a device for converting digital data to be outputted in parallel.
  • FIG. 3 is a flow chart for explaining the operation sequence of the sequential comparison type A / D converter using the switched-capacitor D / A converter according to the present invention.
  • the sequential comparison type A / D converter using the switched-capacitor D / A converter according to the present invention can be made more clear according to the following description. On the other hand, the matters described above are omitted or briefly described. On the other hand, the flow chart of Fig. 3 will be explained more clearly through the signal waveform of Fig. 4 is a diagram showing an embodiment of a signal waveform used in the sequential comparison type A / D converter according to the present invention.
  • the reset clock is reset switch (RESET), a first sample-and-hold switch (SH 1), the second sample-and-hold switch (SH 2), the first cycle switch ( ⁇ 1), and the second cycle switch ( ⁇ 2) Turn- (S100).
  • a reference voltage V DACP, DACN V
  • the input signals V INP and V INN are supplied to the input capacitor C IN and sampled.
  • the charge stored in the input capacitor C IN is supplied to the output capacitor C OUT as the second sample hold switch SH 2 is operated and the positive output voltage V P and negative
  • the output voltage V N is output (S200).
  • the reset clock will be described in more detail with reference to FIG. 4, it can be seen that signals of SH 1 , PHI 1 , SH 2 , PHI 2 are activated at RESET clock.
  • a first sample-and-hold switch (SH 1), and the first cycle switch ( ⁇ 1) is operating in the amount of the reference capacitor (C DACP) and a negative reference capacitor (C DACN) of the reference voltage of 4/4 was produced as .
  • a positive output voltage V P and a negative output voltage V N are generated as the second sample hold switch SH 2 and the second cycle switch? 2 are operated.
  • the numerical value of the voltage (V) is not a specific numerical value but is expressed as a fractional value in order to clarify the magnitude of the reference voltage and the output voltage.
  • the positive output voltage V P and the negative output voltage V N can be expressed by the following Equation 1, respectively.
  • A represents the amplification factor of the integrator, and can be expressed by the following equation (2).
  • the comparator 200 compares the magnitude of the positive output voltage V P with the negative output voltage V N (S300). 4, it can be seen that the magnitude of the positive output voltage V P is greater than the magnitude of the negative output voltage V N. Accordingly, the approximation approximation control circuit 300 generates High data according to the high positive output voltage V P (S400). As the high data is generated, the bit (digital data) of '1' is converted (S600).
  • the approximation control circuit 300 when the negative output voltage V N is higher than the positive output voltage V P , the approximation control circuit 300 generates Low data (S500). As low data is generated, a bit of '0' is converted (S600).
  • the input signal is sampled at the RESET clock, and the first bit is converted, thereby eliminating the clock consumption for sampling the input signal separately.
  • the first cycle switch? 1 and another first cycle switch? 1X are operated. 2, when the first cycle switch? 1 and another first cycle switch? 1X operate, the charge stored in the reference capacitors C DACP , C DACN is applied to the input capacitor C IN .
  • the reference voltage is changed according to the half of the charge charged in the reference capacitor (S800). Referring to the reference voltage of FIG. 4, it can be seen that the size of the reference capacitor is changed from 4/4 to 2/4 as the first cycle switch? 1 and another first cycle switch? 1X are operated .
  • the second cycle switch? 2 is operated. 2, when the second cycle switch? 2 is operated, the charge stored in the input capacitor C IN is transferred to the output capacitor C OUT , and the positive output voltage V P and the positive The output voltage V N is generated.
  • the comparator compares the positive output voltage V P with the negative output voltage V N to generate a bit, and the next bit is determined according to the previously converted digital (bit) value (S900). If the previously converted digital (bits), a value of 'l', and the subtraction switch ( ⁇ 2N) the operation (S1000), if the previously converted digital (bits), a value of '0' is added to the switch ( ⁇ 2P) is (S1100).
  • an output voltage will be described as being in accordance with the operation of the subtraction switch 2N and the addition switch 2P .
  • the subtraction switch ( ⁇ 2N) a negative output voltage (V N) there is the addition amount of the reference voltage (V REFP), the amount of the output voltage (V P) is added to the reference voltage (V REFN) of the sound by do.
  • a '1' bit is output from the 'reset clock', and the subtraction switch 2N is operated.
  • a negative reference voltage of -2 / 4V is added to the positive output voltage of about + 3 / 8V and a positive output voltage (V P ) of about -1 / 8V .
  • a positive reference voltage + 1 / 4V is added to a negative output voltage of about -3 / 8V, and a negative output voltage V N has a value of about + 1/8V.
  • the comparator 200 compares the magnitude of the positive output voltage V P with the negative output voltage V N (S300). Low data is generated as the output voltage of the negative output voltage V N is higher than the positive output voltage V P (S400). As low data is generated, a bit of '0' is converted (S600).
  • the bit conversion is completed in the second cycle, it is checked whether the digital conversion according to the input signal is completed (S700). If the digital conversion is not completed, steps S200 to SS1100 are repeatedly performed. After the second cycle is performed once, the reference voltage is 1/4 V, the reference voltage after the second cycle is 1/8 V, the reference voltage is halved, and the output voltage is outputted by the changed reference voltage.
  • the number of bits is 5, and the steps of S200 to SS1100 are repeated to convert digital data of '10110'.
  • the present invention relates to a slot comparator type A / D converter capable of reducing power consumption and chip area by replacing a D / A converter comprising a capacitor array provided according to the resolution of an A / D converter with a switched-capacitor.

Abstract

According to the present invention, in order to reduce power consumption and a chip area by replacing, with a switched-capacitor, a D/A converter including a capacitor array provided according to the resolution of an A/D converter, the D/A converter including a capacitor array is replaced with a switched-capacitor D/A converter, thereby reducing a capacitance.

Description

스위치드-커패시터 D/A 변환기를 사용한 축차 비교형 A/D 변환기Comparison-type A / D converter using switched-capacitor D / A converter
본 발명은 스위치드-커패시터 D/A 변환기를 사용하는 축차 비교형 A/D 변환기에 관한 것으로, 더욱 상세하게는 A/D변환기의 해상도에 따라 구비되는 커패시터 어레이로 이루어지는 D/A변환기를 스위치드-커패시터로 대체하여 전력소모와 칩 면적을 감소시킬 수 있는 축자 비교형 A/D변환기에 관한 것이다.More particularly, the present invention relates to a D / A converter using a switched-capacitor D / A converter, and more particularly to a D / A converter comprising a capacitor array provided according to the resolution of an A / To a slice comparator type A / D converter capable of reducing power consumption and chip area.
축차 비교형 아날로그-디지털 변환기(Successive approximation ADC)는 이진 탐색 방식으로 양자화하는 변환방식이다. 일반적으로 축자 비교형 방식의 아날로그-디지털 변환기는 샘플홀드회로, D/A 변환기, 전압 비교기, 레지스터(register)로 구성되고, D/A 변환기에서 상위비트부터 순차로 각 비트에 대응하는 전압을 발생시켜 샘플홀드된 입력 전압을 비교하여 디지털 신호를 얻게 된다. A successive approximation ADC is a conversion method that quantizes by a binary search method. Generally, a comparator type analog-to-digital converter is composed of a sample hold circuit, a D / A converter, a voltage comparator, and a register. The D / A converter sequentially generates voltages corresponding to the respective bits And the input voltage sampled and held is compared to obtain a digital signal.
도 1은 기존의 커패시터 어레이로 이루어진 D/A변환기를 나타낸다. 도 1을 살펴보면, 기존의 D/A변환기는 커패시터 어레이를 사용하기 때문에 샘플홀드 회로가 따로 구비되지 않는다. 따라서 스위칭이 일어날 때만 전류가 흐르기 때문에 전력소모가 매우 적다는 장점이 있다. 하지만, 도 1과 같이, 해상도에 대한 커패시터의 가중치가 크기 때문에 고해상도 A/D 변환기를 구현하기는 힘들다. n-bit 해상도의 완전차동의 A/D 변환기를 구현하기 위해서는 2n+1개의 단위 커패시터가 필요하며, 단위 커패시터의 크기는 열잡음과 스위치의 커패시턴스에 따라 결정된다. 커패시턴스가 증가하면 칩의 면적과 스위칭 전류가 증가하게 되고, 이는 소형화와 전력소모 및 고속 동작에 제한을 주게 된다.Figure 1 shows a D / A converter comprising a conventional capacitor array. Referring to FIG. 1, a conventional D / A converter uses a capacitor array, so no sample-and-hold circuit is provided. Therefore, there is an advantage that power consumption is very small because current flows only when switching occurs. However, as shown in FIG. 1, it is difficult to implement a high-resolution A / D converter because the weight of the capacitor is large with respect to the resolution. To implement a fully differential A / D converter with n-bit resolution, 2 n + 1 unit capacitors are required, and the size of the unit capacitors is determined by the thermal noise and the capacitance of the switch. As the capacitance increases, the area of the chip and the switching current increase, which limits the miniaturization, power consumption and high-speed operation.
일본등록특허 JP 4751667호(이하 '선행문헌'으로 칭함)는 샘플링 시간을 단축하기 위한 샘플 홀드 증폭기 회로를 구비하고, 전원 전압과 동일한 신호 진폭의 신호를 입력하여 AD 변환하는 것이 가능한 축차 비교형 AD 변환기에 관한 것이다. 선행문헌은 샘플 홀드 앰프 회로를 구비함으로써, 샘플링 시간(sampling time)을 단축할 수 있는 효과가 있다. 선행문헌은 아날로그-디지털의 처리속도를 향상시킬 수 있는 효과가 있으나, 칩의 면적이 증가되는 문제점을 갖고 있다.Japanese Patent No. JP 4751667 (hereinafter referred to as " Prior Art Document ") has a sample-hold amplifier circuit for shortening the sampling time, and is capable of performing AD conversion by inputting a signal having the same signal amplitude as the power- Converter. The prior art has a sample-and-hold amplifier circuit so that the sampling time can be shortened. Although the prior art has the effect of improving the processing speed of the analog-digital, the area of the chip is increased.
본 발명은 위와 같은 문제점을 해결하기 위해 커패시터 어레이로 구성되는 D/A 변환기를 스위치드-커패시터 D/A 변환기로 대체하여 커패시턴스를 줄이는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to reduce a capacitance by replacing a D / A converter constituted by a capacitor array with a switched-capacitor D / A converter.
본 발명의 스위치드-커패시터 D/A 변환기를 사용한 축차 비교형 A/D 변환기는 비교전압을 공급받아 기준전압을 생성하는 기준커패시터, 입력전압을 공급받아 상기 입력전압을 샘플링하는 입력커패시터, 상기 입력커패시터에 충전된 전하를 전달받는 출력커패시터 및 상기 기준커패시터의 증폭률과 상기 입력전압을 통해 출력전압을 생성하는 신호출력단자가 포함된 D/A 변환기를 포함한다. The sequential comparison type A / D converter using the switched-capacitor D / A converter of the present invention includes a reference capacitor for receiving a comparison voltage and generating a reference voltage, an input capacitor for receiving the input voltage and sampling the input voltage, And a D / A converter including an output capacitor receiving the charge charged in the reference capacitor and a signal output terminal for generating an output voltage through the input voltage.
본 발명의 따른 상기 D/A변환기는 양의 출력전압과 음의 출력전압을 출력하기 위해 상기 기준커패시터, 상기 입력커패시터, 상기 출력커패시터 및 상기 신호출력단자가 차동 한 쌍의 구조로 이루어진다.The D / A converter according to the present invention has a structure in which the reference capacitor, the input capacitor, the output capacitor, and the signal output terminal are differentiated to output a positive output voltage and a negative output voltage.
본 발명의 스위치드-커패시터 D/A 변환기를 사용한 축차 비교형 A/D 변환기는 상기 양의 출력전압과 상기 음의 출력전압의 크기를 비교하는 비교기, 상기 비교결과에 따라 상위비트부터 디지털데이터를 변환하는 축차근사제어회로 및 상기 디지털데이터가 병렬로 출력되도록 변환하는 시프트레지스터를 더 포함한다.A sequential comparison type A / D converter using a switched-capacitor D / A converter according to the present invention comprises a comparator for comparing the positive output voltage and the negative output voltage, And a shift register for converting the digital data to be outputted in parallel.
본 발명은 리셋클록시 상기 기준커패시터가 상기 기준전압을 생성 및 상기 입력커패시터에 공급된 상기 입력전압은 샘플링되며, 상기 신호출력단자는 상기 양의 출력전압과 상기 음의 출력전압을 출력하되, 상기 축차근사제어회로는 상기 양의 출력전압과 상기 음의 출력전압의 비교결과에 따라 디지털데이터를 변환한다. The present invention is characterized in that the reference capacitor generates the reference voltage at a reset clock and the input voltage supplied to the input capacitor is sampled and the signal output terminal outputs the positive output voltage and the negative output voltage, The approximate control circuit converts the digital data according to the comparison result of the positive output voltage and the negative output voltage.
본 발명은 제1사이클시 상기 기준커패시터에 저장된 전하가 상기 입력커패시터로 이동되어 상기 기준커패시터에 충전된 전하가 절반으로 나뉨에 따라 상기 기준전압이 변경되며, 제2사이클시 상기 디지털데이터에 따라 상기 출력전압에 상기 변경된 기준전압을 가감하는 증폭기를 더 포함한다.According to the present invention, the charge stored in the reference capacitor is transferred to the input capacitor during the first cycle, and the reference voltage is changed as the charge charged in the reference capacitor is divided into half. In the second cycle, And an amplifier for adding or subtracting the changed reference voltage to the output voltage.
본 발명은 위와 같은 문제점을 해결하기 위해 커패시터 어레이로 구성되는 D/A 변환기를 스위치드-커패시터 D/A 변환기로 대체하여 커패시턴스를 줄임으로써, 전력소모와 칩 면적을 감소시킬 수 있는 효과가 있다.In order to solve the above problems, the present invention has an effect of reducing a power consumption and a chip area by reducing a capacitance by replacing a D / A converter constituted by a capacitor array with a switched-capacitor D / A converter.
도 1은 기존의 커패시터 어레이로 이루어지는 D/A변환기를 나타낸다. 1 shows a D / A converter comprising a conventional capacitor array.
도 2는 본 발명에 따른 스위치드-커패시터 D/A 변환기가 사용되는 축차비교형 A/D 변환기의 회로도이다. 2 is a circuit diagram of a sequential comparison type A / D converter in which a switched-capacitor D / A converter according to the present invention is used.
도 3은 본 발명에 따른 스위치드-커패시터 D/A 변환기의 회로를 통한 디지털 변환과정을 도시한 순서도이다.3 is a flowchart illustrating a digital conversion process through a circuit of the switched-capacitor D / A converter according to the present invention.
도 4는 본 발명에 따른 축차 비교형 A/D변환기에서 사용된 신호파형의 일 실시예를 나타낸 도면이다.4 is a diagram showing an embodiment of a signal waveform used in the sequential comparison type A / D converter according to the present invention.
이하, 본 발명의 바람직한 실시 예에 대하여 첨부된 도면을 참조하여 상세히 설명하기로 한다. 본 발명의 실시 예를 설명함에 있어서 관련된 공지 기술에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에 그 상세한 설명을 생략하기로 한다. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.
도 2는 본 발명에 따른 스위치드-커패시터 D/A 변환기가 사용되는 축차비교형 A/D 변환기의 회로도이다. 2 is a circuit diagram of a sequential comparison type A / D converter in which a switched-capacitor D / A converter according to the present invention is used.
도 2를 살펴보면, 본 발명에 따른 축차비교형 A/D 변환기는 D/A변환기(100), 축차근사제어회로(200), 시프트레지스터(300)를 포함할 수 있다. 2, the sequential comparison type A / D converter according to the present invention may include a D / A converter 100, a shift approximation control circuit 200, and a shift register 300.
D/A변환기(100)는 신호입력단자(VINP, VINN), 비교전압공급단자(VREFP, VREFN), 기준커패시터(CDACP, CDACN), 입력커패시터(CIN), 출력커패시터(COUT)가 차동의 구조로 이루어져 있다,The D / A converter 100 includes signal input terminals V INP and V INN , comparison voltage supply terminals V REFP and V REFN , reference capacitors C DACP and C DACN , an input capacitor C IN , (C OUT ) consists of a differential structure,
비교전압공급단자(VREFP, VREFN)는 비교전압이 인가되는 장치이다. 도 2와 같이, 비교전압공급단자(VREFP, VREFN)는 차동 한 쌍의 구조이며, VREFP에서는 양의 비교전압, VREFN에서는 음의 비교전압이 인가된다.The comparison voltage supply terminals V REFP and V REFN are devices to which a comparison voltage is applied. As shown in FIG. 2, compared to a voltage supply terminal (V REFP, REFN V) is a structure of the differential pair, the comparative voltage of both the V REFP, REFN V is applied to compare negative voltage.
비교전압공급단자의 일단에는 리셋스위치(RESET)가 연결되며, 리셋스위치(RESET)는 기준커패시터와 연결된다. 리셋스위치(RESET)는 리셋클럭시 Turn-on된다. 양의 비교전압(VREFP)은 양의 기준커패시터(CDACP)에 공급되며, 음의 비교전압(VREFN)은 양의 기준커패시터(CDACN)에 공급된다. 양의 기준커패시터(CDACP)에 공급된 양의 비교전압(VREFP)과 음의 기준커패시터(CDACN)에 공급된 비교전압(VREFN)은 기준전압이 된다.A reset switch RESET is connected to one end of the comparison voltage supply terminal, and a reset switch RESET is connected to the reference capacitor. The reset switch (RESET) is turned on at the reset clock. A positive comparison voltage V REFP is supplied to a positive reference capacitor C DACP and a negative comparison voltage V REFN is supplied to a positive reference capacitor C DACN . The amount of the reference capacitor (C DACP) the comparison voltage (V REFN) supplied to the comparison of the supplied amount of voltage (V REFP) the sound of the reference capacitor (C DACN) in is the reference voltage.
신호입력단자(VINN, VINP)는 입력전압이 인가되는 장치이다. 도 2와 같이, 신호입력단자(VINN, VINP)의 차동 한 쌍의 구조이며, VINP에는 양의 입력전압, VINN에는 음의 입력전압이 인가된다. The signal input terminals V INN and V INP are devices to which an input voltage is applied. As shown in FIG. 2, a differential pair structure of signal input terminals V INN and V INP is applied, and a positive input voltage is applied to V INP and a negative input voltage is applied to V INN .
도 2를 참조하면, 신호입력단자(VINN, VINP)의 일단에는 제1샘플홀드스위치(SH1)가 연결되며, 제1샘플홀드스위치(SH1)는 입력커패시터(CIN)와 연결된다. 제1샘플홀드스위치(SH1)는 리셋클럭에 의해 Trun-on된다. 따라서 양 단의 입력커패시터(CIN)에 입력전압이 인가되며, 입력커패시터(CIN)에 인가된 입력전압은 샘플링(Sampling)된다. 2, a signal input terminal to one end and a first sample-and-hold switch (SH 1) connected to a first sample-and-hold switch (SH 1) of (V INN, V INP) is connected to the input capacitor (C IN) do. A first sample-and-hold switch (SH 1) are Trun-on by the reset clock. Accordingly, an input voltage is applied to the input capacitor C IN of both stages, and an input voltage applied to the input capacitor C IN is sampled.
입력커패시터(CIN)의 일단부는 제2샘플홀드스위치(SH2), 가산스위치(Φ2p), 감산스위치(Φ2n)가 연결된다. 한편, 도 2와 같이 입력커패시터(CIN)가 차동 한 쌍의 형태로 이루어짐에 따라 제2샘플홀드스위치(SH2), 가산스위치(Φ2P), 감산스위치(Φ2N)도 차동 한 쌍의 구조로 이루어진다. 제2샘플홀드스위치(SH2), 가산스위치(Φ2P), 감산스위치(Φ2N)는 증폭기(110) 및 출력커패시터(COUT)와 연결된다.One end of the input capacitor C IN is connected to the second sample hold switch SH 2 , the addition switch 2 2p , and the subtraction switch 2n . On the other hand, also the second sample and hold switch in accordance with the input capacitor (C IN) is made of an aspect of a differential pair, such as 2 (SH 2), the addition switch (Φ 2P), the subtraction switch (Φ 2N) of FIG differential a pair Structure. A second sample-and-hold switch (SH 2), the addition switch (Φ 2P), the subtraction switch (Φ 2N) is connected to the amplifier 110 and the output capacitor (C OUT).
제2샘플홀드스위치(SH2)는 리셋클럭시 Turn-on된다. 따라서 입력기준커패시터(CIN)에 충전된 전하가 출력커패시터(COUT)로 이동되며, 양의 출력전압(VP)과 음의 출력전압(VN)이 출력된다. The second sample hold switch SH 2 is turned on at the reset clock. Therefore, the charge charged in the input reference capacitor C IN is transferred to the output capacitor C OUT , and a positive output voltage V P and a negative output voltage V N are output.
비교기(200)는 양의 출력전압(VP)과 음의 출력전압(VN)의 크기를 비교하는 장치이다. The comparator 200 is a device for comparing the magnitudes of the positive output voltage V P and the negative output voltage V N.
축차근사제어회로(300)는 비교결과에 따라 상위비트부터 디지털데이터를 변환하는 장치이다. The shift approximation control circuit 300 is a device for converting digital data from higher bits according to the comparison result.
시프트레지스터(400)는 디지털데이터가 병렬로 출력되도록 변환하는 장치이다. The shift register 400 is a device for converting digital data to be outputted in parallel.
이하 도 3은 본 발명에 따른 스위치드-커패시터 D/A 변환기를 사용한 축차 비교형 A/D 변환기의 동작순서를 설명하기 위한 플로우챠트이다. 이하의 설명에 따라 본 발명에 따른 스위치드-커패시터 D/A 변환기를 사용한 축차 비교형 A/D 변환기가 보다 명확해 질 수 있다. 한편, 앞서 기재한 사항은 생략 또는 간략하게 기재한다. 한편, 도 4의 신호파형을 통해 도 3의 플로우챠트를 보다 명확하게 설명하도록 한다. 도 4는 본 발명에 따른 축차 비교형 A/D변환기에서 사용된 신호파형의 일 실시예를 나타낸 도면이다.3 is a flow chart for explaining the operation sequence of the sequential comparison type A / D converter using the switched-capacitor D / A converter according to the present invention. The sequential comparison type A / D converter using the switched-capacitor D / A converter according to the present invention can be made more clear according to the following description. On the other hand, the matters described above are omitted or briefly described. On the other hand, the flow chart of Fig. 3 will be explained more clearly through the signal waveform of Fig. 4 is a diagram showing an embodiment of a signal waveform used in the sequential comparison type A / D converter according to the present invention.
[리셋클럭][Reset Clock]
리셋클럭에서는 리셋스위치(RESET), 제1샘플홀드스위치(SH1), 제2샘플홀드스위치(SH2), 제1사이클스위치(Φ1), 및 제2사이클스위치(Φ2)가 Turn-on된다(S100). The reset clock is reset switch (RESET), a first sample-and-hold switch (SH 1), the second sample-and-hold switch (SH 2), the first cycle switch (Φ 1), and the second cycle switch (Φ 2) Turn- (S100).
리셋스위치(RESET)가 동작됨에 따라 양의 기준커패시터(CDACP)와 음의 기준커패시터(CDACN)에는 비교전압이 인가되어 기준전압(VDACP, VDACN)이 생성된다. 또한, 제1샘플홀드스위치(SH1)가 동작됨에 따라 입력신호(VINP, VINN)가 입력커패시터(CIN)에 공급되어 샘플링된다. 또한, 제2샘플홀드스위치(SH2)가 동작됨에 따라 입력커패시터(CIN)에 충전된 전하가 출력커패시터(COUT)에 공급되며, 신호출력단자에서 양의 출력전압(VP)과 음의 출력전압(VN)이 출력된다(S200). RESET amount of the reference capacitor as (RESET) the operation (C DACP) and the reference capacitor in the negative (DACN C) is applied to the comparison voltage is a reference voltage (V DACP, DACN V) is produced. Also, as the first sample hold switch SH 1 is operated, the input signals V INP and V INN are supplied to the input capacitor C IN and sampled. The charge stored in the input capacitor C IN is supplied to the output capacitor C OUT as the second sample hold switch SH 2 is operated and the positive output voltage V P and negative The output voltage V N is output (S200).
도 4를 통해 리셋클럭을 더욱 상세히 설명한다. 도 4의 회로작동신호를 살펴보면, RESET클럭시, SH1, Φ1와, SH2, Φ2의 신호가 작동된 것을 볼 수 있다. 제1샘플홀드스위치(SH1), 및 제1사이클스위치(Φ1)가 동작됨에 따라 양의 기준커패시터(CDACP)와 음의 기준커패시터(CDACN)에 4/4의 기준전압이 생성되었다. 제2샘플홀드스위치(SH2), 제2사이클스위치(Φ2)가 동작됨에 따라 양의 출력전압(VP)과 음의 출력전압(VN)이 생성된다. 여기서 전압(V)의 수치는 특정 수치값을 나타내는 것이 아닌 기준전압과 출력전압의 크기 비교를 명확하게 하기 위해 분수값으로 표시하였다. 한편, 양의 출력전압(VP)과 음의 출력전압(VN)은 각각 아래의 수학식 1로 표현될 수 있다.The reset clock will be described in more detail with reference to FIG. Looking at the circuit operation signal of FIG. 4, it can be seen that signals of SH 1 , PHI 1 , SH 2 , PHI 2 are activated at RESET clock. A first sample-and-hold switch (SH 1), and the first cycle switch (Φ 1) is operating in the amount of the reference capacitor (C DACP) and a negative reference capacitor (C DACN) of the reference voltage of 4/4 was produced as . A positive output voltage V P and a negative output voltage V N are generated as the second sample hold switch SH 2 and the second cycle switch? 2 are operated. Here, the numerical value of the voltage (V) is not a specific numerical value but is expressed as a fractional value in order to clarify the magnitude of the reference voltage and the output voltage. On the other hand, the positive output voltage V P and the negative output voltage V N can be expressed by the following Equation 1, respectively.
[수학식 1][Equation 1]
Figure PCTKR2017010609-appb-I000001
Figure PCTKR2017010609-appb-I000001
Figure PCTKR2017010609-appb-I000002
Figure PCTKR2017010609-appb-I000002
A는 적분기의 증폭률을 나타내며, 다음의 수학식 2로 표현될 수 있다.A represents the amplification factor of the integrator, and can be expressed by the following equation (2).
[수학식 2]&Quot; (2) "
Figure PCTKR2017010609-appb-I000003
Figure PCTKR2017010609-appb-I000003
비교기(200)에 의해 양의 출력전압(VP)과 음의 출력전압(VN)의 크기가 비교된다(S300). 도 4의 출력전압을 살펴보면, 양의 출력전압(VP)의 크기가 음의 출력전압(VN)의 크기보다 큰 것을 볼 수 있다. 따라서 축차근사제어회로(300)는 양의 출력전압(VP)이 높음에 따라 High data를 생성한다(S400). High data가 생성됨에 따라 '1'의 비트(디지털데이터)가 변환된다(S600).The comparator 200 compares the magnitude of the positive output voltage V P with the negative output voltage V N (S300). 4, it can be seen that the magnitude of the positive output voltage V P is greater than the magnitude of the negative output voltage V N. Accordingly, the approximation approximation control circuit 300 generates High data according to the high positive output voltage V P (S400). As the high data is generated, the bit (digital data) of '1' is converted (S600).
반면, 축차근사제어회로(300)는 음의 출력전압(VN)이 양의 출력전압(VP)보다 높을 경우, Low data가 생성된다(S500). Low data가 생성됨에 따라 '0'의 비트가 변환된다(S600).On the other hand, when the negative output voltage V N is higher than the positive output voltage V P , the approximation control circuit 300 generates Low data (S500). As low data is generated, a bit of '0' is converted (S600).
RESET 클록에 입력신호가 샘플링됨과 동시에 첫 번째 비트가 변환이 완성됨으로써, 입력신호를 따로 샘플링하기 위한 클록소모가 없다는 효과가 있다.The input signal is sampled at the RESET clock, and the first bit is converted, thereby eliminating the clock consumption for sampling the input signal separately.
[제1사이클][1st cycle]
도 2 및 도 4의 회로동작신호를 살펴보면, RESET클럭 이후, 제1사이클스위치(Φ1)와 또 다른 제1사이클스위치(Φ1X)가 동작된다. 도 2의 회로도를 참조하면, 제1사이클스위치(Φ1)와 또 다른 제1사이클스위치(Φ1X)가 동작할 경우, 기준커패시터(CDACP, CDACN)에 저장된 전하가 입력커패시터(CIN)로 이동된다. Referring to the circuit operation signals of FIGS. 2 and 4, after the RESET clock, the first cycle switch? 1 and another first cycle switch? 1X are operated. 2, when the first cycle switch? 1 and another first cycle switch? 1X operate, the charge stored in the reference capacitors C DACP , C DACN is applied to the input capacitor C IN .
여기서 기준커패시터와 입력커패시터의 충전용량을 동일하면, 기준커패시터에 충전된 전하가 절반으로 나뉨에 따라 기준전압이 변경된다(S800). 도 4의 기준전압을 살펴보면, 제1사이클스위치(Φ1)와 또 다른 제1사이클스위치(Φ1X)가 동작됨에 따라 기준커패시터의 크기가 4/4에서 2/4로 변환된 것을 볼 수 있다.If the charge capacities of the reference capacitor and the input capacitor are the same, the reference voltage is changed according to the half of the charge charged in the reference capacitor (S800). Referring to the reference voltage of FIG. 4, it can be seen that the size of the reference capacitor is changed from 4/4 to 2/4 as the first cycle switch? 1 and another first cycle switch? 1X are operated .
[제2사이클][Second cycle]
도 4의 회로동작신호를 살펴보면, 제1사이클 동작 이후, 제2사이클스위치(Φ2)가 동작된다. 도 2의 회로도를 참조하면, 제2사이클스위치(Φ2)가 동작되면, 입력커패시터(CIN)에 저장된 전하가 출력커패시터(COUT)로 전송되며, 양의 출력전압(VP)과 음의 출력전압(VN)이 생성된다. 이에 비교기는 양의 출력전압(VP)과 음의 출력전압(VN)을 비교하여 비트를 생성하며, 이전 변환된 디지털(비트) 값에 따라 다음의 비트가 결정된다(S900). 이전 변환된 디지털(비트) 값이 'l'인 경우, 감산스위치(Φ2N)가 동작(S1000)되며, 이전 변환된 디지털(비트) 값이 '0'인 경우는 가산스위치(Φ2P)가 동작된다(S1100). 이하, 도 2를 참조하여 감산스위치(Φ2N) 및 가산스위치(Φ2P)의 동작에 따라 출력전압이 가감방식을 설명하도록 한다. Referring to the circuit operation signal of FIG. 4, after the first cycle operation, the second cycle switch? 2 is operated. 2, when the second cycle switch? 2 is operated, the charge stored in the input capacitor C IN is transferred to the output capacitor C OUT , and the positive output voltage V P and the positive The output voltage V N is generated. The comparator compares the positive output voltage V P with the negative output voltage V N to generate a bit, and the next bit is determined according to the previously converted digital (bit) value (S900). If the previously converted digital (bits), a value of 'l', and the subtraction switch (Φ 2N) the operation (S1000), if the previously converted digital (bits), a value of '0' is added to the switch (Φ 2P) is (S1100). Hereinafter, with reference to FIG. 2, an output voltage will be described as being in accordance with the operation of the subtraction switch 2N and the addition switch 2P .
도 2를 살펴보면, 감산스위치(Φ2N) 및 가산스위치(Φ2P)의 일단부는 입력커패시터(CIN)와 연결되며, 타단부는 증폭기(110)와 연결된다. 가산스위치(Φ2P)는 출력전압에 기준전압이 가산(加算)되도록 설치되는 반면, 감산스위치(Φ2N)는 증폭기에 반전되어 연결되어 출력전압에 기준전압이 감산(減算)되도록 설치된다. 도 2의 회로도에 따라 가산스위치(Φ2P)에 의해 양의 출력전압(VP)에는 양의 기준전압(VREFP)이 가산되며, 음의 출력전압(VN)에는 음의 기준전압(VREFN)이 가산된다. 반면, 감산스위치(Φ2N)에 의해 음의 출력전압(VN)에는 양의 기준전압(VREFP)이 가산되며, 양의 출력전압(VP)에는 음의 기준전압(VREFN)이 가산된다. 2, one end of the subtraction switch 2N and the addition switch 2P is connected to the input capacitor C IN and the other end is connected to the amplifier 110. The addition switch? 2P is provided so that the reference voltage is added to the output voltage, while the subtraction switch? 2N is connected to the amplifier in reverse so that the reference voltage is subtracted from the output voltage. FIG addition switch (Φ 2P) output voltage (V P) of the amount by in accordance with the circuit diagram of the 2 and the addition amount of the reference voltage (V REFP), outputs a negative voltage (V N) is based on a negative voltage (V REFN ) is added. On the other hand, the subtraction switch (Φ 2N) a negative output voltage (V N) there is the addition amount of the reference voltage (V REFP), the amount of the output voltage (V P) is added to the reference voltage (V REFN) of the sound by do.
도 4를 통해 제2사이클을 더욱 자세히 설명한다. 도 4를 살펴보면, '리셋클럭'에서 '1'의 비트가 출력됨에 따라 감산스위치(Φ2N)가 동작된다. 감산스위치(Φ2N)가 동작됨에 따라 양의 출력전압인 약 +3/8V에 음의 기준전압 -2/4V가 가산되며, 양의 출력전압(VP)은 약 -1/8V의 값을 갖는다. 또한, 음의 출력전압 약 -3/8V에 양의 기준전압 +1/4V가 가산되며, 음의 출력전압(VN)은 약 +1/8V의 값을 갖는다. The second cycle will be described in more detail with reference to FIG. Referring to FIG. 4, a '1' bit is output from the 'reset clock', and the subtraction switch 2N is operated. As the subtraction switch (Φ 2N ) is activated, a negative reference voltage of -2 / 4V is added to the positive output voltage of about + 3 / 8V and a positive output voltage (V P ) of about -1 / 8V . Also, a positive reference voltage + 1 / 4V is added to a negative output voltage of about -3 / 8V, and a negative output voltage V N has a value of about + 1/8V.
비교기(200)에 의해 양의 출력전압(VP)과 음의 출력전압(VN)의 크기가 비교된다(S300). 양의 출력전압(VP)보다 음의 출력전압(VN)의 출력전압이 높음에 따라 low data가 생성된다(S400). Low data가 생성됨에 따라 '0'의 비트가 변환된다(S600). The comparator 200 compares the magnitude of the positive output voltage V P with the negative output voltage V N (S300). Low data is generated as the output voltage of the negative output voltage V N is higher than the positive output voltage V P (S400). As low data is generated, a bit of '0' is converted (S600).
제2사이클에 의해 비트변환이 완료되면, 입력신호에 따른 디지털변환이 모두 완료되었는지 여부를 확인한다(S700). 디지털변환이 모두 완료되지 않으면, S200 내지 SS1100의 단계를 반복하여 수행한다. 제2사이클이 한 차례 수행한 뒤의 기준전압은 1/4V, 두 차례 수행한 뒤의 기준전압은 1/8V 등과 같이 기준전압은 절반으로 떨어지며, 출력전압은 변경된 기준전압에 의해 출력된다. When the bit conversion is completed in the second cycle, it is checked whether the digital conversion according to the input signal is completed (S700). If the digital conversion is not completed, steps S200 to SS1100 are repeatedly performed. After the second cycle is performed once, the reference voltage is 1/4 V, the reference voltage after the second cycle is 1/8 V, the reference voltage is halved, and the output voltage is outputted by the changed reference voltage.
도 4의 경우는 비트수가 5인 경우로써, 위의 S200 내지 SS1100의 단계를 반복하여, '10110'의 디지털데이터를 변환한다. In the case of FIG. 4, the number of bits is 5, and the steps of S200 to SS1100 are repeated to convert digital data of '10110'.
본 발명은 A/D변환기의 해상도에 따라 구비되는 커패시터 어레이로 이루어지는 D/A변환기를 스위치드-커패시터로 대체하여 전력소모와 칩 면적을 감소시킬 수 있는 축자 비교형 A/D변환기에 관한 것이다.The present invention relates to a slot comparator type A / D converter capable of reducing power consumption and chip area by replacing a D / A converter comprising a capacitor array provided according to the resolution of an A / D converter with a switched-capacitor.

Claims (6)

  1. 비교전압을 공급받아 기준전압을 생성하는 기준커패시터;A reference capacitor for receiving a comparison voltage and generating a reference voltage;
    입력전압을 공급받아 상기 입력전압을 샘플링하는 입력커패시터;An input capacitor for receiving the input voltage and sampling the input voltage;
    상기 입력커패시터에 충전된 전하를 전달받는 출력커패시터; 및An output capacitor receiving the charge charged in the input capacitor; And
    상기 기준커패시터의 증폭률과 상기 입력전압을 통해 출력전압을 생성하는 신호출력단자가 포함된 D/A 변환기; 를 A D / A converter including an amplification factor of the reference capacitor and a signal output terminal for generating an output voltage through the input voltage; To
    포함하는 스위치드-커패시터 D/A 변환기를 사용한 축차 비교형 A/D 변환기.A comparator of A / D ratio using a switched-capacitor D / A converter.
  2. 제1항에 있어서,The method according to claim 1,
    상기 D/A변환기는 양의 출력전압과 음의 출력전압을 출력하기 위해 상기 기준커패시터, 상기 입력커패시터, 상기 출력커패시터 및 상기 신호출력단자가 차동 한 쌍의 구조로 이루어지는 것을 특징으로 하는 스위치드-커패시터 D/A 변환기를 사용한 축차 비교형 A/D 변환기.Wherein the D / A converter has a pair structure in which the reference capacitor, the input capacitor, the output capacitor, and the signal output terminal are differentiated to output a positive output voltage and a negative output voltage. A / D converter using the / A converter.
  3. 제2항에 있어서,3. The method of claim 2,
    상기 양의 출력전압과 상기 음의 출력전압의 크기를 비교하는 비교기;A comparator for comparing the magnitude of the positive output voltage with the positive output voltage;
    상기 비교결과에 따라 상위비트부터 디지털데이터를 변환하는 축차근사제어회로; 및A shift approximation control circuit for converting the digital data from the upper bits according to the comparison result; And
    상기 디지털데이터가 병렬로 출력되도록 변환하는 시프트레지스터;를 더 포함하는 것을 특징으로 하는 스위치드-커패시터 D/A 변환기를 사용한 축차 비교형 A/D 변환기.And a shift register for converting the digital data so that the digital data is output in parallel. The digital-to-analog converter according to claim 1,
  4. 제3항에 있어서,The method of claim 3,
    리셋클록시 상기 기준커패시터가 상기 기준전압을 생성 및 상기 입력커패시터에 공급된 상기 입력전압은 샘플링되며, 상기 신호출력단자는 상기 양의 출력전압과 상기 음의 출력전압을 출력하되,Wherein the reference capacitor generates the reference voltage and the input voltage supplied to the input capacitor is sampled at a reset clock and the signal output terminal outputs the positive output voltage and the negative output voltage,
    상기 축차근사제어회로는 상기 양의 출력전압과 상기 음의 출력전압의 비교결과에 따라 디지털데이터를 변환하는 것을 특징으로 하는 스위치드-커패시터 D/A 변환기를 사용한 축차 비교형 A/D 변환기.Wherein the approximation approximation control circuit converts the digital data according to a result of the comparison between the positive output voltage and the negative output voltage.
  5. 제4항에 있어서,5. The method of claim 4,
    제1사이클시 상기 기준커패시터에 저장된 전하가 상기 입력커패시터로 이동되어 상기 기준커패시터에 충전된 전하가 절반으로 나뉨에 따라 상기 기준전압이 변경되는 것을 특징으로 하는 스위치드-커패시터 D/A 변환기를 사용한 축차 비교형 A/D 변환기.Wherein the charge stored in the reference capacitor is transferred to the input capacitor in the first cycle and the reference voltage is changed as the charge charged in the reference capacitor is divided into half. Comparative A / D converter.
  6. 제5항에 있어서,6. The method of claim 5,
    제2사이클 시 상기 디지털데이터에 따라 상기 출력전압에 상기 변경된 기준전압을 가감하는 증폭기를 더 포함하는 것을 특징으로 하는 스위치드-커패시터 D/A 변환기를 사용한 축차 비교형 A/D 변환기.And an amplifier for adding or subtracting the changed reference voltage to the output voltage according to the digital data in a second cycle.
PCT/KR2017/010609 2017-06-19 2017-09-26 Successive comparison a/d converter using switched-capacitor d/a converter WO2018235997A1 (en)

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