JP2812169B2 - A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter for converting an analog input signal into a digital output signal.

[0002]

2. Description of the Related Art As a well-known A / D converter, a serial A / D converter as shown in FIG. 3 is known. This conventional A / D converter includes a sample-and-hold circuit 31 that samples and holds an input signal, a parallel A / D converter 32 that performs AD conversion on the output of the sample-and-hold circuit 31 and obtains upper bits, This parallel type A
D which converts the conversion result of the / D converter again into an analog signal
A / A converter 33, an analog subtraction circuit 34 for taking the difference between the input signal and the output of the D / A converter 33, a sample / hold circuit 35 for sampling and holding the output of the analog subtraction circuit 34, and a sample / hold A parallel A / D converter 37 for A / D converting the output of the circuit 35 to obtain lower bits, and an output of the A / D converter 32 and an output of the A / D converter 37 correspond to an analog input signal. And an adder 36 for determining a digital output. Such a serial-parallel A / D converter is excellent in high-speed performance, and can significantly reduce the number of elements, chip area, current consumption, and the like as compared with a completely parallel A / D converter.

On the other hand, a 1-bit A / D conversion cell (41-1 to 4-1) as shown in FIG.
There is known an algorithmic A / D converter in which 1-N, where N is a natural number, is cascade-connected (IEEE Jo).
urnal of Solid-State Circ
uits, vol. 25, no. 4, pp. 997-1
004, '90).

This A / D converter has a 1-bit A / D conversion cell 41 and outputs one bit at a time from the upper bits. The 1-bit A / D conversion cell 41 doubles the input current and compares it with the reference current. If the doubled input current is larger than the reference current, it outputs “1” as a digital output and simultaneously doubles the input current. Is subtracted from the reference current and output to the next stage. Conversely, if the doubled input current is smaller than the reference current, "0" is output as a digital output, and the doubled input current is output to the next stage. The 1-bit A / D conversion cells (41-1 to 41-N) are connected in cascade in n stages to constitute an A / D conversion device with n-bit resolution. In this A / D converter, the number of elements is small and current consumption can be reduced.

[0005]

However, the above-mentioned serial-parallel A / D converter has a parallel type A / D converter used internally.
Since the number of elements, area, and current consumption of the / D converter are still large, an internal parallel A / D converter has been a bottleneck when further reducing the power and size of the entire A / D converter.

In the above-mentioned algorithmic A / D converter, when the resolution is increased, the number of stages of cascade connection is increased, so that the conversion speed is reduced.
Since the precision required for the conversion cell becomes severe, 1 bit A
The problem is that the operation speed of the / D conversion cell itself becomes slow, and as a result, the conversion speed of the A / D conversion device becomes slow. Of these, the problem that the conversion speed becomes slow due to the increase in the number of stages in cascade connection can be solved by pipelining the 1-bit A / D conversion cell, but the required accuracy is severe and the operation speed of the 1-bit A / D conversion cell itself However, the slow problem cannot be solved by the prior art.

That is, as described above, it is difficult for these conventional A / D converters to achieve both high speed, low power, and small size. On the contrary, it has been difficult to increase the speed when trying to reduce the power consumption and size.

An object of the present invention is to provide an A / D converter capable of solving such problems and realizing high speed, low power and small size simultaneously.

[0009]

A / D conversion device of the present invention According to an aspect of the, A / D converter outputs a digital output signal of N-bit analog input signal into A / D (N is a natural number) met Te, parallel a for outputting the upper bits of the digital output signal of the analog input signal is a / D converted
/ D converter, a D / A converter for D / A converting the upper bits of the digital output signal, and an output of an analog subtractor for subtracting the analog input signal and the output of the D / A converter. 1-bit cell pipeline type A / D converter which performs A / D conversion and outputs lower bits of the digital output signal
D converter, the Ru A / D conversion device and an adder which determines the code of the digital output signal corresponding to said analog input signal and a lower bit of the upper bits and the digital signal of the digital output signal, Said 1
The bit cell pipeline type A / D converter has a first input
A first terminal connected to a current input terminal and a second current output
A first current mirror circuit having an end and a second input terminal are electrically connected.
And a current output terminal connected to the first current mirror.
Connected to a first current output of the circuit, the first current
A transistor with a conductivity different from that of the transistor that constitutes the mirror circuit
A second current mirror circuit comprising a transistor;
The currents of the first current mirror circuit and the second current mirror circuit
A third current mirror circuit in which the current input terminal is connected to the current output terminal
Path and the current output terminal of the third current mirror circuit.
A detection circuit for detecting whether the current is flowing, and a current input circuit
Connected to a second current output terminal of the first current mirror circuit
The current input circuit or the third current mirror circuit
And a means for switching between the current input circuit and the
And a current mirror circuit, wherein the fourth current mirror is provided.
The circuit detects a current input when the detection circuit detects a current.
When the path is the current input circuit of the third current mirror,
"1" is output as an output bit, and no current is detected.
If so, the second current output terminal of the first current mirror circuit
Output bit as well as connected current input circuit
To output “0” and output the current of the fourth current mirror circuit.
N2 bit cells having a current end as a current output terminal
It is composed .

[0010]

[0011]

[0012]

Further, the current output terminal of the bit cell of the A / D converter of the present invention is connected to the first current input terminal of the next-stage bit cell, and the N2 cells are connected in series. 1 as a current input terminal,
The current of Ir1 is input to the second input terminal of the first stage, and the current that becomes 1/2 of Ir1 is sequentially input to the second input terminals of the second and subsequent stages. The current gain is set to 1 except for the current mirror circuit of
It is also possible to adopt a configuration in which the output bits of the first stage are the most significant bits and the output bits of the second and subsequent stages are sequentially the bits from the higher order.

[0014]

Next, an A / D converter according to a first embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1 which is a block diagram showing the configuration of an A / D converter according to a first embodiment of the present invention, the A / D converter according to this embodiment samples and holds an analog input signal 13. And the input signal 9 held by the sample and hold circuit 1
A parallel A / D converter 2 having a 5-bit resolution for A / D-converting a 5-bit digital output signal 8; and a D / A converter for D / A-converting the 5-bit digital output signal 8 and outputting an analog signal 10 A converter 3 and input signal 9 described above
And an analog subtracter 4 for subtracting the analog output signal 10 from the analog output signal 10 and outputting an analog output signal 11.
2-4), a 1-bit cell pipeline type A / D converter 5 having a 4-bit resolution, a 5-bit digital output signal 8 and a 4-bit digital output signal (1
2-1 to 12-4) and an adder 6 for outputting a digital code 14 corresponding to the analog input signal 13.

Further, referring to FIG. 7, which shows a circuit configuration in which the A / D converter 2, the D / A converter 3, and the analog subtractor 4 having a 5-bit resolution are integrated, the A / D converter 2 is a reference voltage VRT and a reference voltage V
A resistor R for dividing RB, a node potential for dividing the reference voltage VRT and the reference voltage VRB, and an analog input signal VIN
And 32 comparators (COMP0-CM
OMP31) and comparators (COMP0 to COMP3)
An encoder 71 that encodes the output of 1) to obtain a 5-bit digital signal 8.

Further, the D / A converter 3 and the subtractor 4 have an integrated configuration 72, and include switches (Φ1, Φ2 and inverted Φ2) and 32 capacitor arrays (C0 to C31).
And the analog calculator 73 outputs the analog output signal 11.

When the analog input signal VIN is supplied to the parallel A / D converter 2 for A / D conversion, the capacitor array (C0 to C31) simultaneously samples the input signal (switch Φ1: high level, switch Φ2 : Low level). When the switch Φ2 becomes H, each capacitor is connected to each comparator (COMP0 to CO0) of the parallel A / D converter 2.
MP31), the output result Qi (if Vin ≧ VrI, Q
(If i = H, Vin <Vri, Qi = L) according to the reference potential VRT or the reference potential VRB, and redistribute the electric charges to simultaneously execute the D / A conversion and the subtraction. The result of the subtraction is output from the operational amplifier 73 as an analog output signal Vout.

Further, the sample and hold circuit 1 is shown in FIG.
It is composed of the circuit shown in FIG. The configuration of this sample-and-hold circuit is a well-known configuration example that is generally well-known, and a detailed description thereof will be omitted.

Next, the 1-bit cell pipeline type A / D converter 5 of the A / D converter according to the first embodiment of the present invention.
Is composed of a serial connection of 1-bit A / D conversion cells having a sample and hold function. As a configuration example of a 1-bit A / D conversion cell having a sample and hold function,
Current mirror circuit 2 including switch 20 shown in FIG.
1 and the 1-bit A / D conversion cell shown in the conventional example shown in FIG.

Next, the operation of the A / D converter according to the first embodiment of the present invention will be described.

Referring to FIG. 5, which is a timing chart showing the operation of this embodiment, a case of an A / D converter of an upper 5 bits (AD1) and a lower 4 bits (AD2) of an A / D converter is shown.

The timing chart shown here is an example, and differs when a sample and hold circuit is inserted between stages.

The sample-and-hold circuit SH has a period T10
, The analog input signal Vin (t1) is sampled and held for a period T11.

In a period T11, the upper parallel A / D converter 2 performs A / D conversion of Vin (t1) to obtain upper N1 bits. At the same time, the subtractor 4 is connected to the sample hold circuit SH.
Is sampled.

In the period T20, the sample hold SH samples the next analog input signal Vin (t2) and holds it for the period T21. Hereinafter, this data is Vin
Pipeline processing is performed in parallel with the processing of (t1).

In the period T20, the result of the A / D conversion by the upper-side parallel A / D converter 2 is returned to the analog signal 10 by the D / A converter 3 again. The subtracter 4 subtracts the output 10 of the D / A converter 3 from the input signal sampled in the period T11, and outputs a subtraction result 11. The output 11 of the subtracter 4 is the first 1-bit A / D of the algorithmic A / D converter 5.
It is sampled by the D cell (AD2-1).

In the period T21, the bit cell (AD2-
A / D conversion is performed in 1), and an analog signal is transmitted to a subsequent bit cell (AD2-2) to obtain a lower bit, and is sampled in the bit cell (AD2-2).

In the period T30, the bit cell (AD2-
A / D conversion is performed in 2), and a bit cell (AD2)
-3) An analog signal is transmitted.

Thereafter, A / D conversion is similarly performed in the bit cells (AD2-3 and AD2-4), and the lower bit is set to 1
Bit by bit.

The adder 6 has a register, and a period T1
1 and the output of the upper-side A / D converter 2 and the period T
The output (1) of the bit cell (AD2-1) output at 21
2-1) is added to perform error correction of the upper N1 bits. Thereafter, the bit cell (AD2-
2), the output 12-3 of the bit cell (AD2-3) output in the period T31, and the output (12-4) of the bit cell (AD2-4) output in the period T40.
Are the lower bits, and after all data have been collected,
The digital code 14 is output in the period T41.

Next, the optimum point of the configuration of the resolution of the upper A / D converter and the resolution of the lower A / D converter of the A / D converter of the present invention will be described.

The resolution of the entire serial-parallel A / D converter is N bits, the resolution of the upper A / D converter (AD1) is N1 bits, and the resolution of the lower A / D converter (AD2) is N2 bits. In a serial-parallel A / D converter provided with digital error correction means for correcting the conversion error of AD1 at the time of lower-order conversion, when the digital error correction is 1 bit (AD1
) And the most significant bit of AD2 overlap), and N = N1 + N2-1......... At this time, the precision required for AD1 and AD2 is the precision corresponding to each resolution. That is, AD1 requires N1 bit precision, and AD2 requires N2 bit precision. Here, m-bit precision means that the error is equal to or less than 0.5 LSB of m bits. 1 LSB is 1 /
Since 2 ^m · FS (FS is the full scale of the AD converter), the error with the m-bit precision is (が) ^{(m + 1)} · F
S or less.

A conventional serial / parallel A / D converter,
While both AD1 and AD2 are parallel A / D converters, AD1 is an N1 bit parallel A / D converter and AD2 is an N2 bit algorithmic A / D converter in the present invention. As a result, an optimum configuration can be obtained by a trade-off between conversion speed and area / power consumption.

Let Pc be the power consumption of one comparator used in the parallel A / D converter, and Pa be the power consumption of one 1-bit A / D cell used in the algorithmic A / D converter. Although each of the power consumptions Pc and Pa is strictly different depending on the resolution and the operation speed, the A / D converter composed of the parallel A / D converter and the algorithmic A / D converter as considered in the present invention. When applied to a vessel, 1
Ultra-high-speed A / D converters having a conversion speed of 00 MHz or more and high-resolution A / D converters having a resolution of 16 bits or more are out of scope and may be considered to be approximately constant. As a result, the power consumption P of the entire A / D converter of the present invention is obtained.
t is Pt = ^2N1 · Pc + N2 · Pa (2) = ^2N1 · Pc + (N−N1 + 1) except for a digital part such as a digital adder.・ Pa ………………… (3)

The operating speed is limited by the operating speed of a 1-bit A / D cell when the algorithmic A / D converter is operated in a pipeline. Depending on the transistor size used inside the 1-bit A / D cell, the smaller the transistor size, the higher the speed of operation. However, when the transistor size is small, the relative accuracy of the transistor deteriorates, so that there is a trade-off between speed and accuracy. Therefore, the higher the resolution N2 of the algorithmic A / D converter becomes, the higher the speed becomes.

Here, the relationship between the transistor size and the accuracy and speed is specifically assumed as follows, and the optimum configuration is obtained from the relationship between the configuration of the A / D converter and (speed / power consumption). .

First, it is assumed that the accuracy is proportional to the transistor size (channel length of the transistor) (doubling the transistor size improves the accuracy twice, that is, one bit). This is an assumption that the processing accuracy is constant because the relative accuracy of the transistor is substantially determined by the dimensional accuracy of the transistor.

Next, the operation speed of the 1-bit A / D cell is:
Assume that it is inversely proportional to the 1.5th power of the channel length of a transistor used in a 1-bit A / D cell. This is for the following reason.

If the resolution of the algorithmic A / D converter changes, the channel length L of the transistor must be changed to obtain the required accuracy.
/ L (W is the channel width) is assumed to be constant. Then, since the gate capacitance is proportional to the product of the channel width W and the channel length L, it is proportional to the square of the channel length L. The operating speed is determined by the charge and discharge of the capacity. If the flowing current is constant, the speed is inversely proportional to the capacity value. If the capacitance is only the gate capacitance, the operation speed is inversely proportional to the square of the channel length L. However, there are actually components that are not proportional to the square of the channel length L, such as the wiring capacitance and the parasitic capacitance of the source and drain. Considering that, the operation speed is 1.5 times the channel length L.
It was assumed to be inversely proportional to the power.

Since it is assumed that the accuracy is proportional to the channel length L and the speed is inversely proportional to the 1.5th power of the channel length L, the speed is inversely proportional to the 1.5th power of the accuracy. However, if the accuracy is lower than the accuracy that can be realized by the minimum channel length of the transistor, the speed is not improved even if the accuracy is reduced.

Under the above assumption, the upper A / D converter (AD1) and the lower A / D converter (A1) of the 8-bit A / D converter are used.
Consider the overall performance due to the difference in resolution in D2).

First, power consumption is given by equation (3).
At this time, it is assumed that Pa = Pc and the power consumption Pc is standardized. Since the power consumption is dominated by the power consumption of the parallel A / D converter, Pa = 0.5Pc or Pa = 2 · P
Even if c, there is no big difference in the following discussion. Next, as for the operation speed, the operation speed when AD1 is 2 bits and AD2 is 7 bits is 1, and the accuracy (resolution N2) of AD2 is 1.
It is assumed to be inversely proportional to the fifth power. However, usually analog LSI
Considering a 1 μm CMOS process as a standard process used in the above, it is considered that 4-bit accuracy can be realized by a transistor having a channel length of 1 μm. Therefore, when AD2 is 4 bits or less, the operation speed is equal to that of 4 bits. Table 1 below shows the result of calculation for each configuration in consideration of the operation speed / power consumption as the performance evaluation number F of the A / D converter.

[0044]

[Table 1]

From this table, it can be said that the configuration in which AD1 is 5 bits and AD2 is 4 bits is the optimal configuration in terms of operating speed / power consumption. However, if speed is the most important consideration for power consumption, other configurations are conceivable. Table 1 shows that
Since the results are discussed based on the above assumptions, the optimum configuration will differ if the assumptions change. By the way, in the conventional two-step serial / parallel A / D converter, the operation speed is set to the maximum value of 22.6 in Table 1, and calculation for each configuration is as shown in Table 2.

[0046]

[Table 2]

The results in Table 2 show that, under the above-mentioned assumptions, the A / D converter of the present invention is compared with the conventional two-step serial / parallel A / D converter.
It can be said that the converter is superior in operation speed and power consumption.

Next, an A / D converter according to a second embodiment of the present invention will be described.

This embodiment is different from the first embodiment in that a voltage / current conversion circuit 81 shown in FIG. 8 is used instead of the D / A converter 3 and the analog subtractor 4 of the A / D converter. Has the same configuration as the A / D converter of the first embodiment.

That is, when the D / A converter 2 and the subtraction circuit 72 shown in FIG. 7 are used, the output signal of this arithmetic circuit is a voltage. On the other hand, an input signal of an algorithmic A / D converter using a 1-bit AD cell as shown in FIG. 2 is a current. Therefore, a voltage-current conversion circuit is required between the subtraction circuit and the algorithmic A / D converter.
One example is shown in FIG.

If a current is output by a circuit configuration for performing current subtraction as a D / A conversion and subtraction circuit, a voltage-current conversion circuit is unnecessary.

The operation of this embodiment is the same as the operation of the first embodiment, and a detailed description thereof will be omitted.

Next, an A / D converter according to a third embodiment of the present invention will be described.

Referring to FIG. 9 showing the configuration of a 1-bit cell pipeline type A / D converter of the A / D converter of this embodiment, this 1-bit cell pipeline type A / D converter has a first (The current is in the direction of the arrow) Iin input to the input terminal 91 is multiplied by the current gains A ₁ and A ₁ ′ by the first current mirror circuit 93 and output to the output terminals 95 and 100, respectively.

On the other hand, the current Ir1 input to the second input terminal 92 is multiplied by A2 in the second current mirror circuit 94 and output to the output terminal 95.

At this time, if A ₁ I _in > A ₂ I _r1 ,
The current of (A ₁ I _in −A ₂ I _r1 ) is input to the third current mirror circuit 96. Therefore, a current flows through the output terminal of the current mirror circuit 96.

However, if A ₁ I _in <A ₂ I _r1 , the current of the A ₂ I _r1 cannot flow to the output of the current mirror circuit 94, and the potential of the output terminal 95 drops. No current is input. Also, when A ₁ I _in = A ₂ I _r1, no current flows through the current mirror circuit 96 because the current flows through the current mirror circuit 94 flowing on the output side of the current mirror circuit 93.

The current detection circuit 97 is a circuit for detecting whether or not a current is flowing through the current mirror circuit 96. As a specific example, it is composed of a resistor and an inverter as shown in FIG. When the current flows through the current mirror circuit 96, the current flows through the resistor R9 connected between the output terminal of the current mirror circuit 96 and the constant voltage source, so that the input potential of the inverter decreases. As a result, the output b of the inverter becomes a high level, that is, "1". However, if no current flows through the current mirror circuit 96, no current flows through the resistor R9, so that the input potential of the inverter remains at a high level and the output b of the inverter becomes a low level, that is, "0".

Thus, the output b of the current detection circuit 97
Is "1" if a current is flowing through the current mirror circuit 96,
If it is not flowing, it can be set to “0”. In the current detection circuit 97, a similar function can be realized by using a transistor instead of the resistor R9, and a dynamic circuit can be easily formed by inserting a switch. This output b becomes the output bit of the 1-bit cell as it is.

The input current circuit is switched by the switch S1 in the current mirror circuit 98 in accordance with the output b of the current detection circuit 97. When the output b is "0", it is connected to the input current circuit connected to the second output terminal 100 of the current mirror circuit 93, and when the output b is "1", it is connected to the current input circuit of the current mirror circuit 96. Be replaced. Therefore, when the output b is “0”, the output current of the current mirror circuit 98 has a current gain of A4
When at ^{_{A 4 (A 1 'I in}} ), the current of the _{^{A 4 (A 1 I in -A}} 2 I r1) when the output b is "1".

Next, an A / D converter according to a fourth embodiment of the present invention will be described.

Referring to FIG. 10, the A / D of this embodiment is shown.
The conversion device has a 1-bit cell series connection configuration. At this time, the current gain of the current mirror circuit is A ₁ = A ₁ ′ = A ₂
= A ₄ = A ₁ . Therefore, in this configuration, the current input to the first input terminal of the 1-bit cell is I1,
When the current input to the input terminal 92 of the I2 I _1>
If I ₂ b = 1, the output current _{I 1 -I 2, I 1 ≦} I
If ₂ b = 0, the output current is I _1. When the current I ₂ of the n-th stage and the current I _rn Since the second and subsequent stages will become halves of sequential current _{I r1 I r2 = (1/2)} I r1, I r3 = (1/2 ) I _r2 = (1/2 ² ) I _r1 ,..., I _rn = (1/2) I _{r (n-1)} = (1/2 ^n-1 = (1/2 ^n-1 ) I _r1 ............ is (4). Thus the input current in of the n-th stage when the current to the Iin input to the first input terminal of the first-stage _{th, I n = I in -b 1} I r1 -b 2 _{I r2 - ... -b n -1I rn} -1 = I in -b 1 I r1 - (1/2) b 2 I r1 - (1/2 2) b 3 I r1 - ... - (1/2 n- ²⁾ a _{b n-1 I r1 ............................................................... (} 5). However b _i is the output bit of 1 bit cell of the i-th stage .

[0063] and the current I _n represented by formula (4) (1 /
Bn is determined by the magnitude relation of 2 ^n-1) I _r1. The result is, as is well known, that 2I _r1 is full scale, output bit b ₁ is the most significant bit, and output bit b
An A / D converter in which ₂ or less bits are sequentially set from the upper bits.

Accordingly, an A / D converter having a resolution of n bits, where n is the number of 1-bit cells connected in the second, can be obtained.

In this A / D converter, the vertically stacked transistors in the current path between the positive power supply voltage and the negative power supply voltage in each 1-bit cell configuration are NMOSFET and PMOS.
Since there is only one FET each, and no switch is included in the current path, it is not limited by the on-resistance.

Therefore, in this embodiment, an A / D converter suitable for lowering the voltage can be provided.

Although the sample and hold circuit 1 is used in the embodiment shown in FIG. 1, the sample and hold circuit may be externally attached to the A / D converter, or may not be used.

When the configuration of the present invention is compared with the conventional configuration shown in FIG. 3, a 1-bit cell pipeline type A / D converter is used in place of the conventional parallel A / D converter for the A / D converter for obtaining lower bits. By using the device, the area and power consumption of the subsequent stage can be reduced. Further, since the lower bits are obtained, the accuracy required for the 1-bit cell pipeline type A / D converter may be as high as the resolution of the lower bits, and the accuracy of the entire A / D converter is required as in the conventional case. Not done.

Therefore, the operation speed of the 1-bit cell pipeline type AD converter shown in FIG.
Compared to the case where each 1-bit AD conversion cell is pipelined in order to increase the speed of the / D converter, the conversion speed can be increased because accuracy is not required, and the conversion of the entire AD converter is accordingly performed. Speed can be increased.

Therefore, in the present invention, the conventional parallel type AD
A / D converter with low power consumption and small size compared to the converter
Further, it is possible to provide a high-speed A / D converter as compared with a conventional 1-bit cell pipeline type A / D converter.

[0071]

As described above, according to the present invention, the power consumption and the size of the A / D converter are smaller than those of the conventional parallel A / D converter.
It is possible to provide a high-speed A / D converter as compared with the conventional 1-bit cell pipeline type A / D converter.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of an A / D converter according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a 1-bit cell pipeline type A / D converter of the A / D converter shown in FIG.

FIG. 3 is a diagram showing a configuration of a conventional A / D converter.

4A and 4B are diagrams showing a configuration of a 1-bit cell pipeline type A / D converter of a conventional A / D converter, in which FIG. 4A shows a configuration for one bit, and FIG. FIG. 3A is a diagram in which 4 bits are connected in series.

FIG. 5 is a time chart explaining the operation of the A / D converter shown in FIG. 1;

6A and 6B are diagrams illustrating a configuration example of a sample and hold circuit of the A / D converter illustrated in FIG. 1, in which FIG. 6A is a diagram illustrating one configuration example, and FIG. 6B is a diagram illustrating another configuration example; FIG.

7 is a diagram showing a configuration of an upper-side A / D converter of the A / D converter shown in FIG. 1 and an integrated configuration of a D / A converter and a subtractor.

FIG. 8 is a diagram illustrating a configuration of a voltage-power supply conversion circuit of an A / D converter according to a second embodiment of the present invention.

FIG. 9 is a diagram illustrating a configuration of an A / D converter according to a third embodiment of the present invention.

FIG. 10 is a diagram illustrating a configuration of an A / D converter according to a fourth embodiment of the present invention.

[Explanation of symbols]

1, 31, 35 Sample hold circuit 2, 32, AD1 Upper A / D converter 3, 33, DAC D / A converter 4, 34 Subtractor 5, 37, AD2-1 to AD2-4 Lower A / D converter 6,36 Adder 7,72 Integrated D / A converter 8,38 Upper A / D converter output 9 Sample hold circuit output 10 D / A converter 11 Subtractor output 12-1 to 12- 4 Lower side A / D converter output 13, VIN Analog input signal 14 Digital output signal 20 Switch 21 Current mirror circuit 41, 41-1 to 41-4 Bit cell 42, 42-2 to 42-4, b1 to bn Digital output 43, 43-1 to 43-3 Analog output 44, 44-1 to 44-4 Analog input 71 Encoder 73, 82 Operation unit 81 Voltage-current conversion circuit C0 to C31 Sita COMP1~COMP31 comparator 91 input terminal 93,94,96,98 current mirror circuit 95,100 output terminal 97 the current detection circuit

Claims (2)

(57) [Claims] 1. A / D conversion of an analog input signal to N
Bit (N is a natural number) a A / D converter for outputting a digital output signal of the analog input signal A /
A parallel A / D converter for D-converting and outputting the upper bits of the digital output signal; a D / A converter for D / A-converting the upper bits of the digital output signal; A 1-bit cell pipeline type A / D converter for A / D converting an output of an analog subtractor for performing subtraction with an output of an A / A converter and outputting lower bits of the digital output signal; All upper bits of an adder which determines the code of the digital output signal corresponding to said analog input signal and a low-order bit of the digital signal to the Ru a / D conversion apparatus comprising a
And the 1-bit cell pipelined A / D converter has a first
Input terminal is connected to the current input terminal and the first and second power
A first current mirror circuit having a current output terminal, and a second input terminal
Is connected to the current input terminal, and the current output terminal is connected to the first power supply terminal.
A first current output terminal of the current mirror circuit;
Conductivity different from the transistors that make up the current mirror circuit
Current mirror circuit composed of neutral transistors
And the first current mirror circuit and the second current mirror
A third current whose current input is connected to the current output of the circuit;
A mirror circuit, and a current output terminal of the third current mirror circuit
A detection circuit for detecting whether a current is flowing through the
An input circuit for providing a second current output of the first current mirror circuit;
Terminal or a current input circuit connected to the third terminal.
Equipped with means for switching between the current input circuit and
And a fourth current mirror circuit,
The current mirror circuit is activated when the detection circuit detects a current.
The current input circuit is a current input circuit of the third current mirror.
Outputs “1” as an output bit at the same time
If not, a second current of said first current mirror circuit
At the same time as the current input circuit connected to the output terminal,
And outputs "0" as a signal to the fourth current mirror circuit.
The bit cell having the current output terminal of
An A / D conversion device comprising two arrays . 2. The current output terminal of the bit cell is connected to:
Connected in series with the first current input of the bit cell of the stage
N2 connected, the first current input terminal of the first stage bit cell
Is a current input terminal, and Ir1 is connected to the second input terminal of the first stage.
, And sequentially input to the second and subsequent input terminals of the second and subsequent stages.
Input a current that is 1/2 of Ir1 and
The current gain is 1 except for the third current mirror circuit.
The output bit in the first stage is the most significant bit, and
It is special that the descending output bits are
The A / D converter according to claim 1, wherein