JPS6029028A - High speed analog-digital converting circuit - Google Patents

Abstract

PURPOSE:To attain high speed A/D conversion by sampling and holding an input data dividedly at plural sample holding circuits, applying A/D conversion and then synthesizing the data. CONSTITUTION:An analog signal inputted from an input terminal 22 is sampled sequentially in the N-set of separate timing by the N-set of sample holding circuits SH1, SH2... and held for N times the sampling time. The N-set of A/D converting circuits AD1, AD2-ADN receive the data, they conduct A/D conversion with a time N times the sampling time and the result is outputted sequentially with the separate timing. The data outputted are synthesized by a data synthesis circuit 20, the result is outputted from an output terminal 23 and the operation above is controlled by a control circuit 21.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a high-speed analog-to-digital conversion circuit (hereinafter referred to as A).
A/D conversion circuit (abbreviated as A/D conversion circuit)
Typical conventional methods for converting circuits are: (1) successive approximation method, (2) cyclic method, (3) integral method, and (4) parallel method.
etc. Each method has its own advantages and disadvantages, but in principle the fastest method is the parallel processing type A/
It is generally considered to be a D conversion circuit. Since the purpose of the present invention is a high-speed A/D conversion circuit, explanations of other methods that are inferior in speed will be omitted, and the parallel method A/D conversion circuit will be omitted.
/ Let's briefly touch on the D conversion circuit.

FIG. 1 is a simple configuration diagram of the conventional parallel processing type A/D conversion circuit, which is considered to be the fastest in principle. In FIG. 1, the reference voltage is applied from terminals 11 and 12, and the reference voltage is resistance-divided by (K-1) resistors RI to RK-1, and comparators OMP to OMPX are connected to each intermediate potential. The analog input voltage of the signal under test is applied from the terminal 13 to the first input terminal of each of the comparators OMF, -OMPK.
The signals are input to the input terminals, the respective humparators compare the potentials, and the results are input to ten encoders and latch circuits, respectively, and output as encoded digital signals from the output terminal 14. The above circuit operations are controlled by a clock signal input from the clock input terminal 15. The parallel processing type A/D conversion circuit described above has the number of comparators corresponding to the total number of states, so the analog signal input voltage can be determined in one clock cycle, so high-speed A/D conversion can be performed. . In order to achieve faster conversion in this parallel processing type A/D conversion circuit, it is first necessary to increase the frequency of the clock that determines the sampling frequency, but eventually a limit is reached. In this case, the obstacles generally occur in the two comparators OMF to OMpK shown in Fig. 1, which are connected to the first human power terminal and the first terminal to which the resistor-divided voltage of the input analog signal voltage 6 reference voltage is input, respectively. This is the responsiveness of the comparator where the voltage difference between the two input terminals is the smallest. In other words, it is necessary to determine in a short time which potential is larger or smaller, but the smaller the potential difference, the longer it takes. Therefore, similarly, if the number of bits of the digital signal output as an h/D conversion circuit is increased, the minimum value of the voltage difference between the first input terminal and the second input terminal of the comparator will further decrease, and the responsiveness of the comparator will deteriorate. / The limit sampling frequency as a D conversion circuit also decreases. Therefore, when a high-speed A/D conversion circuit with a large number of bits is required, even the parallel processing type A/D conversion circuit, which has traditionally been thought to be the fastest in principle, naturally has its limits, and a faster one is needed. The circuit method was considered.

The present invention provides a circuit system that performs even faster A/D conversion under the conditions of the same number of pits and the same device. The present invention will be explained in detail below.

Figure 2 is a block diagram showing the circuit configuration of the present invention. In FIG. 2, 22 is an input signal 0 terminal into which an analog signal as a signal to be converted is input. 8H,,EIH2
,...8HN are N sample and hold circuits, each of which samples the input signal at different timings and holds the sampled analog voltage. A.D.

eADtw・・・・・・ADH is N h/
This is a D conversion circuit. The A/D conversion circuit is A/D
Any A/D conversion circuit of the various types mentioned above may be used as long as it has the function of a conversion circuit, but in order to pursue high speed, a parallel processing type A/D conversion circuit is most desirable. 20 is a data synthesizing circuit, and the N pieces of A
/ AD, which is a D conversion circuit, AD,...
...Takes in each digital output signal of ADN and synthesizes it.

23 is an output terminal for the digital signal synthesized by the data synthesis circuit 20. 21 is a control circuit that controls the N sample and hold circuits, N A/D conversion circuits, and data synthesis circuit. In addition, the input signal terminal 2
2 is the N sample bold circuits SH, , sH,
,......Connected to the input of 8HN.

The N sample and hold circuits ""1*"He
@・・・・・・・・・Each output of 8HN is the above N number of A
/ D conversion circuit AD1 * AD! ＊・・・・・・・・・
. . . are connected to the inputs of the ADN. The N A/D conversion circuits AD1, AD, . . .
. . . Each output of the ADN is input to the data synthesis circuit 20. From the control circuit 21, the sample and hold times flf5" Ht m 8Hz m
. . . BHN, the A/D conversion circuits AD1, AD, . . . ADN, and the data synthesis circuit 2o are each connected with a control signal.

Now, FIG. 3 is a timing chart showing the operation of each circuit in the circuit of FIG. 2, which is the circuit of the present invention. In FIG. 3, (α) shows the sampling timing of N sample-and-hold circuits, (b) shows the hold timing of the N sample-and-hold circuits, and (C) shows the timing of N AD conversions. 3 illustrates the timing of the output of the converted digital signal of the circuit; Also, (α) and (h
)9(C), the time of high potential represents the timing of operation. In addition, the timing charts numbered 1 to N correspond to (α) and (h), and (C) corresponds to the numbers 1 to N. Then, N A/D conversion circuits AD
It corresponds to the numbers 1 to N of 1 to ADH.

In the circuit of FIG. 2 of the present invention, the analog signal of the signal to be measured inputted from the input signal terminal 22 is processed into N sample-and-hold circuits SR, SH2, . . . as shown in the timing chart of FIG. 3 (α). . . . Sampling is performed in order of N separate timings TO by 8H9.

As shown in Fig. 3 (Ch), the sampled data is held for a time that is N times the sampling time, including the sampling time. The N A/D conversion circuits receive the respective data and perform A/D conversion operations, respectively, taking a time N times the sampling time. N h/D conversion circuits A DHr A D2 e
. . . The ADN sequentially outputs values obtained by converting data at different sampling timings at different timings as shown in FIG. 3(C). A data synthesis circuit 20 synthesizes the output data of the N A/D conversion circuits and outputs the synthesized data from an output terminal 23 as a digital output signal. The control circuit issues control signals so that the above operations can be performed without any trouble. Now, from the above explanation of the circuit operation, the number of bits of each of the N A/D conversion circuits in the circuit of FIG. 2 is B. , and the maximum sampling frequency determined from the limit of each response is f. , and if the time required for conversion is To, then the circuit in FIG. 2 spends the time equivalent to the sum of the sampling time and sample hold time in the timing chart in FIG. 3 for conversion by the N A/D converter circuits. It takes 7 hours. It can be seen that it is possible to operate even if it is set equal to . Therefore, in the timing chart of FIG. 3, the sampling time T' of (α) is T, = T. Therefore, the sampling frequency f' is f''N/.

And also T. The number of bits B at the time. N pieces of data are sequentially converted and outputted from the output terminal 23. Therefore, in the circuit shown in Fig. 2, A/D conversion circuit A
The number of bits of each ADN is Bo, and the highest sampling frequency of each is f. However, the number of bits is B for the circuit of the present invention shown in FIG. The sampling frequency is A of Nfo.
/ It can be seen that it operates as a D conversion circuit.

As described above, the invention is to realize an A/D conversion circuit that is N times faster overall by using N basic A/D conversion circuits, sampling at different timings, and dividing the conversion. . Furthermore, if the number of A/D conversion circuits is increased according to the circuit of the present invention, in principle, any number of high-speed A/D conversion circuits can be obtained until the responsiveness limit of the sample-hold circuit or data synthesis circuit is reached. I can do 2 things. Therefore, the present invention utilizes the parallel A/
It can also be said that this is an A/D conversion circuit system that is even faster than a D conversion circuit. In addition, in the timing chart of Fig. 5, the simplest example is shown for ease of understanding, but N
The essence of the present invention is the relationship between the N sample hold circuits, the N A/D conversion circuits, and the data synthesis circuit. While holding with the hold circuit
If the configuration is such that each A/D conversion circuit divides and converts each piece of data, and then synthesizes the data, it doesn't matter if there are delicate timings or timings for other operations. is a minor problem. Furthermore, if the circuit of the present invention is constructed from the same integrated circuit, N pieces of A
/ Since the characteristics of the D conversion circuits AD1 to ADN are the same and the parasitic capacitance at the time of connection between each circuit is also reduced, it is more effective for speeding up.

[Brief explanation of the drawing]

1 [Δ is a circuit diagram of a parallel type A/D conversion circuit, which is conventionally said to be the fastest in principle, FIG. 2 is a circuit diagram of a high-speed A/D conversion circuit of the present invention, and FIG. FIG. 3 is a timing chart diagram showing the operation of the circuit shown in the figure. 10... Latch and encoder circuit 11.12
...Reference voltage terminal 13...Input terminal 14...Output terminal 15...Clock input terminal R1 to RK-1'°゛°°°Resistance OMP, ~OMPK...Comparator 20
...Data synthesis circuit 21 ...Control circuit 22 ...Input signal terminal 26 ...Output terminal SH1-8HN ...Sample hold circuit AD
1~ADN・・・A/D conversion circuit 3rd (2)

Claims (3)

[Claims] (1) N sample-and-hold circuits (N is a positive integer of 2 or more) that sample and hold input data, and N analog-to-digital conversion circuits that convert the data of the N sample-and-hold circuits, respectively. , a data synthesis circuit that synthesizes the output data of the N analog-to-digital conversion circuits, and a control circuit that controls each of the above circuits, and divides input data at N timings to sample and hold the data. 1. A high-speed analog-to-digital converter circuit, characterized in that it is configured to operate at higher speeds by performing shared processing among N analog-to-digital converter circuits and then synthesizing data. (2) The high-speed analog-to-digital conversion circuit according to claim 1, wherein the N analog-to-digital conversion circuits are all parallel processing type analog-to-digital conversion circuits. (3) A high-speed analog-to-digital conversion circuit according to claim 1 or 2, wherein each of the circuits is built into the same integrated circuit.