CN114285414B - Scaling type increment type analog-to-digital conversion method and converter - Google Patents

Abstract

An analog-to-digital conversion method and a scaled delta analog-to-digital converter, wherein the scaled delta analog-to-digital converter ADC comprises a successive approximation type ADC used as a coarse converter and a second order delta ADC used as a fine converter, which comprises two integrators connected in series, wherein each integrator comprises a zero crossing detection circuit. In the method, two control signals phi 1 and phi 2 are set to alternately control sampling and integration of the two integrators, and the effective switching of phi 1 and phi 2 is controlled according to zero crossing signals generated when the integration process of each integrator is completed, so that the phi 1 and phi 2 become self-timing control signals through mutual pushing of the two integrators, and the self-timing execution of the coarse conversion process and the fine conversion process is controlled through integral time sequence design.

Description

Scaling incremental analog-to-digital conversion method and converter

Technical Field

The present invention relates to the technical field of analog-to-digital converters (ADC), and in particular to a zoom incremental analog-to-digital conversion method and converter (Zoom Incremental ADC).

Background technique

With the development of electronic information technology, the application of sensors is becoming more and more extensive. Sensors are devices that convert physical signals in reality, such as temperature, humidity, gas concentration, and various biological signals, into electrical signals, so that they can accurately and quickly measure physical signals containing important information with the help of the powerful ability of electrical signal processing. At present, wearable or portable sensor systems are playing an increasingly important role for purposes such as health, medical and environmental monitoring. Due to the requirements of portable applications, these sensor systems need to have the characteristics of low power consumption, small size, low cost, and simple circuit structure.

The core of the sensor system is usually the ADC, which converts the time- and amplitude-continuous electrical signals output by the sensor into digital signals, which can then be easily and reliably processed, stored, and transmitted. The two main types are the Successive Approximation Register ADC (SAR ADC) based on binary search and the Oversampling and Noise Shaping ΔΣ ADC.

SAR ADC can achieve faster conversion speed, thus having higher energy efficiency and meeting the requirements of low power consumption. However, due to the mismatch of components, in order to achieve higher measurement accuracy (such as >12bit), some additional technical means are usually required, which will lead to higher power consumption or cost.

Oversampled noise-rectified ΔΣ ADC can achieve higher resolution and accuracy. However, due to the use of oversampling technology, low-order ΔΣ ADC usually requires a longer conversion time. In order to meet the stability requirements, the dynamic range of the input signal of high-order ΔΣ ADC is often limited, and the circuit complexity is relatively high.

In practical applications, the bandwidth requirements of sensor systems used to measure environmental parameters or biological signals are usually not high, for example, they are usually low frequency or close to DC, but they need to meet the requirements of high precision, high linearity and low power consumption, so oversampling noise rectification type ΔΣ ADC is usually used. In such systems, the ADC often works in a low duty cycle mode, that is, it is reset at the beginning of each operation, and it is turned off after completing a conversion until it is triggered by the next signal to reduce unnecessary static power consumption. This type of ADC is called an incremental ADC.

A solution that has emerged in recent years is a hybrid ADC that combines these two types of converters, namely a zoom incremental ADC. See “Y. Chae, K. Souri, and K. A. A. Makinwa, “A 6.3 μW 20bit incremental zoom-ADC with 6 ppm INL and 1 μV offset,” IEEE J. Solid-StateCircuits, vol. 48, no. 12, pp. 3019–3027, Dec. 2013.” The conversion process of the zoom ADC is divided into two steps. First, the SAR ADC is used for coarse conversion to quickly determine the approximate range of the signal. Then, the ΔΣ ADC is used to perform fine conversion on the reduced range to complete the accurate measurement of the signal.

The scaled incremental ADC combines the high efficiency of the SAR ADC and the high precision of the ΔΣ ADC, and is an ideal solution for low-power sensors. However, its potential problem is that the design of the timing circuit is relatively complex. In order to avoid the need for a high-speed clock and improve conversion efficiency, the SAR ADC is usually implemented in an asynchronous manner. The ΔΣ ADC used for fine conversion still requires an external high-speed clock signal to achieve oversampling, which will increase the complexity of the system, as well as power consumption and cost. Although there are also studies on self-timed ΔΣ ADCs, see "C.Chen, Z. Tan and M. A. P. Pertijs, "A 1V 14b self-timed zero-crossing-basedincremental ΔΣ ADC," 2013 IEEE International Solid-State CircuitsConference Digest of Technical Papers, 2013, pp. 274-275, doi: 10.1109/ISSCC.2013.6487732.", there is still no overall design to integrate a local asynchronous and a local synchronous subsystem.

Summary of the invention

According to one aspect of the present invention, an analog-to-digital conversion method is provided, using a scaling incremental ADC, which includes a coarse converter and a fine converter, wherein:

The coarse converter is a successive approximation ADC, and the fine converter is a second-order incremental ADC, which includes a first integrator and a second integrator connected in series, and each integrator includes a zero-crossing detection circuit ZCBC (Zero-Crossing-Based Circuits);

The scaling incremental ADC is provided with a first control signal φ1 and a second control signal φ2, wherein when φ1 is effective, the first integrator is controlled to start sampling and the second integrator is controlled to start integration, and when φ2 is effective, the first integrator is controlled to start integration and the second integrator is controlled to start sampling. When the integration process of each integrator is completed, a zero-crossing signal is generated to control the switching between the effective φ1 and the effective φ2. The two integrators promote each other, so that φ1 and φ2 become self-timing control signals;

The method comprises the steps of:

Obtain a start signal; start the coarse conversion process performed by the coarse converter according to the start signal, adopt a successive approximation method, start from the most significant bit MSB, and run N1 cycles, where N1 is an integer greater than or equal to the number of bits of precision of the coarse conversion. In each cycle of the coarse conversion, sample the input voltage Vin to be converted through φ1 control, generate a predicted voltage value corresponding to the current bit through φ2 control, quantize the difference between the predicted voltage value and Vin through a comparator, and determine the data of the current bit according to the quantization result;

After all the cycles of coarse conversion are completed, the predicted voltage value Vref corresponding to the result m of the coarse conversion is used as the reference voltage for fine conversion, and the fine conversion process performed by the fine converter is started. The oversampling noise shaping method is used to run N2 cycles. N2 is an integer determined according to the conversion accuracy requirements for Vin. In each cycle of fine conversion, two integrators are alternately controlled by φ1 and φ2 to perform sampling and integration, and the outputs of the two integrators are combined and quantized by a comparator to output the corresponding bit sequence.

According to another aspect of the present invention, a scaling incremental ADC is provided, comprising:

A coarse converter, which uses a successive approximation ADC to perform a coarse conversion process;

A fine converter, which uses a second-order incremental ΔΣ ADC for performing a fine conversion process, and includes a first integrator and a second integrator connected in series, each integrator including a ZCBC;

The state control module is used for controlling and executing the aforementioned analog-to-digital conversion method.

According to the zoomable incremental ADC solution of the present invention, the overall timing is self-controlled through an overall unified self-timing design, and the timing control requirements in the two stages of coarse conversion and fine conversion are coordinated, thereby eliminating the external clock requirements in the traditional zoomable incremental ADC, solving the complex timing circuit design problem of the zoomable incremental ADC, and its additional cost and power consumption problems. The difficulty of system integration of the zoomable incremental ADC in practical applications is greatly reduced, and the robustness and reliability of this type of ADC are improved.

The following is a detailed description of specific examples according to the present invention in conjunction with the accompanying drawings. The words used herein to indicate the order, such as "first", "second", etc., are only used for identification and do not have an absolute meaning.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the principle of a zoomable incremental ADC according to the present invention;

FIG2 is a system block diagram of a zoomed incremental ADC according to the present invention;

FIG3 is an overall design diagram of a scaling incremental ADC according to an example of the present invention;

FIG4 is a schematic flow chart of a scaling incremental analog-to-digital conversion method according to the present invention;

FIG5 is a timing diagram of a conversion process of a conversion method according to an example of the present invention;

FIG6 is a schematic diagram of a comparator-based switched capacitor integrator applied to the present invention;

FIG7 is a timing diagram of the integrator in FIG6 during a fine conversion process;

FIG8 is a schematic diagram of a method for dynamically adjusting a preset output voltage of an integrator applied to the present invention;

FIG9 is a schematic diagram of a switched capacitor integrator based on an amplifier and a comparator applied to the present invention;

FIG10 is a timing diagram of the integrator in FIG9 during a fine conversion process;

FIG11 is a schematic diagram of another switched capacitor integrator based on an amplifier and a comparator applied to the present invention;

FIG. 12 is a timing diagram of the integrator in FIG. 11 during a fine conversion process.

Detailed ways

The present invention provides a self-timed asynchronous scaling incremental ADC solution that does not require an external clock signal. An example of the solution according to the present invention can be seen in Figures 1 and 2, which includes a two-stage conversion process, which is implemented by a coarse converter and a fine converter respectively.

The coarse converter Con-c is an M bit SAR ADC, which is used to determine the approximate range of the input voltage Vin to be converted. It operates in a successive approximation manner, starting from the most significant bit MSB (Most Significant Bit), controlling the digital-to-analog converter DAC (Digital-to-Analog Converter) to output the predicted voltage value corresponding to the current bit, and compares it with Vin (direct comparison, or quantization of the differential result, etc.), determines the data of the current bit according to the comparison result, and continues to judge the data of the next bit until the M-bit comparison is completed, and determines the result m of the coarse conversion. The result of the SAR ADC can lock Vin in the range of a least significant bit LSB (Least Significant Bit) of Vref, where Vref is the predicted voltage value corresponding to m. That is, from the result m of the coarse conversion, it can be determined that Vin falls within the interval of an LSB of Vref: m*VLSB < Vin < (m+1)*VLSB, where VLSB is the precision step of the coarse conversion.

The fine converter Con-f uses an oversampling noise-rectified ΔΣ ADC. The differential value between Vin and the reference voltage is integrated and quantized for multiple cycles in an oversampling manner within the preset reference voltage range. The output bit sequence bs (bit stream) can be further filtered by a decimation filter DF (Decimation Filter) to obtain valid data. After merging with the result of the coarse conversion, the final output conversion result Dout is obtained.

The existing scaling ADCs all use the traditional ΔΣADC with a fixed oversampling clock frequency for fine conversion. The fine converter in the present invention uses a self-timed ΔΣ ADC, specifically a second-order incremental ΔΣ ADC including two integrators connected in series. The outputs of the two integrators are quantized by a comparator after being combined, and the corresponding bit sequence bs is output. Each integrator includes a zero-crossing detection circuit ZCBC. Each integrator determines the completion of an integration cycle by detecting whether the virtual ground voltage at the input end of the integrator reaches the circuit signal zero point (i.e., the common mode voltage Vcm). Through the zero-crossing judgment of the two integrators alternately, a transitive, asynchronous conversion sequence can be realized. The overall self-timed timing control can be performed by a state machine running in the digital domain. After starting execution, the state machine first runs the control logic SAR-Log of the coarse conversion stage, and controls the coarse converter Con-c to run N1 cycles in a self-timed manner. After the coarse conversion is completed, the control logic ΔΣ-Log of the fine conversion stage continues to run, and controls the fine converter Con-f to run N2 cycles in a self-timed manner, thereby completing the entire conversion process. Specifically, the first control signal φ1 and the second control signal φ2 can be set, the state A of the state machine corresponds to φ1 being valid, controlling the first integrator to start sampling and the second integrator to start integration, the state B of the state machine corresponds to φ2 being valid, controlling the first integrator to start integration and the second integrator to start sampling, and when the integration process of each integrator is completed (i.e., when a zero-crossing signal is detected), the corresponding state is completed, triggering the switching of φ1 being valid and φ2 being valid. In this way, the two integrators push each other, so that φ1 and φ2 become self-timing control signals.

As a preferred embodiment, the result value m of the coarse conversion can be stored in the SAR register SAR-r, which is used to reconfigure the DAC to output Vref as a reference voltage for fine conversion. This allows the DAC to be reused in both the coarse conversion and the fine conversion process by reconfiguration, thereby saving chip area.

As a preferred implementation, the same comparator can be used for quantization (comparison) in coarse conversion and fine conversion, as shown in FIG2 , to further save chip area. In this case, the output of the fine conversion circuit can be bypassed using the bypass control signal SAR_EN during the coarse conversion stage, so that the differential result of the coarse conversion is directly input to the input terminal of the comparator for quantization.

Referring to FIG3 , it is an overall design diagram of a scaling incremental ADC according to an example of the present invention. It consists of a SAR ADC (coarse converter) with M=5 and a second-order incremental ΔΣ ADC (fine converter). The reference voltage of the DAC output is configured by the switch signals S0-6p and S0-6n output by the register SAR-r, where VREFP and VREFN are the positive and negative reference voltage sources, respectively. In the fine converter, a switched-capacitor adder SCA (Switched-Capacitor Adder) is used to combine the outputs of the two integrators to form a feedforward path around the second integrator. In FIG3 , in order to facilitate better reuse of the coarse/fine converter circuit, the first integrator of the fine converter is also used to store the difference between the predicted voltage value and Vin during the coarse conversion process, while the second integrator will not be used during the coarse conversion process. Therefore, during the coarse conversion process, the second integrator is bypassed by the bypass control signal SAR_EN. The "Log" shown in the figure is a logic circuit for switch control according to the comparison result.

Generally, the operation cycle N1 of the coarse conversion is determined by its precision bit M, but N1 can also be greater than M. For example, in Figure 3, a capacitor of size C/2 is also added to the DAC, which allows the coarse conversion process to be executed for an additional cycle after the judgment to the lowest bit LSB. In this cycle, the predicted voltage value is set to (m+0.5)*VLSB, where VLSB is the precision step of the coarse conversion, thereby determining whether to select the range of m-1 to m+1 or m to m+2 in the subsequent fine conversion. This additional judgment cycle adds a redundant range of LSB to the fine conversion, making the system have better fault tolerance. The operation cycle (i.e., oversampling cycle) N2 of the fine conversion can be determined according to the conversion accuracy requirements for Vin.

The flow chart of the conversion method according to the present invention can refer to FIG4. For ease of understanding, the conversion method will be described below with reference to the exemplary design diagram of FIG3. During the entire conversion process, the timing steps of the entire ADC are uniformly controlled by the state machine to ensure the completion of each current conversion step and promote the next step. The method includes:

Step S100, obtaining a start signal to start a new round of conversion process. This signal can be provided by a preset threshold, for example, it can be determined whether a state change of a certain state change of the measured physical quantity causes the state change of the sensor to exceed the threshold, if so, triggering the start signal, otherwise keep waiting.

Step S200, starting the state machine according to the start signal and starting the coarse conversion process.

The state machine controls the coarse converter to run N1 cycles in a self-timed manner. In each cycle of the coarse conversion, the input voltage Vin to be converted is sampled through φ1 control, and the predicted voltage value corresponding to the current bit is generated through φ2 control. The difference Vx1 between the predicted voltage value and Vin is quantized through a comparator, and the data bi,i∈[1,M] of the current bit is determined according to the quantization result.

In the example shown in FIG3 , the delayed signals φ1d and φ2d of φ1 and φ2 are further used for control. The delay is only to ensure that when the switch is turned off, the switches controlled by φ1d and φ2d are not turned off at the same time as the switches controlled by φ1 and φ2, thereby reducing channel charge injection. This is a conventional operation of the switched capacitor circuit. In terms of control logic, φ1d can be considered to be equivalent to φ1, and φ2d to be equivalent to φ2.

φ2_st is further used for control. φ2_st is a control signal extended from φ2, which is the part of the φ2 cycle after the preset is completed. At the beginning of the φ2 cycle, the preset is first performed (the integrator output voltage is pulled up to ensure that the integrator input is above the signal zero point Vcm of the circuit), and then the actual charge transfer begins, so the meaning of "st" here is "start transfer".

Step S300, determining that all cycles of the coarse conversion are completed, and setting the predicted voltage value Vref corresponding to the coarse conversion result m as a reference voltage for fine conversion.

Step S400, starting the fine conversion process of Vin.

The state machine controls the fine converter in a self-timing manner to run N2 cycles in an oversampling noise shaping manner. In each cycle of the fine conversion, two integrators are alternately controlled by φ1 and φ2 to perform sampling and integration, and the outputs of the two integrators are quantized by a comparator after being combined to output a corresponding bit sequence. Specifically, at the beginning of each cycle of the fine conversion, φ1 is set to be valid to put the first integrator in a sampling state and start the integration process of the second integrator. When the integration of the second integrator is completed, φ1 is set to be invalid and switched to φ2 valid to start the integration process of the first integrator and put the second integrator in a sampling state. When the integration of the first integrator is completed, the comparator is triggered to perform comparison, φ2 is set to be invalid and switched to φ1 valid to start the execution of the next cycle.

Step S500, after the fine conversion is completed, the data result is output, the conversion process of the entire zoom ADC is completed, and the next conversion is ready to start. It should be understood that since it is an incremental ADC, the integrator needs to be reset each time a new conversion starts.

FIG5 exemplarily shows a timing diagram of a round of conversion process of the above conversion method. All control signals listed in the figure are high level valid. As shown in the figure, except for the initial start signal START, all timing signals, including the reset signal RST, the bypass control signal SAR_EN, the coarse conversion completion signal C_Done, the fine conversion completion signal F_Done, φ1, φ2, etc., are generated by handshake transmission. Therefore, the whole system realizes a completely self-timing measurement.

The self-timed integrator used in the fine converter of the present invention can be implemented in a variety of ways. For example, referring to FIG6 , as an optional implementation, a comparator-based switched-capacitor integrator CBSC (Comparator-Based Switched-Capacitor) is provided. It includes an inverter with autozeroing, which is used as a threshold comparator. In the charge transfer cycle (i.e., the integration process), the integrator uses two unidirectional current sources E1 and E2 of different sizes to charge the integration capacitor (see C _I1 and C _I2 in FIG3 , which are not shown in FIG6 for simplicity). Due to the use of a unidirectional current source structure, in order to ensure that the initial state of the circuit is correct, the output voltage Vo is first preset to a higher voltage Vpx, and then the capacitor is first charged by the larger current source E1, and then the capacitor is charged by the smaller current source E2 after early-threshold detection. The timing diagram of the integrator in FIG6 during the fine conversion process can be referred to FIG7 . The symbols in FIG6 and FIG7 are explained as follows:

φAZ: Auto-zero cycle, during which the offset voltage of the inverter is stored on Cc so that this offset does not affect the accuracy of charge transfer in the subsequent charge transfer cycle (integration process);

Cbwl: bandwidth-limited capacitor, used to limit the bandwidth of the first inverter (also known as the pre-amp inverter), which helps reduce noise;

D: decision result;

DE: early threshold decision result;

Ccls: Correlated Level Shifting capacitor, which is charged and discharged through this capacitor instead of directly discharging the output voltage of the integrator, so that the output voltage of the integrator will not directly modulate the current source, which helps to improve linearity;

P: preset period, used for preset before charge transfer (pull up the integrator output voltage to ensure that the integrator input terminal Vx is above the signal zero point Vcm of the circuit);

Vbc: bias voltage of coarse current source, “bc” means “bias coarse”;

Vbf1: the first bias voltage of the fine current source, “bf1” means “bias fine 1”;

Vbf2: The second bias voltage required for the fine current source (cascode bias used to increase the output impedance of the current source). “bf2” means “bias fine 2”.

In some embodiments, Vpx may be fixed, for example, preset to the system power supply voltage VDD. However, since this preset process is an additional charging process, unnecessary energy consumption is actually generated. According to analysis, as long as Vpx is equal to the maximum positive swing voltage of the integrator, the correct state of the circuit can be guaranteed. Therefore, as a preferred embodiment, a dynamically adjustable Vpx can be used instead of the fixed VDD, and a suitable Vpx value can be selected by judging the output swing of the integrator, such as the density estimator shown in FIG3, so that the virtual ground voltage Vx of the integrator needs to be preset to above the signal zero point Vcm of the circuit, while minimizing the additional power consumption caused by the preset. Referring to FIG8, a schematic diagram of the density estimator dynamically adjusting the preset output voltage Vpx of the integrator is shown. First, the output swing of the integrator is determined by judging the density μ (i.e., the number of 1s in bs) of the first X bits of the bit sequence bs that have been output during the fine conversion process. Obviously, the range of μ is 0<μ<1. When μ≈0.5, it means that the feedback of the circuit alternates between the positive and negative reference voltages. At this time, the output swing of the integrator should be the smallest; and when μ is close to 0 or 1, the output swing of the integrator should be the largest. Therefore, Vpx can be dynamically adjusted according to |μ-0.5|. The smaller the absolute value, the smaller Vpx. For example, a set of 4 preset values Vp1< Vp2< Vp3< Vp4 can be set. According to the change of μ, an appropriate preset value is selected, so that the adjusted Vpx is used in the subsequent conversion process. In this process, 1 is accumulated to obtain the value a, the bit sequence is accumulated to obtain the value b, and subsequent calculations and selections can be performed in the digital domain.

Referring to FIG9 , as another optional implementation, there is an amplifier and comparator-based switched-capacitor integrator ACBSC (Amplifier and Comparator-Based Switched-Capacitor). It includes two inverters with automatic zero adjustment, one used as a threshold comparator and the other used as an amplifier. Compared with the CBSC in FIG6 , the ACBSC uses a negative feedback amplifier to assist discharge, so a coarse current source as in FIG6 is no longer required, but only a fine current source is required to produce a zero-crossing detection effect to achieve the requirement of self-timing operation. During the integration process, the output of the threshold comparator controls the amplifier and the fine current source to charge the integration capacitor _CI .

The timing diagram of the integrator in the fine conversion process in Figure 9 can be referred to Figure 10. It can be seen that because a negative feedback amplifier is used to replace the coarse current source, the discharge mode is first exponential discharge (mainly the amplifier), and as the voltage gradually approaches the common mode voltage, the dynamic current of the amplifier gradually decreases. When the voltage is close to the common mode voltage, the discharge mainly relies on the fine current source, and gradually tends to linear discharge. The advantages of ACBSC are: (1) The exponential discharge efficiency is higher, the discharge is completed faster, and it is easier to improve the overall energy efficiency of the system. (2) Because the dynamic current of the inverter as an amplifier is the largest when the input voltage is VDD or ground voltage (GND), and it will gradually decrease as the input voltage approaches the common mode voltage Vcm, although the early threshold detection function is still included in Figure 8, in fact, the early threshold detection can be ignored because the dynamic current generated by the amplifier will naturally decrease as the charging and discharging process proceeds. In other words, this dynamic "coarse current source" will "turn off" itself. Referring to FIG11, an ACBSC with omitted early threshold detection is shown, in which the threshold comparator only generates a decision result D output to control the fine current source to charge the integration capacitor C _I. The timing diagram of the integrator in FIG11 during the fine conversion process can be referred to FIG12. (3) If the comparator part is turned off, the ACBSC becomes a traditional integrator relying on an external clock. Therefore, the ADC constructed with this type of integrator can be easily switched between self-timing and external clock modes, providing the system with the possibility of selection according to the application.

The above specific examples are used to illustrate the principles and implementation methods of the present invention. It should be understood that the above implementation methods are only used to help understand the present invention and should not be construed as limiting the present invention. For those skilled in the art, the above specific implementation methods can be changed according to the idea of the present invention.

Claims (10)

1. An analog-to-digital conversion method using a scaled delta analog-to-digital converter ADC comprising a coarse converter and a fine converter, characterized in that,

The coarse converter is a successive approximation ADC and the fine converter is a second order delta ADC comprising a first integrator and a second integrator in series, each integrator comprising a zero crossing detection circuit ZCBC;

the scaling type incremental ADC is provided with a first control signal phi 1 and a second control signal phi 2, wherein the first integrator is controlled to start sampling and the second integrator is controlled to start integrating when phi 1 is effective, the first integrator is controlled to start integrating and the second integrator is controlled to start sampling when phi 2 is effective, zero crossing signals are generated when the integration process of each integrator is finished, and the zero crossing signals are used for controlling the effective switching of phi 1 and the effective switching of phi 2, and the two integrators push each other to enable phi 1 and phi 2 to be self-timing control signals;

The method comprises the steps of:

Acquiring a starting signal;

starting a coarse conversion process executed by the coarse converter according to the starting signal, wherein the coarse conversion adopts a successive approximation mode, starts from the MSB of the highest bit, runs for N1 periods, wherein N1 is an integer greater than or equal to the number of precision bits of the coarse conversion, samples an input voltage Vin to be converted in each period of the coarse conversion through phi 1 control, generates a predicted voltage value corresponding to the current bit through phi 2 control, quantizes a difference value between the predicted voltage value and Vin through a comparator, and determines data of the current bit according to a quantization result;

After the whole period execution of the coarse conversion is completed, taking a predicted voltage value Vref corresponding to a result m of the coarse conversion as a reference voltage for the fine conversion, starting a fine conversion process executed by the fine converter, wherein the fine conversion is operated for N2 periods in an oversampling noise shaping mode, N2 is an integer determined according to the conversion precision requirement of Vin, in each period of the fine conversion, sampling and integration are alternately controlled through phi 1 and phi 2, and the output of the two integrators is quantized through a comparator after being combined, and a corresponding bit sequence is output.

2. The method of claim 1, wherein the step of determining the position of the substrate comprises,

N1 is set to the number of precision bits of the coarse conversion plus 1, and the coarse conversion process is further increased to perform a period in which the predicted voltage value is set to (m+0.5) ×vlsb, which is a precision step of the coarse conversion, after judging to the least significant bit LSB, thereby determining whether to select m-1 to m+1 or m to m+2 in the fine conversion.

3. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The same digital-to-analog converter DAC is used to provide the predicted voltage value in the coarse conversion and Vref in the fine conversion,

Quantization in the coarse and fine conversions is performed using the same comparator,

The coarse conversion uses the first integrator in the fine conversion to store the difference of the predicted voltage value from Vin,

The scaled delta ADC is provided with a bypass control signal SAR EN which, when active, bypasses the second integrator from the input of the comparator,

The method further includes, upon starting the coarse transformation process, setting sar_en to active until the coarse transformation is complete.

4. A method according to any one of claims 1 to 3, further comprising

In the fine conversion process, the density μ of the outputted bit sequence is determined, the preset voltage Vpx at the output end of ZCBC is dynamically adjusted according to |μ -0.5|, the smaller the absolute value is, the smaller the Vpx is, and the Vpx is used for meeting the requirement that the virtual ground voltage Vx of the corresponding integrator is preset to be above the common mode voltage Vcm of the circuit.

5. A scaled delta analog-to-digital converter, comprising:

a coarse converter employing a successive approximation ADC for performing a coarse conversion process;

a fine converter employing a second order delta sigma ADC for performing a fine conversion process comprising a first integrator and a second integrator in series, each integrator comprising a zero crossing detection circuit ZCBC;

the state control module is used for setting a first control signal phi 1 and a second control signal phi 2, wherein the first integrator is controlled to start sampling and the second integrator is controlled to start integrating when phi 1 is valid, the first integrator is controlled to start integrating and the second integrator is controlled to start sampling when phi 2 is valid, zero crossing signals are generated when the integration process of each integrator is completed, and the zero crossing signals are used for controlling the effective switching of phi 1 and the effective switching of phi 2, and the two integrators are pushed by each other so that phi 1 and phi 2 become self-timing control signals;

And is used to obtain the start signal,

Starting the coarse conversion process according to the start signal, starting the coarse conversion from the most significant MSB by adopting a successive approximation mode, running for N1 periods, wherein N1 is an integer greater than or equal to the precision bit number of the coarse conversion, sampling the input voltage Vin to be converted by phi 1 control in each period of the coarse conversion, generating a predicted voltage value corresponding to the current bit by phi 2 control, quantizing the difference value between the predicted voltage value and Vin by a comparator, determining the data of the current bit according to the quantized result,

After the whole period execution of the coarse conversion is completed, taking a predicted voltage value Vref corresponding to a result m of the coarse conversion as a reference voltage for the fine conversion, starting the fine conversion process, operating N2 periods by adopting an oversampling noise shaping mode in the fine conversion, wherein N2 is an integer determined according to the conversion precision requirement of Vin, alternately controlling two integrators to sample and integrate through phi 1 and phi 2 in each period of the fine conversion, and quantizing the outputs of the two integrators through a comparator after combining to output a corresponding bit sequence.

6. The scaled delta analog-to-digital converter of claim 5, wherein,

The coarse converter and the fine converter use the same digital-to-analog converter DAC for providing a predicted voltage value in the coarse conversion and Vref in the fine conversion,

The coarse converter and the fine converter use the same comparator for quantization in the coarse conversion and the fine conversion,

The coarse converter further comprises a first integrator in the fine converter for storing a difference between a predicted voltage value and Vin;

The state control module is further configured to set a bypass control signal sar_en, and when the coarse conversion process is started, set sar_en to be valid until the coarse conversion is completed, and when the sar_en is valid, control to bypass the second integrator from the input end of the comparator.

7. The scaled delta analog-to-digital converter of claim 6, wherein,

The DAC further comprises an output circuit for providing 0.5 x VLSB, wherein VLSB is the precision step size of the coarse conversion;

the state control module is further configured to, during the coarse transition, after determining to the least significant LSB, add to execute a period in which the predicted voltage value is set to (m+0.5) VLSB, thereby determining whether to select a range of m-1 to m+1 or m to m+2 in the fine transition.

8. The scaled incremental analog-to-digital converter of any one of claims 5-7 wherein,

The state control module is further configured to determine, during the fine transition, a density μ of the outputted bit sequence, dynamically adjust, according to |μ -0.5|, an output preset voltage Vpx of ZCBC, where the smaller the absolute value is, the smaller Vpx is, and Vpx is used to satisfy that a virtual ground voltage Vx of a corresponding integrator is preset above a common mode voltage Vcm of the circuit.

9. The scaled delta analog-to-digital converter of claim 5, wherein,

At least one of the two integrators adopts a switched capacitor integrator ACBSC based on an amplifier and a comparator, and comprises two inverters with auto-zero, one is used as a threshold comparator, the other is used as an amplifier, the amplifier adopts negative feedback type, the dynamic current of the amplifier is reduced along with the progress of charge and discharge,

In the integration process, the threshold comparator generates two paths of output of a judgment result and an early threshold judgment result, and the amplifier and a thin current source are respectively controlled to charge a capacitor for integration; or the threshold comparator generates one path of judgment result to output, and controls a thin current source to charge a capacitor for integration.

10. The scaled delta analog-to-digital converter of claim 5, wherein,

At least one of the two integrators employs a comparator-based switched capacitor integrator CBSC, comprising an inverter with auto-zero, acting as a threshold comparator,

The threshold comparator generates two paths of output of a judgment result and an early threshold judgment result, controls a coarse current source and a fine current source to charge a capacitor for integration respectively, charges the capacitor by the coarse current source firstly, and charges the capacitor by the fine current source after the early threshold judgment result is effective.