CN114285414B - Scaling type increment type analog-to-digital conversion method and converter - Google Patents
Scaling type increment type analog-to-digital conversion method and converter Download PDFInfo
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Abstract
An analog-to-digital conversion method and a scaled delta analog-to-digital converter, wherein the scaled delta analog-to-digital converter ADC comprises a successive approximation type ADC used as a coarse converter and a second order delta ADC used as a fine converter, which comprises two integrators connected in series, wherein each integrator comprises a zero crossing detection circuit. In the method, two control signals phi 1 and phi 2 are set to alternately control sampling and integration of the two integrators, and the effective switching of phi 1 and phi 2 is controlled according to zero crossing signals generated when the integration process of each integrator is completed, so that the phi 1 and phi 2 become self-timing control signals through mutual pushing of the two integrators, and the self-timing execution of the coarse conversion process and the fine conversion process is controlled through integral time sequence design.
Description
Technical Field
The invention relates to the technical field of Analog-to-Digital Converter (ADC), in particular to a scaling incremental Analog-to-digital conversion method and a scaling incremental Analog-to-digital converter (Zoom INCREMENTAL ADC).
Background
With the development of electronic information technology, sensors are increasingly widely used. The sensor is a device for converting physical signals in reality, such as temperature, humidity, gas concentration, various biological signals, etc., into electrical signals, so that the physical signals containing important information can be accurately and rapidly measured by means of the strong capability of electrical signal processing. Currently, wearable or portable sensor systems are playing an increasingly important role for health, medical and environmental monitoring purposes, etc. Due to the requirements of portable applications, the sensor systems are required to have the characteristics of low power consumption, small volume, low cost, simple circuit structure and the like.
The core of the sensor system is typically an ADC which functions to convert the time and amplitude continuous electrical signal output by the sensor into a digital signal so that the digital signal can be processed, stored and transmitted later on in a convenient and reliable manner. Successive approximation ADC (SAR ADC, successive Approximation REGISTER ADC) based on binary search and oversampled noise-in-full form (Oversampling and Noise Shaping) ΔΣ ADC are two main types.
The SAR ADC can achieve a faster conversion speed, so that the SAR ADC has higher energy efficiency and meets the requirement of low power consumption. However, limited by the mismatch of the components, some additional technical measures are often required in order to achieve a high measurement accuracy (e.g. >12 bit), which leads to a high power consumption or cost.
Oversampling noise-full-form delta-sigma ADCs can achieve higher resolution and accuracy, but because of the oversampling technique used, lower-order delta-sigma ADCs typically require longer conversion times, while higher-order delta-sigma ADCs tend to have limited dynamic range of the input signal and higher complexity of the circuit in order to meet stability requirements.
In practical applications, the bandwidth requirements of sensor systems for environmental parameter or bio-signal measurements are typically not high, e.g. typically low frequency or near dc, but need to meet the requirements of high accuracy, high linearity and low power consumption, so that usually an oversampled noise-integrated delta-sigma ADC is used. In such systems, the ADC often operates with a low duty cycle, i.e., clears (Reset) each time operation is initiated, and shuts down after a transition is completed until triggered by the next signal to reduce unnecessary static power consumption. This type of ADC is called an incremental ADC.
One solution that has emerged in recent years is a hybrid ADC that combines these two types of converters, namely a scaled (Zoom) delta ADC. Referring to "Y. Chae, K. Souri, and K. A. A. Makinwa, "A 6.3 μW 20 bit incremental zoom-ADC with 6 ppm INL and 1 μV offset," IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3019–3027, Dec. 2013.". the conversion process of the scaled ADC is split into two steps, first a coarse conversion (coarse conversion) is performed with the SAR ADC to quickly determine the approximate range of the signal. A fine conversion (fine conversion) is then performed on the scaled down range with a delta-sigma ADC to complete an accurate measurement of the signal.
The scaled delta ADC combines the high efficiency of SAR ADC with the high accuracy of ΔΣ ADC, which is a more ideal solution for low power consumption sensors. But a potential problem is that the design of the sequential circuit is complex. To avoid the need for high-speed clocks and to increase conversion efficiency, SAR ADCs are typically implemented in an Asynchronous (asynchroous) manner. While delta-sigma ADCs for fine conversion still require an external high-speed clock signal to achieve oversampling, this results in increased system complexity and increased power consumption and cost. Although there are also delta-sigma ADCs that are studied for Self-timing (Self-Timed), see "C. Chen, Z. Tan and M. A. P. Pertijs, "A 1V 14b self-timed zero-crossing-based incremental ΔΣ ADC," 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, pp. 274-275, doi: 10.1109/ISSCC.2013.6487732.",, there is no overall design to integrate a local asynchronous and a local synchronous subsystem.
Disclosure of Invention
According to an aspect of the present invention, there is provided an analog-to-digital conversion method using a scaled delta ADC comprising a coarse converter and a fine converter, wherein,
The coarse converter is a successive approximation ADC and the fine converter is a second order delta ADC comprising a first integrator and a second integrator in series, each integrator comprising a Zero-crossing detection circuit ZCBC (Zero-Crossing-Based Circuits);
The scaling incremental ADC is provided with a first control signal phi 1 and a second control signal phi 2, wherein the first integrator is controlled to start sampling and the second integrator is controlled to start integrating when phi 1 is effective, the first integrator is controlled to start integrating and the second integrator is controlled to start sampling when phi 2 is effective, zero crossing signals are generated when the integration process of each integrator is finished, and the zero crossing signals are used for controlling the effective switching of phi 1 and the effective switching of phi 2, and the two integrators push each other to enable phi 1 and phi 2 to be self-timing control signals;
the method comprises the following steps:
Acquiring a starting signal; starting a coarse conversion process executed by a coarse converter according to a start signal, starting from the MSB of the highest bit by adopting a successive approximation mode, running for N1 periods, wherein N1 is an integer greater than or equal to the number of precision bits of the coarse conversion, sampling an input voltage Vin to be converted through phi 1 control in each period of the coarse conversion, generating a predicted voltage value corresponding to the current bit through phi 2 control, quantizing a difference value between the predicted voltage value and Vin through a comparator, and determining the data of the current bit according to a quantized result;
After the whole period execution of the coarse conversion is completed, taking a predicted voltage value Vref corresponding to a coarse conversion result m as a reference voltage for the fine conversion, starting a fine conversion process executed by a fine converter, operating N2 periods in an oversampling noise shaping mode, wherein N2 is an integer determined according to the conversion precision requirement of Vin, alternately controlling two integrators to sample and integrate through phi 1 and phi 2 in each period of the fine conversion, and quantizing the outputs of the two integrators through a comparator after combining to output a corresponding bit sequence.
According to another aspect of the invention there is provided a scaled-delta ADC comprising:
a coarse converter employing a successive approximation ADC for performing a coarse conversion process;
a fine converter employing a second order delta sigma ADC for performing a fine conversion process comprising a first integrator and a second integrator in series, each integrator comprising ZCBC;
the state control module is used for controlling to execute the analog-to-digital conversion method.
According to the solution of the scaling type incremental ADC, the self-timing control is carried out on the whole time sequence through the integral unified self-timing design, and the time sequence control requirements in two stages of coarse conversion and fine conversion are coordinated, so that the external clock requirement in the traditional scaling type incremental ADC is eliminated, the problem of complex time sequence circuit design of the scaling type incremental ADC and the additional cost and power consumption problems are solved. The difficulty of system integration of the scaling type incremental ADC in practical application is greatly reduced, and the robustness and reliability of the type ADC are improved.
Specific examples according to the present invention will be described in detail below with reference to the accompanying drawings. The words of order, such as "first," "second," and the like, as used herein are merely used for identifying purposes and are not to be taken in an absolute sense.
Drawings
FIG. 1 is a schematic diagram of a scaled-delta ADC according to the present invention;
FIG. 2 is a system block diagram of a scaled-delta ADC according to the present invention;
FIG. 3 is an overall design of a scaled-delta ADC according to one example of the invention;
FIG. 4 is a flow chart of a scaled incremental analog-to-digital conversion method according to the present invention;
FIG. 5 is a timing diagram of a set of switching processes of a switching method according to an example of the present invention;
FIG. 6 is a schematic diagram of a comparator-based switched capacitor integrator for use in the present invention;
FIG. 7 is a timing diagram of the integrator of FIG. 6 during a fine transition;
FIG. 8 is a schematic diagram of a dynamic adjustment of the preset output voltage of an integrator applied to the present invention;
FIG. 9 is a schematic diagram of a switched capacitor integrator based amplifier and comparator for use with the present invention;
FIG. 10 is a timing diagram of the integrator of FIG. 9 during a fine transition;
FIG. 11 is a schematic diagram of another switched capacitor integrator based amplifier and comparator applied to the present invention;
fig. 12 is a timing diagram of the integrator of fig. 11 during fine transitions.
Detailed Description
The present invention provides a self-timed asynchronous scaling delta ADC solution that does not require an external clock signal. An example of a solution according to the invention can be seen with reference to fig. 1 and 2, comprising a two-stage conversion process implemented by a coarse converter and a fine converter, respectively.
The coarse converter Con-c is an M-bit SAR ADC for determining the approximate range of the input voltage Vin to be converted. The method is operated in a successive approximation mode, and starts from the highest bit MSB (Most Significant Bit), a Digital-to-Analog Converter (DAC) is controlled to output a predicted voltage value corresponding to the current bit, the predicted voltage value is compared with Vin (direct comparison or differential result quantization and the like), the data of the current bit is determined according to the comparison result, the data of the next bit is continuously judged until the comparison of M bits is completed, and a coarse conversion result M is determined. The result of the SAR ADC can lock Vin to the range of one of the lowest Bit LSBs (LEAST SIGNIFICANT Bit) of Vref, where Vref is the predicted voltage value corresponding to m. That is, it can be determined from the result m of the rough conversion that Vin falls within the interval of one LSB of Vref: VLSB < Vin < (m+1) < VLSB, where VLSB is the precision step of coarse conversion.
The fine converter Con-f takes the oversampled noise-integrated form ΔΣ ADC. And integrating and quantifying the difference value of Vin and the reference voltage for a plurality of periods in an oversampling mode in a preset reference voltage range. The output bit sequence bs (bit stream) may be further noise filtered using a decimation filter DF (Decimation Filter) to obtain valid data. After being combined with the result of the coarse conversion, the conversion result Dout of the final output is obtained.
Currently available scaling ADCs employ conventional delta-sigma ADCs with fixed oversampling clock frequencies during fine conversion. The fine converter of the present invention adopts a self-timing delta-sigma ADC, specifically a second-order delta-sigma ADC comprising two integrators connected in series, the outputs of the two integrators are quantized by a comparator after being combined, and the corresponding bit sequence bs is output. Each integrator includes a zero crossing detection circuit ZCBC. Each integrator determines the completion of an integration period by detecting whether the virtual ground voltage at the integrator input has reached the circuit signal zero (i.e., the common mode voltage Vcm). A transitive, asynchronous switching sequence can be realized by the alternating zero crossing decisions of the two integrators. The whole self-timing time sequence control can be carried out through a state machine running in a digital domain, after the start-up execution, the state machine firstly runs a control logic SAR-Log of a coarse conversion stage, controls a coarse converter Con-c to run for N1 periods in a self-timing mode, and after the coarse conversion is finished, continues to run a control logic delta sigma-Log of a fine conversion stage, and controls a fine converter Con-f to run for N2 periods in a self-timing mode, so that the whole conversion process is finished. Specifically, a first control signal Φ1 and a second control signal Φ2 may be set, state a of the state machine corresponds to Φ1 being active, state B of the state machine corresponds to Φ2 being active, state a of the state machine controlling the first integrator to begin sampling and the second integrator to begin sampling, and when each integrator integration process is completed (i.e., when a zero crossing signal is detected), the corresponding state is completed, triggering a switch between Φ1 being active and Φ2 being active. In this way, phi 1 and phi 2 are made self-timed control signals by pushing each other through the two integrators.
As a preferred embodiment, the resulting value m of the coarse conversion may be stored in SAR register SAR-r for reconfiguring the DAC to output Vref as a reference voltage for the fine conversion. This allows the DAC to be re-used in both the coarse and fine conversion processes by reconfiguration, thus saving chip area.
As a preferred embodiment, the same comparator may be used for quantization (comparison) in both coarse and fine conversion, as shown in fig. 2, to further save chip area. In this case, the output of the fine conversion circuit may be bypassed using the bypass control signal sar_en in the coarse conversion stage, so that the differential result of the coarse conversion is directly input to the input of the comparator for quantization.
Referring to fig. 3, an overall design of a scaled-delta ADC in accordance with one example of the invention is shown. It consists of one SAR ADC (coarse converter) with m=5 and one second order delta-sigma ADC (fine converter). The reference voltages output by the DAC are configured by the switching signals S0-6p and S0-6n output by the registers SAR-r, where VREFP and VREFN are positive and negative reference voltage sources, respectively. In a fine converter, the outputs of the two integrators are combined using a Switched capacitor adder SCA (Switched-Capacitor Adder) to form a feed forward path around the second integrator. In fig. 3, to facilitate better multiplexing of the coarse/fine converter circuits, the first integrator of the fine converter is also used to store the difference between the predicted voltage value and Vin during coarse conversion, while the second integrator is not used during coarse conversion. Thus during the coarse conversion the second integrator is bypassed by the bypass control signal sar_en. "Log" shown in the figure is a logic circuit for performing switching control based on the comparison result.
Typically, the run-time N1 of the coarse transformation is determined by its number of precision bits M, but N1 may also be greater than M. For example, in fig. 3, a capacitor of C/2 is further added to the DAC, which makes it possible to further increase the coarse conversion process to perform a period after determining the least significant LSB, in which the predicted voltage value is set to (m+0.5) VLSB, which is the precision step of the coarse conversion, to thereby determine whether to select the range of m-1 to m+1 or m to m+2 in the subsequent fine conversion. This increased decision period increases the redundancy range of one LSB for fine transitions, allowing for better fault tolerance of the system. The running period (i.e., the oversampling period) N2 of the fine conversion can be determined according to the conversion accuracy requirement for Vin.
A flowchart of the conversion method according to the present invention may refer to fig. 4, and for convenience of understanding, the following description will be made with reference to the exemplary design diagram of fig. 3 when describing the conversion method. In the whole conversion process, the time sequence steps of the whole ADC are uniformly controlled by a state machine so as to ensure the completion of each current conversion step and push the next step. The method comprises the following steps:
step S100, a start signal is acquired to start a new conversion process. This signal may be provided by a predetermined threshold value, for example, it may be determined whether a certain state change of the measured physical quantity causes a state change of the sensor exceeding the threshold value, if so, the start signal is triggered, and if not, waiting is maintained.
Step S200, the state machine is started according to the starting signal, and the rough conversion process is started.
The state machine controls the coarse converter to run for N1 cycles in a self-timed manner. In each period of the coarse conversion, the input voltage Vin to be converted is sampled through phi 1 control, a predicted voltage value corresponding to the current bit is generated through phi 2 control, a difference value Vx1 between the predicted voltage value and Vin is quantized through a comparator, and the data bi, i epsilon [1, M ] of the current bit is determined according to the quantization result.
In the example shown in fig. 3, the delay signals Φ1d and Φ2d of Φ1 and Φ2 are further employed for control. This delay is only to satisfy that when the switch is off, the switches controlled by φ 1d and φ 2d are not turned off at the same time as the switches controlled by φ 1 and φ 2, thereby reducing channel charge Injection (CHANNEL CHARGE Injection). This is the normal operation of the switched capacitor circuit, and in terms of control logic, can be considered to be equivalent to φ1d and φ1d, and equivalent to φ2d and φ2d.
Phi 2_ st is further used for control. Phi 2_st is the part of the phi 2 period after the preset is completed based on the control signal from phi 2. At the beginning of the period phi 2, a preset is first made (pulling the integrator output voltage high, ensuring that the integrator input is above the signal zero Vcm of the circuit), after which the actual charge transfer starts, so that here "st" means "start transfer (START TRANSFER)".
Step S300, it is determined that the execution of all cycles of the coarse conversion is completed, and the predicted voltage value Vref corresponding to the coarse conversion result m is set as the reference voltage for the fine conversion.
Step S400, the fine transition procedure to Vin is started.
The state machine controls the fine converter to operate for N2 cycles in a self-timed manner using oversampling noise shaping. In each period of the fine conversion, the two integrators are alternately controlled to sample and integrate by phi 1 and phi 2, and the outputs of the two integrators are quantized by a comparator after being combined, and the corresponding bit sequence is output. Specifically, at the beginning of each cycle of the fine transition, φ 1 is asserted to place the first integrator in the sampling state and to initiate the integration process of the second integrator, and when the integration of the second integrator is complete, φ 1 is asserted and switched to be asserted to initiate the integration process of the first integrator and to place the second integrator in the sampling state. When the first integrator integration is complete, the comparator is triggered to perform a comparison, setting φ 2 inactive and switching φ 1 active to initiate execution of the next cycle.
Step S500, after finishing the fine conversion, outputting a data result, ending the conversion process of the whole zoom ADC, and preparing to start the next conversion. It should be appreciated that the integrator needs to be Reset (Reset) each time a new conversion is started, due to the delta ADC.
Fig. 5 schematically shows the timing diagram of a cycle of the switching process of the switching method described above. Each of the control signals listed in the figure is active high. As shown, all timing signals, including the reset signal RST, the bypass control signal sar_en, the coarse transition completion signal c_done, the fine transition completion signals f_done, Φ1, Φ2, and the like, are generated by handshake transfer, except for the START-up signal START. The whole system thus achieves a completely self-timed measurement.
The self-timed integrator used in the fine converter of the present invention may be implemented in a variety of ways, for example, referring to fig. 6, as an alternative embodiment, a Comparator-Based Switched Capacitor integrator CBSC (Comparator-Based Switched-Capacitor). Which includes an inverter with auto-zero (Autozeroing) to act as a threshold comparator. During the charge transfer cycle (i.e., the integration process), the integrator charges the integration capacitors (see C I1、CI2 in fig. 3, not shown in fig. 6 for simplicity) with two unidirectional current sources E1, E2 of different magnitudes, respectively. Because of the unidirectional current source structure, in order to ensure the correct initial state of the circuit, the output voltage Vo is preset to a higher voltage Vpx, then the capacitor is charged by a larger current source E1, and after early threshold detection (early-threshold detection), the capacitor is charged by a smaller current source E2. The timing diagram of the integrator in fig. 6 during fine switching can be seen with reference to fig. 7. The labels in fig. 6 and 7 are explained as follows:
phi AZ: an auto-zero period, in the phase of its control, the offset voltage offset of the inverter is stored onto Cc so that this offset does not affect the accuracy of the charge transfer during the subsequent charge transfer period (integration process);
Cbwl: a bandwidth limiting (bandwidth-limited) capacitor to limit the bandwidth of the first inverter (i.e., pre-amp) inverter, which is advantageous for noise reduction;
D: decision (decision) results;
DE: early threshold decision (decision) results;
Ccls: a Correlated level shift (Correlated LEVEL SHIFTING) capacitor, through which the output voltage of the integrator is charged and discharged, instead of being directly discharged, can isolate the current source from the output of the integrator, so that the output voltage of the integrator does not directly modulate the current source, contributing to improving linearity;
P: a preset period for performing a preset (pulling up the integrator output voltage to ensure that the integrator input Vx is above the signal zero Vcm of the circuit) before charge transfer;
Vbc: the bias voltage of the coarse current source, "bc", i.e. "bias coarse";
Vbf1: the first bias voltage of the thin current source, "bf1", i.e., "bias fine 1";
Vbf2: the second bias voltage required by the thin current source (cascode bias to increase the current source output impedance), "bf2", i.e., "bias fine 2".
In some embodiments, vpx may be fixed, e.g., preset to the system supply voltage VDD. However, since this predetermined process is an additional charging process, unnecessary power consumption is actually generated. According to the analysis, the correct circuit state can be ensured as long as Vpx is equal to the forward highest swing voltage of the integrator. Thus, as a preferred embodiment, instead of the fixed VDD, a dynamically adjustable Vpx may be used, and an appropriate Vpx value may be selected by determining the output swing of the integrator, such as the density estimator (Density Estimator) shown in fig. 3, so that it is satisfied that the virtual ground voltage Vx of the integrator needs to be preset above the zero Vcm of the circuit, while minimizing the additional power consumption due to the preset. Referring to fig. 8, a schematic diagram of the density estimator dynamically adjusting the integrator preset output voltage Vpx is exemplarily shown. Firstly judging the output swing of the integrator by judging the density mu of the bit sequence bs of the front X bits (namely the number of 1 in bs) which is output in the fine conversion process, wherein obviously, the range of mu is 0< mu <1, when mu is about 0.5, the feedback of the circuit is alternately changed between positive and negative reference voltages, and the output swing of the integrator is supposed to be minimum; whereas the output swing of the integrator should be maximum when μ is close to 0 or 1. Vpx can thus be dynamically adjusted according to |mu-0.5|, the smaller the absolute value, the smaller Vpx. For example, a set of 4 preset values Vp1< Vp2< Vp3< Vp4 may be set, with an appropriate one selected according to the change in μ, so that this adjusted Vpx is used in the subsequent conversion process. In this process, the operations of accumulating 1 to obtain a value a, accumulating the bit sequence to obtain a value b, and subsequent calculation and selection can be performed in the digital domain.
Referring to fig. 9, as another alternative embodiment, an amplifier and Comparator Based Switched Capacitor integrator ACBSC (AMPLIFIER AND Comparator-Based Switched-Capacitor). It comprises two inverters with auto-zeroing, one acting as a threshold comparator and the other as an amplifier. Compared to the CBSC of fig. 6, ACBSC employs a negative feedback amplifier to assist the discharge, so that a coarse current source like that of fig. 6 is no longer required, but only a fine current source is required to produce a zero crossing detection effect to achieve the self-timing operation requirement. During integration, the integrating capacitor C I is charged based on the output of the threshold comparator and the fine current source.
The timing diagram of the integrator in fig. 9 during fine switching can be referred to fig. 10. It can be seen that because a negative feedback amplifier is used instead of a coarse current source, the mode of discharge is first exponential (mainly the amplifier acts), and as the voltage gradually goes towards the common mode voltage, the dynamic current of the amplifier gradually becomes smaller, and at the point close to the common mode voltage, the discharge mainly depends on a fine current source, so that the discharge gradually tends towards the linear discharge. ACBSC have the advantages that: (1) The exponential discharge efficiency is higher, the completion of discharging is faster, and the overall energy efficiency of the system is easier to improve. (2) Since the dynamic current when the inverter is used as an amplifier is maximum when the input voltage is VDD or ground voltage (GND) and gradually decreases as the input voltage tends to the common mode voltage Vcm, although the early threshold detection function is still included in fig. 8, the early threshold detection can be ignored in practice, since the dynamic current generated by the amplifier naturally decreases as the charging and discharging process proceeds, in other words, the dynamic "coarse current source" is turned "off itself. Referring to fig. 11, a diagram is shown that omits early threshold detection ACBSC, and the threshold comparator only generates one output of the decision result D, and controls the thin current source to charge the integrating capacitor C I. The timing diagram of the integrator in fig. 11 during fine switching can be referred to fig. 12. (3) ACBSC, if part of its comparator is turned off, becomes a conventional integrator relying on an external clock, so that an ADC constructed with this type of integrator can be switched conveniently between self-timing and external clock modes, giving the system the possibility of choosing according to the application.
The foregoing is illustrative of the principles and embodiments of the present invention, with the understanding that the above embodiments are merely intended to aid in the understanding of the invention and are not to be construed as limiting of the invention. Variations of the above embodiments may be made by those of ordinary skill in the art in light of the present teachings.
Claims (10)
1. An analog-to-digital conversion method using a scaled delta analog-to-digital converter ADC comprising a coarse converter and a fine converter, characterized in that,
The coarse converter is a successive approximation ADC and the fine converter is a second order delta ADC comprising a first integrator and a second integrator in series, each integrator comprising a zero crossing detection circuit ZCBC;
the scaling type incremental ADC is provided with a first control signal phi 1 and a second control signal phi 2, wherein the first integrator is controlled to start sampling and the second integrator is controlled to start integrating when phi 1 is effective, the first integrator is controlled to start integrating and the second integrator is controlled to start sampling when phi 2 is effective, zero crossing signals are generated when the integration process of each integrator is finished, and the zero crossing signals are used for controlling the effective switching of phi 1 and the effective switching of phi 2, and the two integrators push each other to enable phi 1 and phi 2 to be self-timing control signals;
The method comprises the steps of:
Acquiring a starting signal;
starting a coarse conversion process executed by the coarse converter according to the starting signal, wherein the coarse conversion adopts a successive approximation mode, starts from the MSB of the highest bit, runs for N1 periods, wherein N1 is an integer greater than or equal to the number of precision bits of the coarse conversion, samples an input voltage Vin to be converted in each period of the coarse conversion through phi 1 control, generates a predicted voltage value corresponding to the current bit through phi 2 control, quantizes a difference value between the predicted voltage value and Vin through a comparator, and determines data of the current bit according to a quantization result;
After the whole period execution of the coarse conversion is completed, taking a predicted voltage value Vref corresponding to a result m of the coarse conversion as a reference voltage for the fine conversion, starting a fine conversion process executed by the fine converter, wherein the fine conversion is operated for N2 periods in an oversampling noise shaping mode, N2 is an integer determined according to the conversion precision requirement of Vin, in each period of the fine conversion, sampling and integration are alternately controlled through phi 1 and phi 2, and the output of the two integrators is quantized through a comparator after being combined, and a corresponding bit sequence is output.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
N1 is set to the number of precision bits of the coarse conversion plus 1, and the coarse conversion process is further increased to perform a period in which the predicted voltage value is set to (m+0.5) ×vlsb, which is a precision step of the coarse conversion, after judging to the least significant bit LSB, thereby determining whether to select m-1 to m+1 or m to m+2 in the fine conversion.
3. The method of claim 1, wherein the step of determining the position of the substrate comprises,
The same digital-to-analog converter DAC is used to provide the predicted voltage value in the coarse conversion and Vref in the fine conversion,
Quantization in the coarse and fine conversions is performed using the same comparator,
The coarse conversion uses the first integrator in the fine conversion to store the difference of the predicted voltage value from Vin,
The scaled delta ADC is provided with a bypass control signal SAR EN which, when active, bypasses the second integrator from the input of the comparator,
The method further includes, upon starting the coarse transformation process, setting sar_en to active until the coarse transformation is complete.
4. A method according to any one of claims 1 to 3, further comprising
In the fine conversion process, the density μ of the outputted bit sequence is determined, the preset voltage Vpx at the output end of ZCBC is dynamically adjusted according to |μ -0.5|, the smaller the absolute value is, the smaller the Vpx is, and the Vpx is used for meeting the requirement that the virtual ground voltage Vx of the corresponding integrator is preset to be above the common mode voltage Vcm of the circuit.
5. A scaled delta analog-to-digital converter, comprising:
a coarse converter employing a successive approximation ADC for performing a coarse conversion process;
a fine converter employing a second order delta sigma ADC for performing a fine conversion process comprising a first integrator and a second integrator in series, each integrator comprising a zero crossing detection circuit ZCBC;
the state control module is used for setting a first control signal phi 1 and a second control signal phi 2, wherein the first integrator is controlled to start sampling and the second integrator is controlled to start integrating when phi 1 is valid, the first integrator is controlled to start integrating and the second integrator is controlled to start sampling when phi 2 is valid, zero crossing signals are generated when the integration process of each integrator is completed, and the zero crossing signals are used for controlling the effective switching of phi 1 and the effective switching of phi 2, and the two integrators are pushed by each other so that phi 1 and phi 2 become self-timing control signals;
And is used to obtain the start signal,
Starting the coarse conversion process according to the start signal, starting the coarse conversion from the most significant MSB by adopting a successive approximation mode, running for N1 periods, wherein N1 is an integer greater than or equal to the precision bit number of the coarse conversion, sampling the input voltage Vin to be converted by phi 1 control in each period of the coarse conversion, generating a predicted voltage value corresponding to the current bit by phi 2 control, quantizing the difference value between the predicted voltage value and Vin by a comparator, determining the data of the current bit according to the quantized result,
After the whole period execution of the coarse conversion is completed, taking a predicted voltage value Vref corresponding to a result m of the coarse conversion as a reference voltage for the fine conversion, starting the fine conversion process, operating N2 periods by adopting an oversampling noise shaping mode in the fine conversion, wherein N2 is an integer determined according to the conversion precision requirement of Vin, alternately controlling two integrators to sample and integrate through phi 1 and phi 2 in each period of the fine conversion, and quantizing the outputs of the two integrators through a comparator after combining to output a corresponding bit sequence.
6. The scaled delta analog-to-digital converter of claim 5, wherein,
The coarse converter and the fine converter use the same digital-to-analog converter DAC for providing a predicted voltage value in the coarse conversion and Vref in the fine conversion,
The coarse converter and the fine converter use the same comparator for quantization in the coarse conversion and the fine conversion,
The coarse converter further comprises a first integrator in the fine converter for storing a difference between a predicted voltage value and Vin;
The state control module is further configured to set a bypass control signal sar_en, and when the coarse conversion process is started, set sar_en to be valid until the coarse conversion is completed, and when the sar_en is valid, control to bypass the second integrator from the input end of the comparator.
7. The scaled delta analog-to-digital converter of claim 6, wherein,
The DAC further comprises an output circuit for providing 0.5 x VLSB, wherein VLSB is the precision step size of the coarse conversion;
the state control module is further configured to, during the coarse transition, after determining to the least significant LSB, add to execute a period in which the predicted voltage value is set to (m+0.5) VLSB, thereby determining whether to select a range of m-1 to m+1 or m to m+2 in the fine transition.
8. The scaled incremental analog-to-digital converter of any one of claims 5-7 wherein,
The state control module is further configured to determine, during the fine transition, a density μ of the outputted bit sequence, dynamically adjust, according to |μ -0.5|, an output preset voltage Vpx of ZCBC, where the smaller the absolute value is, the smaller Vpx is, and Vpx is used to satisfy that a virtual ground voltage Vx of a corresponding integrator is preset above a common mode voltage Vcm of the circuit.
9. The scaled delta analog-to-digital converter of claim 5, wherein,
At least one of the two integrators adopts a switched capacitor integrator ACBSC based on an amplifier and a comparator, and comprises two inverters with auto-zero, one is used as a threshold comparator, the other is used as an amplifier, the amplifier adopts negative feedback type, the dynamic current of the amplifier is reduced along with the progress of charge and discharge,
In the integration process, the threshold comparator generates two paths of output of a judgment result and an early threshold judgment result, and the amplifier and a thin current source are respectively controlled to charge a capacitor for integration; or the threshold comparator generates one path of judgment result to output, and controls a thin current source to charge a capacitor for integration.
10. The scaled delta analog-to-digital converter of claim 5, wherein,
At least one of the two integrators employs a comparator-based switched capacitor integrator CBSC, comprising an inverter with auto-zero, acting as a threshold comparator,
The threshold comparator generates two paths of output of a judgment result and an early threshold judgment result, controls a coarse current source and a fine current source to charge a capacitor for integration respectively, charges the capacitor by the coarse current source firstly, and charges the capacitor by the fine current source after the early threshold judgment result is effective.
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