CN114285414A - Scaling type incremental analog-to-digital conversion method and converter - Google Patents
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Abstract
An analog-to-digital conversion method and a scaling incremental analog-to-digital converter (ADC) are provided, wherein the ADC comprises a successive approximation ADC used as a coarse converter and a second-order incremental ADC used as a fine converter, and comprises two integrators which are connected in series, and each integrator comprises a zero-crossing detection circuit. In the method, two control signals phi 1 and phi 2 are set to alternately control sampling and integration of two integrators, phi 1 effective and phi 2 effective switching is controlled according to a zero-crossing signal generated when the integration process of each integrator is completed, the two integrators are mutually pushed, so that the phi 1 and the phi 2 become self-timing control signals, and self-timing execution of a coarse conversion process and a fine conversion process is controlled through integral time sequence design.
Description
Technical Field
The invention relates to the technical field of Analog-to-Digital converters (ADCs), in particular to a scaling type Incremental Analog-to-Digital conversion method and a Converter (Zoom Incremental ADC).
Background
With the development of electronic information technology, the application of sensors is increasingly widespread. The sensor is a device for converting physical signals in reality, such as temperature, humidity, gas concentration, and various biological signals, into electrical signals, so that the physical signals containing important information can be accurately and rapidly measured by means of the powerful capability of electrical signal processing. At present, wearable or portable sensor systems are playing an increasingly important role for health, medical, environmental monitoring and other purposes. Due to the requirements of portable applications, these sensor systems need to have the characteristics of low power consumption, small size, low cost, simple circuit structure, etc.
The core part of the sensor system is usually an ADC, which functions to convert the time and amplitude continuous electrical signal output by the sensor into a digital signal, so that the digital signal can be subsequently processed, stored and transmitted easily and reliably. Binary search based Successive Approximation ADC (SAR ADC) and Oversampling Noise Shaping (Oversampling and Noise Shaping) Δ Σ ADC are two main types.
The SAR ADC can achieve a higher conversion speed, so that the SAR ADC has higher energy efficiency and meets the requirement of low power consumption. However, limited by the mismatch of the components, some additional technical means are usually required to achieve higher measurement accuracy (e.g., >12 bit), which may result in higher power consumption or cost.
Oversampling noise-shaping Δ Σ ADCs can achieve higher resolution and accuracy, but because of the oversampling technology, low-order Δ Σ ADCs generally require longer conversion time, while high-order Δ Σ ADCs often have limited dynamic range of input signals and higher circuit complexity to meet the stability requirement.
In practical applications, the bandwidth requirement of a sensor system for measuring environmental parameters or biological signals is usually not high, for example, low frequency or near direct current, but high precision, high linearity and low power consumption are required, so that an oversampling noise integral form Δ Σ ADC is usually adopted. In such systems, the ADC often operates in a low duty cycle manner, i.e., is cleared (Reset) each time it starts to operate, and is turned off after completing a transition until triggered by the next signal, to reduce unnecessary static power consumption. This type of ADC is referred to as an incremental ADC.
One solution that has emerged in recent years is a hybrid ADC that combines these two types of converters, namely a scaled (Zoom) incremental ADC. See "Y. Chae, K. Source, and K.A.A. Makinwa," A6.3. mu.W 20 bit interferometric ADC with 6 ppm INL and 1. mu.V offset, "IEEE J. Solid-State Circuits, vol. 48, No. 12, pp. 3019-3027, Dec. 2013. The conversion process of the scaled ADC is divided into two steps, first a coarse conversion (coarse conversion) with the SAR ADC to quickly determine the approximate range of the signal. Fine conversion (fine conversion) is then performed on the reduced scale with a Δ Σ ADC to complete accurate measurement of the signal.
The scaling type incremental ADC combines the high efficiency of the SAR ADC and the high accuracy of the Δ Σ ADC, and is an ideal solution for a low power consumption sensor. But a potential problem is that the design of the sequential circuit is complex. To avoid the need for high speed clocks and to improve conversion efficiency, SAR ADCs are typically implemented in an Asynchronous (Asynchronous) manner. A delta-sigma ADC for fine conversion still requires an external high-speed clock signal to achieve oversampling, which results in increased system complexity and increased power consumption and cost. Although Self-Timed (Self-Timed) Δ Σ ADCs have also been investigated, see "c. Chen, z. Tan and m.a.p. Pertijs," A1V 14b Self-Timed zero-crossing-based increment Δ Σ ADC, "2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, pp. 274 cake 275, doi: 10.1109/isscc.2013.6487732", there is no overall design to integrate a locally asynchronous and a locally synchronous subsystem.
Disclosure of Invention
According to an aspect of the present invention, there is provided an analog-to-digital conversion method using a scaled delta-ADC including a coarse converter and a fine converter, wherein,
the coarse converter is a successive approximation type ADC, the fine converter is a second-order incremental type ADC, and the second-order incremental type ADC comprises a first integrator and a second integrator which are connected in series, and each integrator comprises a Zero-cross-Based circuit ZCBC (Zero-cross-Based Circuits);
the scaling type incremental ADC is internally provided with a first control signal phi 1 and a second control signal phi 2, wherein phi 1 controls a first integrator to start sampling and a second integrator to start integrating when effective, phi 2 controls the first integrator to start integrating and the second integrator to start sampling when effective, and each integrator generates a zero-crossing signal when the integration process is completed and is used for controlling the effective switching of phi 1 and phi 2, and the two integrators are mutually pushed to enable phi 1 and phi 2 to become self-timing control signals;
the method comprises the following steps:
acquiring a starting signal; starting a coarse conversion process executed by a coarse converter according to a starting signal, running for N1 cycles from the most significant bit MSB by adopting a successive approximation mode, wherein N1 is an integer which is more than or equal to the precision bit number of the coarse conversion, sampling an input voltage Vin to be converted by phi 1 control in each cycle of the coarse conversion, generating a predicted voltage value corresponding to the current bit by phi 2 control, quantizing the difference value between the predicted voltage value and Vin by a comparator, and determining the data of the current bit according to a quantization result;
after the execution of all the periods of the coarse conversion is finished, taking a predicted voltage value Vref corresponding to a result m of the coarse conversion as a reference voltage for the fine conversion, starting the fine conversion process executed by the fine converter, operating N2 periods by adopting an oversampling noise shaping mode, wherein N2 is an integer determined according to the conversion precision requirement of Vin, in each period of the fine conversion, alternately controlling two integrators to sample and integrate through phi 1 and phi 2, quantizing the outputs of the two integrators after being combined by a comparator, and outputting a corresponding bit sequence.
According to another aspect of the present invention, there is provided a scaled delta ADC comprising:
a coarse converter employing successive approximation ADC for performing a coarse conversion process;
a fine converter employing a second order delta-sigma ADC for performing a fine conversion process, comprising a first integrator and a second integrator in series, each integrator comprising a ZCBC;
and the state control module is used for controlling to execute the analog-to-digital conversion method.
According to the scaling incremental ADC solution, the whole time sequence is subjected to self-timing control through the whole unified self-timing design, and the time sequence control requirements in the two stages of coarse conversion and fine conversion are coordinated, so that the external clock requirement in the traditional scaling incremental ADC is removed, and the problems of the complex time sequence circuit design of the scaling incremental ADC and the additional cost and power consumption of the scaling incremental ADC are solved. The difficulty of system integration of the scaling type incremental ADC in practical application is greatly reduced, and the robustness and reliability of the ADC are improved.
Specific examples according to the present invention will be described in detail below with reference to the accompanying drawings. As used herein, ordinal terms such as "first," "second," etc., are used for identification purposes only and are not intended to have an absolute meaning.
Drawings
FIG. 1 is a schematic diagram of a scaled delta ADC according to the present invention;
FIG. 2 is a system block diagram of a scaled incremental ADC according to the present invention;
FIG. 3 is an overall design of a scaled delta ADC according to an example of the present invention;
FIG. 4 is a flow chart illustrating a scaled incremental analog-to-digital conversion method according to the present invention;
FIG. 5 is a timing diagram of a one-cycle conversion process of an exemplary conversion method according to the present invention;
FIG. 6 is a schematic diagram of a comparator based switched capacitor integrator for use in the present invention;
FIG. 7 is a timing diagram of the integrator of FIG. 6 during a fine transition;
FIG. 8 is a schematic diagram of a dynamically adjusting integrator preset output voltage as applied to the present invention;
FIG. 9 is a schematic diagram of a switched capacitor integrator based on an amplifier and comparator for use in the present invention;
FIG. 10 is a timing diagram of the integrator of FIG. 9 during a fine transition;
FIG. 11 is a schematic diagram of another amplifier and comparator based switched capacitor integrator for use in the present invention;
fig. 12 is a timing diagram of the integrator of fig. 11 during a fine transition.
Detailed Description
The present invention provides a self-timed asynchronous scaled incremental ADC solution that does not require an external clock signal. An example of a solution according to the invention can be seen in fig. 1 and 2, comprising a two-stage conversion process, implemented by a coarse converter and a fine converter, respectively.
The coarse converter Con-c is an M-bit SAR ADC for determining the approximate range of the input voltage Vin to be converted. The method is operated in a successive approximation mode, and starts from the most Significant bit MSB (most Significant bit), a Digital-to-Analog Converter (DAC) is controlled to output a predicted voltage value corresponding to the current bit, the predicted voltage value is compared with Vin (direct comparison or difference result quantization and the like), the data of the current bit is determined according to the comparison result, the data of the next bit is continuously judged until the comparison of M bits is completed, and a result M of coarse conversion is determined. The result of the SAR ADC may lock Vin in the range of one least Significant bit lsb (least Significant bit) of Vref, where Vref is the predicted voltage value corresponding to m. That is, from the result m of the coarse conversion, it can be determined that Vin falls within an interval of one LSB of Vref: m VLSB < Vin < (m +1) > VLSB, where VLSB is the precision step size of the coarse conversion.
The fine converter Con-f employs an oversampling noise shaping form Δ Σ ADC. And integrating and quantizing the differential value of Vin and the reference voltage in an oversampling manner within a preset reference voltage range for a plurality of periods. The output bit sequence bs (bit stream) can further adopt an extraction filter df (differentiation filter) to perform noise filtering to obtain valid data. After being combined with the result of the coarse conversion, the final output conversion result Dout is obtained.
The existing scaling ADCs all use the conventional delta-sigma ADC with a fixed oversampling clock frequency during the fine conversion. The fine converter in the invention adopts a self-timing delta-sigma ADC, specifically adopts a second-order incremental delta-sigma ADC comprising two integrators connected in series, the outputs of the two integrators are combined and quantized by a comparator, and a corresponding bit sequence bs is output. Each integrator comprises a zero crossing detection circuit ZCBC. Each integrator determines the completion of an integration period by detecting whether the virtual ground voltage at the input of the integrator reaches the circuit signal zero (i.e., the common mode voltage Vcm). A transitive, asynchronous switching sequence can be realized by the decision of the zero crossings alternately by the two integrators. The overall self-timing sequence control can be performed by a state machine operating in a digital domain, after the start-up execution, the state machine firstly operates the control logic SAR-Log of the coarse conversion stage, controls the coarse converter Con-c to operate for N1 cycles in a self-timing mode, and continues to operate the control logic DeltaSigma-Log of the fine conversion stage after the coarse conversion is completed, and controls the fine converter Con-f to operate for N2 cycles in a self-timing mode, so that the whole conversion process is completed. Specifically, a first control signal Φ 1 and a second control signal Φ 2 may be set, a state a of the state machine corresponds to Φ 1 being valid, the first integrator is controlled to start sampling and the second integrator starts integrating, a state B of the state machine corresponds to Φ 2 being valid, the first integrator is controlled to start integrating and the second integrator starts sampling, and when the integration process of each integrator is completed (i.e., when a zero-crossing signal is detected), the corresponding state is completed, and the valid switching of Φ 1 and Φ 2 is triggered. In this way, φ 1 and φ 2 are self-timed control signals, driven by each other by the two integrators.
As a preferred embodiment, the result value m of the coarse conversion may be stored in a SAR register SAR-r for reconfiguring the DAC to output Vref as a reference voltage for the fine conversion. This allows the DAC to be reused in both the course of the coarse and fine conversions by reconfiguration, thereby saving chip area.
As a preferred embodiment, the same comparator may be used for quantization (comparison) in the coarse and fine conversions, as shown in fig. 2, to further save chip area. In this case, the output of the fine conversion circuit may be bypassed using a bypass control signal SAR _ EN during the coarse conversion stage, so that the differential result of the coarse conversion is directly input to the input terminal of the comparator for quantization.
Referring to fig. 3, an overall design of a scaled delta ADC according to an example of the invention is shown. It consists of one M =5 SAR ADC (coarse converter) and one second order delta-sigma ADC (fine converter). The reference voltages output by the DACs are configured by switching signals S0-6p and S0-6n output by registers SAR-r, where VREFP and VREFN are positive and negative reference voltage sources, respectively. In the fine converter, the outputs of the two integrators are combined using a Switched-Capacitor Adder SCA (Switched-Capacitor Adder adapter) to form a feed-forward path around the second integrator. In fig. 3, to facilitate better multiplexing of the coarse/fine converter circuit, the first integrator of the fine converter is also used to store the difference between the predicted voltage value and Vin during the course of the coarse conversion, while the second integrator is not used during the course of the coarse conversion. Thus, during the course of the coarse transition, the second integrator is bypassed by the bypass control signal SAR _ EN. "Log" shown in the figure is a logic circuit for performing switching control according to the comparison result.
Typically, the operating period N1 of the coarse conversion is determined by its precision number of bits M, but N1 may be larger than M. For example, in fig. 3, a capacitor of C/2 is added to the DAC, which allows the coarse conversion process to be performed after the least significant bit LSB is determined, and a cycle is added in which the predicted voltage value is set to (m + 0.5) × VLSB, where VLSB is the precision step size of the coarse conversion, thereby determining whether m-1 to m +1 or m to m +2 is selected in the subsequent fine conversion. This increased decision period adds a redundancy range of one LSB to the fine transition, resulting in a better fault tolerance for the system. The operating period of the fine conversion (i.e., the oversampling period) N2 may then be determined based on the conversion accuracy requirement for Vin.
A flowchart of a conversion method according to the present invention may be referred to fig. 4, and for ease of understanding, the following description will be made with reference to the exemplary plan view of fig. 3 in describing the conversion method. In the whole conversion process, the timing steps of the whole ADC are uniformly controlled by a state machine so as to ensure the completion of each current conversion step and promote the next step. The method comprises the following steps:
in step S100, a start signal is obtained to start a new conversion process. This signal may be provided by a preset threshold, for example, it may be determined whether a change in the state of the physical quantity being measured causes a change in the state of the sensor that exceeds the threshold, and if so, the activation signal is triggered, and if not, it remains on hold.
And step S200, starting the state machine according to the starting signal and starting a coarse conversion process.
The state machine controls the coarse converter to run for N1 cycles in a self-timed manner. In each period of the coarse conversion, sampling an input voltage Vin to be converted through phi 1 control, generating a predicted voltage value corresponding to a current bit through phi 2 control, quantizing a difference value Vx1 between the predicted voltage value and Vin through a comparator, and determining data bi, i belonging to [1, M ] of the current bit according to a quantization result.
In the example shown in FIG. 3, the delay signals φ 1d and φ 2d of φ 1 and φ 2 are further employed for control. This delay is simply to meet the requirement that the switches controlled by φ 1d and φ 2d are not open at the same time as the switches controlled by φ 1 and φ 2, so as to reduce Channel Charge Injection (Channel Charge Injection). This is the normal operation of a switched capacitor circuit, and φ 1d and φ 1 can be considered equivalent, while φ 2d and φ 2 are considered equivalent in control logic.
Phi 2_ st is further employed for control. φ 2_ st is a control signal that extends out based on φ 2, for the portion of the φ 2 cycle after the preset is completed. At the beginning of the period φ 2, a preset is first performed (pulling the integrator output voltage high, ensuring that the integrator input is above the signal zero Vcm of the circuit), after which the actual charge transfer begins, so "st" here means "start transfer".
In step S300, it is determined that the execution of all cycles of the coarse conversion is completed, and the predicted voltage value Vref corresponding to the coarse conversion result m is set as the reference voltage for the fine conversion.
Step S400, starts the fine conversion process for Vin.
The state machine controls the fine converter in a self-timed manner to run for N2 cycles in an oversampling noise shaping manner. In each period of the fine conversion, the two integrators are alternately controlled by phi 1 and phi 2 to carry out sampling and integration, the outputs of the two integrators are combined and then quantized by a comparator, and a corresponding bit sequence is output. Specifically, at the beginning of each cycle of the fine transition, φ 1 is asserted to place the first integrator in the sampling state and initiate the integration process of the second integrator, and φ 1 is deasserted and switched to φ 2 to initiate the integration process of the first integrator and place the second integrator in the sampling state when the integration of the second integrator is completed. And when the integration of the first integrator is completed, triggering the comparator to perform comparison, and setting phi 2 to be invalid and switching to be valid as phi 1 so as to start the execution of the next period.
Step S500, after the fine conversion is completed, outputting the data result, ending the conversion process of the whole scaling ADC, and preparing to start the next conversion. It will be appreciated that, being an incremental ADC, the integrator needs to be Reset (Reset) each time a new conversion is started.
Fig. 5 exemplarily shows a timing diagram of one-cycle switching process of the above switching method. Each of the control signals listed in the figure is active high. As shown, all timing signals, including the reset signal RST, the bypass control signal SAR _ EN, the coarse transition complete signal C _ Done, the fine transition complete signal F _ Done, φ 1, φ 2, etc., are generated by handshake transfer, except for the initial START signal START. The whole system thus achieves a completely self-timed measurement.
The self-timed integrator used in the fine converter of the present invention may be implemented in a variety of ways, for example, with reference to fig. 6, as an alternative embodiment, a Comparator-Based Switched Capacitor integrator CBSC (Comparator-Based switch-Capacitor). Which includes an inverter with auto-zeroing (Autozeroing) to act as a threshold comparator. During the charge transfer period (i.e. the integration process), the integrator uses two unidirectional current sources E1, E2 with different sizes as integration capacitors (see C in fig. 3)I1、CI2Not shown in fig. 6 for simplicity). Due to the adoption of a one-way current source structure, in order toTo ensure the initial state of the circuit is correct, the output voltage Vo is first preset to a higher voltage Vpx, then the capacitor is first charged by the larger current source E1 and then by the smaller current source E2 after early-threshold detection. The timing diagram of the integrator during the fine transition in fig. 6 can be referred to fig. 7. The labels in fig. 6 and 7 are explained as follows:
phi AZ: an auto-zero period, during which the offset voltage offset of the inverter is stored onto Cc during the phase of its control, so that this offset does not affect the accuracy of the charge transfer during the subsequent charge transfer period (integration process);
cbwl: a bandwidth-limited (bandlimited) capacitor for limiting the bandwidth of the first inverter (i.e., the pre-amp inverter), which is advantageous for reducing noise;
d: decision (decision) result;
DE: early threshold decision (decision early) result;
ccls: a Correlated Level Shifting (Correlated Level Shifting) capacitor, which can isolate the current source from the output of the integrator by charging and discharging the capacitor instead of directly discharging the output voltage of the integrator, so that the output voltage of the integrator cannot directly modulate the current source, which is helpful for improving linearity;
p: a preset period, which is used for presetting (pulling up the output voltage of the integrator to ensure that the input end Vx of the integrator is above the signal zero point Vcm of the circuit) before charge transfer;
vbc: bias voltage of the coarse current source, "bc" is "bias coarse";
vbf 1: the first bias voltage of the fine current source, "bf 1", i.e., "bias fine 1";
vbf 2: the second bias voltage required by the fine current source (cascade bias for increasing the output impedance of the current source), "bf 2" or "bias fine 2".
In some embodiments, Vpx may be fixed, e.g., preset to the system supply voltage VDD. However, since this predetermined process is an additional charging process, unnecessary energy consumption is actually generated. According to the analysis, the circuit state can be guaranteed to be correct as long as Vpx is equal to the highest forward swing voltage of the integrator. Therefore, as a preferred embodiment, instead of the fixed VDD, a dynamically adjustable Vpx may be used, and an appropriate Vpx value is selected by determining the output swing condition of the integrator, such as a Density Estimator (Density Estimator) shown in fig. 3, so that the virtual ground voltage Vx of the integrator needs to be preset to be above the signal zero Vcm of the circuit, and the extra power consumption caused by the presetting is minimized. Referring to fig. 8, a schematic diagram of the density estimator dynamically adjusting the integrator preset output voltage Vpx is illustratively shown. Firstly, judging the output swing of the integrator by judging the density mu of the bit sequence bs of the first X bits (namely the number of 1 in bs) output in the fine conversion process, obviously, the range of mu is 0< mu <1, when mu is approximately equal to 0.5, the feedback of the circuit is changed alternately between positive reference voltage and negative reference voltage, and the output swing of the integrator should be minimum; and the output swing of the integrator should be at a maximum when μ is close to 0 or 1. Vpx can therefore be dynamically adjusted according to | μ -0.5| the smaller the absolute value, the smaller Vpx. For example, a set of 4 preset values Vp1< Vp2< Vp3< Vp4 may be set, and an appropriate one of the preset values is selected according to the change in μ, so that this adjusted Vpx is used in the subsequent conversion process. In the process, the value a obtained by accumulating 1, the value b obtained by accumulating the bit sequence, and subsequent operations such as calculation and selection can be performed in the digital domain.
Referring to fig. 9, as another alternative embodiment, the present invention is a Switched Capacitor integrator ACBSC (Amplifier and Comparator-Based Switched-Capacitor integrator) Based on an Amplifier and a Comparator. It includes two inverters with auto-zero, one serving as a threshold comparator and the other as an amplifier. Compared with the CBSC in fig. 6, ACBSC uses a negative feedback amplifier to assist the discharge, so that a coarse current source like that in fig. 6 is not needed, and only a fine current source is needed to generate a zero-crossing detection effect, so as to achieve the self-timing operation requirement. Controlling amplifier and finesse based on output of threshold comparator during integrationCurrent source pair integrating capacitor CIAnd charging is carried out.
The timing diagram of the integrator during the fine transition in fig. 9 can be referred to fig. 10. It can be seen that because a negative feedback amplifier is adopted to replace a coarse current source, the discharge mode is firstly exponential discharge (mainly the amplifier functions), the dynamic current of the amplifier becomes gradually smaller as the voltage gradually approaches to the common-mode voltage, and the discharge mainly depends on a fine current source at the position close to the common-mode voltage, so that the discharge gradually approaches to linear discharge. The ACBSC has the advantages that: (1) the exponential type discharge efficiency is higher, the discharge can be completed more quickly, and the overall energy efficiency of the system can be improved more easily. (2) Since the dynamic current of the inverter as an amplifier is maximum when the input voltage is VDD or Ground (GND) and gradually decreases as the input voltage goes to the common mode voltage Vcm, although the function of early threshold detection is still included in fig. 8, in practice early threshold detection can be ignored, since the dynamic current generated by the amplifier naturally decreases as the charging and discharging process proceeds, in other words, this dynamic "coarse current source" will "turn off" itself. Referring to fig. 11, an ACBSC omitting early threshold detection is shown, in which a threshold comparator only generates a decision result D for output, and a fine current source is controlled to supply an integrating capacitor CIAnd charging is carried out. The timing diagram of the integrator during the fine transition in fig. 11 can be referred to fig. 12. (3) ACBSC becomes a conventional external clock-dependent integrator if part of its comparator is turned off, so an ADC constructed with this type of integrator can be easily switched between self-timed and external clock modes, providing the system with the possibility of selection depending on the application.
While the principles and embodiments of this invention have been described above using specific examples, it is to be understood that the above embodiments are merely provided to assist in understanding the invention and are not to be construed as limiting the invention. Variations of the above-described embodiments may be made by those skilled in the art, consistent with the principles of the invention.
Claims (10)
1. A method of analog to digital conversion using a scaled incremental analog to digital converter (ADC) comprising a coarse converter and a fine converter,
the coarse converter is a successive approximation ADC, the fine converter is a second-order incremental ADC and comprises a first integrator and a second integrator which are connected in series, and each integrator comprises a zero-crossing detection circuit ZCBC;
the scaling type incremental ADC is internally provided with a first control signal phi 1 and a second control signal phi 2, wherein the first integrator is controlled to start sampling and the second integrator to start integrating when phi 1 is effective, the first integrator is controlled to start integrating and the second integrator is controlled to start sampling when phi 2 is effective, a zero-crossing signal is generated when the integration process of each integrator is completed and is used for controlling the effective switching of phi 1 and phi 2, and the two integrators are mutually pushed to enable phi 1 and phi 2 to become self-timing control signals;
the method comprises the following steps:
acquiring a starting signal;
starting a coarse conversion process executed by the coarse converter according to the starting signal, wherein the coarse conversion adopts a successive approximation mode, and runs for N1 cycles from the most significant bit MSB, N1 is an integer which is more than or equal to the precision bit number of the coarse conversion, in each cycle of the coarse conversion, an input voltage Vin to be converted is sampled through phi 1 control, a predicted voltage value corresponding to the current bit is generated through phi 2 control, the difference value between the predicted voltage value and Vin is quantized through a comparator, and the data of the current bit is determined according to the quantization result;
after the execution of all the periods of the coarse conversion is finished, taking a predicted voltage value Vref corresponding to a result m of the coarse conversion as a reference voltage for fine conversion, starting the fine conversion process executed by the fine converter, wherein the fine conversion is executed for N2 periods in an oversampling noise shaping mode, N2 is an integer determined according to the conversion precision requirement of Vin, in each period of the fine conversion, two integrators are alternately controlled by phi 1 and phi 2 to carry out sampling and integration, the outputs of the two integrators are quantized by a comparator after being combined, and a corresponding bit sequence is output.
2. The method of claim 1,
n1 is set to the number of precision bits of the coarse conversion plus 1, and the coarse conversion process, after determining the least significant bit LSB, is further incremented by performing a cycle in which the predicted voltage value is set to (m + 0.5) × VLSB, where VLSB is the precision step size of the coarse conversion, thereby determining whether the range of m-1 to m +1 or m to m +2 is selected in the fine conversion.
3. The method of claim 1,
using the same digital-to-analog converter DAC to provide the predicted voltage value in the coarse conversion and Vref in the fine conversion,
the same comparator is used for quantization in the coarse and fine conversions,
the coarse conversion uses the first integrator in the fine conversion to store the difference of the predicted voltage value and Vin,
a bypass control signal SAR _ EN is provided in the scaled-delta ADC, which, when active, bypasses the second integrator out of the input of the comparator,
the method also includes, while initiating the coarse transition process, further setting SAR _ EN active until the coarse transition is complete.
4. The method of any one of claims 1 to 3, further comprising
And in the fine conversion process, judging the density mu of the output bit sequence, dynamically adjusting the output end preset voltage Vpx of the ZCBC according to the absolute value of mu-0.5, wherein the smaller the absolute value is, the smaller the Vpx is, and the Vpx is used for presetting the virtual ground voltage Vx of the corresponding integrator to be more than the common-mode voltage Vcm of the circuit.
5. A scaled incremental analog-to-digital converter, comprising:
a coarse converter employing successive approximation ADC for performing a coarse conversion process;
a fine converter employing a second order incremental delta-sigma ADC for performing a fine conversion process, comprising a first integrator and a second integrator in series, each integrator comprising a zero crossing detection circuit ZCBC;
the state control module is used for setting a first control signal phi 1 and a second control signal phi 2, wherein the first integrator is controlled to start sampling and the second integrator to start integrating when phi 1 is effective, the first integrator is controlled to start integrating and the second integrator is controlled to start sampling when phi 2 is effective, a zero-crossing signal is generated when the integration process of each integrator is completed and is used for controlling the effective switching of phi 1 and phi 2, and the two integrators are mutually pushed to enable phi 1 and phi 2 to become self-timing control signals;
and for obtaining a start-up signal for the device,
starting the coarse conversion process according to the starting signal, wherein the coarse conversion adopts a successive approximation mode, starting from the most significant bit MSB, running for N1 periods, N1 is an integer which is more than or equal to the precision bit number of the coarse conversion, in each period of the coarse conversion, sampling an input voltage Vin to be converted through phi 1 control, generating a predicted voltage value corresponding to the current bit through phi 2 control, quantizing the difference value of the predicted voltage value and the Vin through a comparator, and determining the data of the current bit according to the quantization result,
and after the execution of all the periods of the coarse conversion is finished, starting the fine conversion process by taking a predicted voltage value Vref corresponding to a result m of the coarse conversion as a reference voltage for the fine conversion, wherein the fine conversion is operated for N2 periods in an oversampling noise shaping mode, N2 is an integer determined according to the conversion precision requirement of Vin, in each period of the fine conversion, two integrators are alternately controlled by phi 1 and phi 2 to carry out sampling and integration, the outputs of the two integrators are quantized by a comparator after being combined, and a corresponding bit sequence is output.
6. The scaled, incremental type analog-to-digital converter of claim 5,
the coarse converter and the fine converter use the same digital-to-analog converter DAC for providing the predicted voltage value in the coarse conversion and Vref in the fine conversion,
the coarse converter and the fine converter use the same comparator for performing quantization in the coarse conversion and the fine conversion,
the coarse converter further comprises a first integrator in the fine converter for storing a difference between the predicted voltage value and Vin;
the state control module is also used for setting a bypass control signal SAR _ EN, when the coarse conversion process is started, the SAR _ EN is set to be effective until the coarse conversion is completed, and when the SAR _ EN is effective, the state control module controls the second integrator to bypass out of the input end of the comparator.
7. The scaled, incremental type analog-to-digital converter of claim 6,
the DAC further comprises an output circuit for providing 0.5 x VLSB, wherein VLSB is a precision step size of the coarse conversion;
the state control module is further configured to, during the coarse transition, increment and execute a cycle in which the predicted voltage value is set to (m + 0.5) × VLSB after the least significant bit LSB is determined, thereby determining whether the range of m-1 to m +1 or m to m +2 is selected in the fine transition.
8. A scaled incremental analog-to-digital converter according to any of claims 5 to 7,
and the state control module is further used for judging the density mu of the output bit sequence in the fine conversion process, dynamically adjusting the output end preset voltage Vpx of the ZCBC according to the absolute value of mu-0.5, wherein the smaller the absolute value is, the smaller the Vpx is, and the Vpx is used for presetting the virtual ground voltage Vx of the corresponding integrator to the common-mode voltage Vcm of the circuit.
9. The scaled, incremental type analog-to-digital converter of claim 5,
at least one of the two integrators adopts a switch capacitor type integrator ACBSC based on an amplifier and a comparator, which comprises two inverters with automatic zero adjustment, one is used as a threshold comparator, the other is used as an amplifier, the amplifier adopts a negative feedback type, the dynamic current of the amplifier is reduced along with the progress of the charging and discharging processes,
in the integration process, the threshold comparator generates two paths of outputs of a judgment result and an early threshold judgment result, and the amplifier and a thin current source are respectively controlled to charge a capacitor for integration; or the threshold comparator generates a decision result and outputs the decision result, and a thin current source is controlled to charge the capacitor for integration.
10. The scaled, incremental type analog-to-digital converter of claim 5,
at least one of the two integrators is a comparator-based switched capacitor integrator CBSC comprising an inverter with auto-zero, acting as a threshold comparator,
the threshold comparator generates two paths of outputs of a decision result and an early threshold decision result, respectively controls a coarse current source and a fine current source to charge a capacitor for integration, and the coarse current source charges the capacitor firstly, and the fine current source charges the capacitor after the early threshold decision result is valid.
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