CN115549683A - High-precision incremental zoom ADC (analog to digital converter) framework - Google Patents
High-precision incremental zoom ADC (analog to digital converter) framework Download PDFInfo
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Abstract
The invention provides a high-precision incremental zoom ADC (analog to digital converter) framework, which comprises the following components: a fine incremental DSM, a coarse quantization ADC, a residual feed forward module, and an extended count module; the residual error feedforward module is used for reconstructing signal feedforward of a CIFF structure in the fine incremental DSM and reducing the output swing amplitude of the incremental zoom ADC integrator; the input of the residual error feedforward module is the analog input VIN of the incremental type zoom ADC and the output k of the rough quantization ADC, and the residual error feedforward module outputs a feedforward signal which is used as a CIFF structure of the fine incremental DSM; the extended counting module is used for improving the signal quantization noise ratio SQNR of the incremental zoom ADC; the input of the expanding counting module is the output analog voltage of the last-stage integrator in the fine incremental DSM in the incremental mode in the last period, namely the analog quantization error of the incremental DSM in the CIFF structure, and the output is the digital value of the quantization error of the fine incremental DSM after analog-to-digital conversion.
Description
Technical Field
The invention relates to an ADC (analog to digital converter) architecture, in particular to a high-precision incremental zoom ADC architecture.
Background
For many applications, such as smart sensors, biomedical signal processing and battery-powered internet of things devices, high-precision low-power consumption ADCs (analog-to-digital converters) are required. IADC (delta-sigma analog-to-digital converter) is a better choice than a conventional DS ADC (delta-sigma analog-to-digital converter) because it has low latency and is easy to multiplex. However, the switching pattern of the IADC's Finite Impulse Response (FIR) causes its SQNR (signal to quantization noise ratio) to decrease.
A Zoom ADC (analog-to-digital converter) is a framework (reference: Y.Chae, K.souri and K.A.Makinwa, "A6.3 μ W20 bit Incremental Zoom-ADC with 6ppm INL and 1 μ V Offset," IEEE JSSC, vol.48, pp.12, pp.3019-3027, 2013.) combining SAR (successive approximation register) and DSM (delta-sigma modulator), and can reduce the requirement on the output swing of the operational amplifier, thereby easily realizing the design with low power consumption. The corresponding incremental zoom ADC has the advantages of IADC, and therefore, the incremental zoom ADC is more applicable to many application scenarios. As shown in fig. 2, is a conventional incremental zoom ADC architecture.
The traditional incremental zoom ADC has obvious disadvantages:
1. after the input signal passes through the coarse quantizer SAR ADC, the subsequent incremental DSM is a FIR conversion process, similar to IADC, which results in a loss of its SQNR;
the signal feed-forward path of the CIFF (feedforward integrator) structure is truncated in the loop (loop) of dsm, which still results in a large integrator output swing.
Disclosure of Invention
The purpose of the invention is as follows: the invention provides a high-precision incremental zoom ADC architecture aiming at the defects of the prior art.
In order to solve the above technical problem, the present invention discloses a high-precision incremental zoom ADC architecture, comprising: a fine incremental DSM, a coarse quantization ADC, a residual feed forward module, and an extended count module;
the residual error feedforward module is used for reconstructing signal feedforward of a CIFF structure in the fine incremental DSM and reducing the output swing of the incremental zoom ADC integrator; the input of the residual error feedforward module is the analog input VIN of the incremental type zoom ADC and the output k of the rough quantization ADC, and the residual error feedforward module outputs a feedforward signal which is used as a CIFF structure of the fine incremental DSM;
the extended counting module is used for improving the signal quantization noise ratio SQNR of the incremental zoom ADC; the input of the extended counting module is the output analog voltage of the last-stage integrator in the fine incremental DSM in the incremental mode in the last period, namely the analog quantization error of the incremental DSM in the CIFF structure, and the output is the digital value of the quantization error of the fine incremental DSM after analog-to-digital conversion.
The residual feed-forward module comprises:
inputting a signal transmission path, and establishing a digital-to-analog converter DAC2 and an addition or subtraction module according to the coarse quantization result; an input signal transmission path directly transmits the input signal VIN of the whole high-precision incremental zoom ADC; establishing a coarse quantization result by a digital-to-analog converter DAC2 and establishing a quantization result of a coarse quantization ADC; and subtracting the coarse quantization result established by the digital-to-analog converter DAC2 from the input signal VIN through an addition or subtraction module to obtain a quantization residual error of the coarse quantization ADC.
The quantization residual of the coarse quantization ADC, i.e. the coarse quantization error, is used in the subsequent fine incremental DSM, summed with the output of the integrator in the fine incremental DSM, and fed into the quantizer of the fine incremental DSM to form a complete CIFF loop.
The extended count module includes:
a gain module and a counting ADC module; wherein the gain module amplifies a fine quantization error, which is an analog quantization error of the fine incremental DSM; and the counting ADC performs analog-to-digital conversion on the amplified analog quantization error to obtain a digital value of the fine incremental DSM quantization error, and the digital value is used as the output of the expansion counting module.
And the final output of the high-precision incremental zoomADC is obtained by adding the output of the extended counting module into the original output.
Has the beneficial effects that:
the incremental zoom ADC framework provided by the invention improves the SQNR of the incremental zoom ADC, and meanwhile, an operational amplifier with low output swing can be used. High accuracy and low power consumption are better achieved.
Drawings
The foregoing and/or other advantages of the invention will become more apparent from the following detailed description of the invention when taken in conjunction with the accompanying drawings.
Fig. 1 is a schematic diagram of an incremental zoom ADC architecture according to the present invention.
Fig. 2 is a schematic diagram of a conventional incremental zoom ADC architecture.
Fig. 3 is a circuit implementation diagram of an incremental zoom ADC architecture according to an embodiment of the present invention.
FIG. 4 is a timing diagram of the circuit in one embodiment.
FIG. 5 is a diagram illustrating a comparison of simulation results between an embodiment of the architecture of the present invention and a conventional architecture.
FIG. 6 is a diagram illustrating a comparison of test results between an embodiment of the present invention and a conventional test result.
Detailed Description
As shown in fig. 2, the conventional incremental zoom ADC adopts the following scheme:
the input signal VIN is firstly quantized through a coarse quantization SAR ADC, then the subsequent fine delta-sigma modulator DSM is subjected to fine quantization, and the incremental DSM only quantizes the quantization error of the successive approximation SAR, so that the requirement on the output swing amplitude of the operational amplifier can be reduced, and the operational amplifier with low power consumption is used.
The invention uses a residual feed forward (residual feed forward) path to reconstruct the signal feed forward of the CIFF structure of the feed forward integrator and reduce the output swing of the incremental zoom ADC integrator, thereby realizing low power consumption design. Furthermore, the SQNR of the incremental zoom ADC is improved by using an extended counting (extended counting) mode, so as to achieve high precision, and the specific scheme of the high-precision incremental zoom ADC architecture provided by the invention is as follows:
as shown in fig. 1, the digital-to-analog converter DAC2 implements residual feedforward, so that a signal feedforward path in the DSM of the CIFF architecture is established, and thus the output of the second stage integrator is the quantization error of the incremental DSM. Further, the signal quantization noise ratio SQNR is improved by using the extended count, and the quantization error is quantized by one SAR after being amplified by n times (2 times). And finally, combining the result of coarse quantization SAR, the result of incremental DSM and the result of extended counting SAR to form a final digital output DOUT.
The combination process:
the result k of the coarse SAR, when used by the DSM, is selected based on the BS and k of the DSM. The selection result is determined by over range, for example, over range =1, and the value of feedback at each time is: if BS =1, feedback = k +2; if BS =0, the feedback = k-1 (over range =1 is equivalent to 1 coarse quantization interval on the basis of k to k + 1). The Over range ensures that the input is always within the reference voltage of the DSM, and ensures the stability. The output of the Zoom ADC itself is the combination of BS and k, i.e., k1-1/k1+2, k2-1/k2+2, k3-1/k3+2, k4-1/k4+2, \ 8230where i of ki denotes the output sequence order and ki-1 or ki +2 is determined from BS =0 or 1.
Therefore, the output result of the conventional incremental zoom is the conversion result obtained by passing the output sequence of zoom through a CoI (code of integrators) filter, and is denoted as Dout1.
The invention adds the extended count, records the output of the extended count ADC as y (normalized to-1- + 1), and then the extended count result Dex = y/gex 2/(a) 1 a 2 M (M-1)), where gex is the gain of the gain stage before the extended count ADC (2 in FIG. 1), a 1 a 2 Representing the product of the integrator coefficients in the DSM (0.5 and 0.33 in fig. 1), M is the over-sampling rate. (Extended counting principle refer to "A High-Resolution Low-Power increment Sigma Delta ADC With Extended Range for Biosensor Arrays")
Finally, DOUT = DOUT1+ Dex.
Example (b):
fig. 3 shows an embodiment of a specific circuit implementation of the solution of the present invention. 4b SAR as a coarse quantizer from CLK SAR1 And controlling, namely performing coarse quantization on the input signal to obtain a coarse quantization result k. Then, DAC1 in the thin DSM is composed of 16 unit capacitors C S1,j Array implementation, using k and BS in combination for feedback, achieves zoom effect. DAC2 in fine DSM as residual feed-forward by weighted C F1,j The array implementation realizes signal feedforward in a CIFF architecture, so that the fine quantization error of DSM can be directly obtained at the output of a second-stage integrator, and an addition (subtraction) module in residual feedforward is combined with an addition module in front of a quantizer in DSM and is realized by a passive capacitor adder. From CLK SAR2 The controlled 4b SAR acts as an ADC for extended counting, quantifying the fine quantization error of the DSM amplified by 2-fold gain, achieving extended counting. All integrators use a fully dynamic cascoded FIA as an operational amplifier to save power. In the first stage integrator, a chopping technique is employed to reduce the packer noise and offset, and in the second-order IADC, a fractal sequence of { +1, -1, -1, +1} is used for chopping.
This embodiment is merely an example of the implementation, in which:
1. the ADC for coarse quantization and extended counting is not necessarily a SAR ADC;
the architecture of dsm is not unique;
the order of the DSM is not unique;
the coefficients of the DSM are not unique;
the operational amplifier configuration used for dsm is not unique;
6. the gain of the gain stage before the expansion technology is not fixed to 2;
the OTAs implementing the integrators in DSM are not necessarily cascoded FIA;
the control sequence realized by the circuit is shown in fig. 4. One conversion for an incremental zoom ADC includes 256 DSM operating cycles. The DSM operates at an oversampling frequency of fs and the coarse SAR operates at a frequency of fs/4 to save power consumption. The frequency of the fractal sequence chopping is also fs/4. The extended count 2 gain stage and the extended count SAR ADC are only turned on in the last cycle of each conversion and therefore their power consumption is negligible.
As shown in fig. 5, simulation results show that, using the architecture of the present solution, SQNR =118dB of the incremental zoom ADC is improved by about 10dB compared to not using residual feed forward and spread counts.
As shown in FIG. 6, test results show that the incremental zoom ADC of the scheme realizes SNDR of 97.6dB in a 95Hz bandwidth, the power consumption is only 0.96 μ W, and high precision and extremely low power consumption are realized.
In a specific implementation, the present application provides a computer storage medium and a corresponding data processing unit, where the computer storage medium is capable of storing a computer program, and the computer program, when executed by the data processing unit, may execute the inventive content of the high-precision incremental zoom ADC architecture and some or all of the steps in the embodiments provided in the present invention. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like.
It is clear to those skilled in the art that the technical solutions in the embodiments of the present invention can be implemented by means of a computer program and its corresponding general-purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention or portions thereof that contribute to the prior art may be embodied in the form of a computer program, that is, a software product, which may be stored in a storage medium and include several instructions for enabling a device (which may be a personal computer, a server, a single chip microcomputer, an MUU, or a network device) including a data processing unit to execute the method according to the embodiments or some portions of the embodiments of the present invention.
While the present invention provides a method and a system for implementing a high-precision incremental zoom ADC architecture, and the method and system for implementing the method and system are many, the above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, many modifications and refinements can be made without departing from the principle of the present invention, and these modifications and refinements should be regarded as the protection scope of the present invention. All the components not specified in the present embodiment can be realized by the prior art.
Claims (10)
1. A high-precision incremental zoom ADC architecture, comprising: a fine incremental DSM, a coarse quantization ADC, a residual feed forward module, and an extended count module;
the residual error feedforward module is used for reconstructing signal feedforward of a CIFF structure in the fine incremental DSM and reducing the output swing of the incremental zoom ADC integrator; the input of the residual error feedforward module is the analog input VIN of the incremental type zoom ADC and the output k of the rough quantization ADC, and the residual error feedforward module outputs a feedforward signal which is used as a CIFF structure of the fine incremental DSM;
the extended counting module is used for improving the signal quantization noise ratio SQNR of the incremental zoom ADC; the input of the extended counting module is the output analog voltage of the last-stage integrator in the fine incremental DSM in the incremental mode in the last period, namely the analog quantization error of the incremental DSM in the CIFF structure, and the output is the digital value of the quantization error of the fine incremental DSM after analog-to-digital conversion.
2. A high precision incremental zoom ADC architecture according to claim 1, wherein said residual feed forward module comprises:
inputting a signal transmission path, establishing a digital-to-analog converter DAC2 and an addition or subtraction method module according to the coarse quantization result; an input signal transmission path directly transmits the input signal VIN of the whole high-precision incremental zoom ADC; establishing a coarse quantization result by a digital-to-analog converter DAC2 and establishing a quantization result of a coarse quantization ADC; and subtracting the coarse quantization result established by the digital-to-analog converter DAC2 from the input signal VIN through an addition or subtraction module to obtain a quantization residual error of the coarse quantization ADC.
3. A high precision incremental zoom ADC architecture according to claim 2, wherein the quantization residual of the coarse quantization ADC, i.e. the coarse quantization error, is used in the subsequent fine incremental DSM, summed with the output of the integrator in the fine incremental DSM, and fed into the quantizer of the fine incremental DSM to form a complete CIFF loop.
4. A high precision incremental zoom ADC architecture according to claim 3, wherein said extended count module comprises:
a gain module and a counting ADC module; wherein the gain module amplifies a fine quantization error, which is an analog quantization error of the fine incremental DSM; and the counting ADC performs analog-to-digital conversion on the amplified analog quantization error to obtain a digital value of the fine incremental DSM quantization error, and the digital value is used as the output of the expansion counting module.
5. The architecture of claim 4, wherein a final output of the high-precision incremental zoom ADC is obtained by adding an output of the extended count module to an original output.
6. A high precision incremental zoom ADC architecture according to claim 5, wherein said residual feedforward module is implemented by a capacitor array.
7. The architecture of claim 6, wherein the capacitive array is a weighted capacitive array.
8. A high accuracy incremental zoom ADC architecture as recited in claim 7, wherein the addition or subtraction module in the residual feedforward module is combined with the pre-quantizer addition module in the fine incremental DSM and implemented as a passive capacitor summer.
9. The architecture of claim 8, wherein the count ADC module of the extended count module is clocked by the clock signal CLK at the Nyquist sampling rate SAR2 Controlled 4b SAR implementation.
10. The architecture of claim 9, wherein all integrators use a fully dynamic cascode floating-inverting amplifier (cascode FIA) as an operational amplifier.
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| CN202211271724.0A CN115549683A (en) | 2022-10-18 | 2022-10-18 | High-precision incremental zoom ADC (analog to digital converter) framework |
| PCT/CN2023/108604 WO2024082739A1 (en) | 2022-10-18 | 2023-07-21 | High-precision incremental zoom adc architecture |
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| CN117040522A (en) * | 2023-10-09 | 2023-11-10 | 电子科技大学 | Full-dynamic power frequency interference suppression circuit suitable for double-electrode framework |
| WO2024082739A1 (en) * | 2022-10-18 | 2024-04-25 | 杭州万高科技股份有限公司 | High-precision incremental zoom adc architecture |
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| US7782237B2 (en) * | 2008-06-13 | 2010-08-24 | The Board Of Trustees Of The Leland Stanford Junior University | Semiconductor sensor circuit arrangement |
| KR101645571B1 (en) * | 2015-08-18 | 2016-08-04 | 연세대학교 산학협력단 | Sigma-Delta Zoom ADC by using Slope ADC with Asynchronous Reference Generation |
| KR101840683B1 (en) * | 2017-09-27 | 2018-03-21 | 포항공과대학교 산학협력단 | Sar trpe analog to digital converter using residue integration |
| CN109889199B (en) * | 2019-02-20 | 2023-03-31 | 哈尔滨工程大学 | Sigma delta type and SAR type mixed ADC with chopper stabilization |
| CN110518914A (en) * | 2019-08-19 | 2019-11-29 | 华中科技大学 | A kind of Deltasigma modulator based on time-sharing multiplex ASAR ADC |
| CN113225084B (en) * | 2021-04-16 | 2023-08-08 | 西安交通大学 | Delta-Sigma ADC structure of self-adaptive reference voltage |
| CN114285414B (en) * | 2021-12-27 | 2024-04-26 | 北京大学深圳研究生院 | Scaling type increment type analog-to-digital conversion method and converter |
| CN114421968A (en) * | 2022-03-30 | 2022-04-29 | 武汉杰开科技有限公司 | Incremental sigma delta analog-to-digital conversion method, converter and chip |
| CN115549683A (en) * | 2022-10-18 | 2022-12-30 | 杭州万高科技股份有限公司 | High-precision incremental zoom ADC (analog to digital converter) framework |
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| WO2024082739A1 (en) * | 2022-10-18 | 2024-04-25 | 杭州万高科技股份有限公司 | High-precision incremental zoom adc architecture |
| CN117040522A (en) * | 2023-10-09 | 2023-11-10 | 电子科技大学 | Full-dynamic power frequency interference suppression circuit suitable for double-electrode framework |
| CN117040522B (en) * | 2023-10-09 | 2024-01-23 | 电子科技大学 | Full-dynamic power frequency interference suppression circuit suitable for double-electrode framework |
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