JPH06109779A - Voltage comparator - Google Patents

Abstract

PURPOSE:To provide a necessary DC gain without deteriorating response speed under compact constitution using a single amplification stage by positively feeding back an output signal from a differential amplification circuit to the input side of a comparator. CONSTITUTION:Input voltage Vin and reference voltage Vre are differentially inputted to transistors M1 and M5 respectively. Also, transistors M3 and M4 become loads for the transistor M1, while transistors M7 and M8 become loads for the transistor M5. The drains of the input transistors M1 and M5 are respectively connected to a pair of transistors M1 and M2, together with the loads, thereby constituting a positive feedback circuit. Also, an external sampling signal SMPL, a reset signal RST and gate voltage signals CMP from the transistors M3 and M7 are fed to the circuit, thereby obtaining differential output from terminals +OUT and -OUT. Furthermore, sufficient DC accuracy can be ensured by suitably changing a positive feedback amount during operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage comparator suitable for use as an analog signal processing circuit such as a sampling A / D converter.

[0002]

2. Description of the Related Art As a circuit configuration of a voltage comparator (comparator), one having a circuit configuration illustrated in FIG. 3 has been widely used. The circuit of FIG. 3 is a MOS type F
The basic configuration is a cascode-connected two-stage inverting amplifier composed of ET.
Is a differential amplifier that receives the reference voltage V _ref and the input voltage V _in as differential inputs, and the output thereof is further amplified by the inverting amplifier 32 in the next stage. This circuit configuration is
This is a configuration generally used in commercially available comparator ICs and the like.

[0003]

By the way, in a comparator, in general, it is necessary to amplify a minute analog signal to a logic level.
C gain is required. However, in the circuit shown in FIG.
There is a drawback that the response speed is deteriorated when the DC gain is increased. Therefore, in such a circuit,
In order to prevent the response speed from deteriorating, it is necessary to cascode-connect many stages of amplification stages in which the DC gain is set low, which causes an increase in chip area and power consumption. Also, by providing multiple amplification stages, the delay in each stage will be accumulated,
There is a limit to the speed of response.

An object of the present invention is to provide a voltage comparator which can obtain a necessary DC gain and has a high response speed in a compact structure using a single amplification stage.

[0005]

In order to achieve the above object, a voltage comparator of the present invention provides an amplifier circuit for differentially amplifying and outputting a differentially input signal, and an output signal of the amplifier circuit. It is characterized by including circuit means for positively feeding back to the input side and circuit means for variably controlling the amount of feedback.

[0006]

By performing the amplification by the positive feedback, even a single stage amplifier can be sufficiently amplified and the response speed is not deteriorated. Further, by appropriately changing the positive feedback amount during the operation, it becomes possible to secure sufficient DC accuracy.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram of an embodiment of the present invention, showing an example in which a MOS type FET is used as a circuit element.

M1 and M5 are respectively the input voltage V _in
And an input transistor for differentially inputting the reference voltage V _ref . Further, M3 and M4 serve as the load of the transistor M1, and M7 and M8 serve as the load of the transistor M5.

The equivalent resistance value formed by M3 and M4 is variable depending on the gate voltage of M3, and takes the minimum value when the signal CMP supplied from the outside is at L level, Becomes infinite when is at H level. This also applies to M7 and M8,
When the signal CMP supplied as the gate signal of M7 changes from the L level to the H level, the transistor M
The load resistance value of 5 changes from the minimum value to infinity.

The drains of the input transistors M1 and M5 are connected to the pair of transistors M2 and M6 together with the above-mentioned loads, and the pair of M2 and M6 constitutes a positive feedback circuit. With this configuration, in the differential amplifier circuit configured mainly with the transistors M1 and M5, the differential amplification result of the input voltage V _in and the reference voltage V _ref is positively fed back under the gain based on the level of the signal CMP. Will be done.

In such a configuration, the transistor M
Taking the 1 side as an example, the transconductance of M1 is g
The transconductance of m ₁ and M2 is gm ₂ , M3 and M4
When the resistance value of the load constituted by is R, the gain of the input signal to M1 can be expressed as G = gm ₁ R / (1-gm ₂ ² R ² ) ... (1). That is, the gain increases as the value of gm ₂ R approaches 1, the gain becomes infinite when gm ₂ R = 1, and when gm ₂ R> 1, it operates as a latch.

In this embodiment, the transistor M1
And M5 are provided with sampling switches S1a and S1b which are opened and closed in synchronization with each other by a sampling signal SMPL supplied from the outside and capacitors Ca and Cb, and M1 and M5.
The reset switches S2a and S2b, which are opened and closed by the reset signal RST having a phase opposite to the sampling signal, are provided between the gate and the drain of the.

Then, the sampling signal SMPL and the reset signal RS are externally applied at the following timings.
By supplying T and the gate voltage signal CMP of the transistors M1 and M5 described above, + and -O
A differential output is obtained from the UT terminal.

FIG. 2 is a time chart showing the signal states of the respective parts of the embodiment of the present invention. The operation will be described below with reference to this figure. Reset signal RS supplied from the outside
T and sampling signal SMPL signal are alternately H in cycle T
And L are repeated. For one cycle, first, the reset signal RST =
Starting from the H state, the circuit is in the reset state during this period.

Next, the reset signal RST = L and the sampling signal SMPL = H are set to activate the circuit, and the reference voltage V _ref and the input voltage V _in are sampled via the capacitors Ca and Cb, respectively. The difference V _in -V _ref of both the input signal is amplified with an amplification factor of (1), appearing in the differential output from ± OUT terminal. here,
The CMP signal is synchronized with the sampling signal SMPL,
It is a signal whose voltage value gradually increases from the time of rising of the signal SMPL to the sampling signal SMP.
At the beginning of the rise of L, gm ₂ R in (1) is 1 or less, and this gm ₂ R is set to exceed 1 after passing through 1. By this signal CMP, the sampling signal SMPL
The gain G has a small value at the beginning of the rise of the signal, but after that, gm ₂ R gradually increases and the gain G becomes infinite and then latched. Therefore, by extracting the signal appearing at the differential output ± OUT terminals in this latched state as a comparison result, a large amplification factor and
A comparison result with sufficient DC accuracy can be obtained.

In the above embodiment, M is used as the circuit element.
Although the OS type FET is used, it goes without saying that a junction type transistor may be used in place of this.

[0017]

As described above, according to the present invention,
Amplification is performed by positively feeding back the differential output signal of the amplifier circuit that differentially inputs and amplifies the input voltage and the reference voltage, so even a single-stage amplifier can sufficiently amplify to the logic level. In addition, the response speed is not deteriorated, and the positive feedback amount is appropriately changed during the operation, so that sufficient DC accuracy can be secured. As a result, it is possible to obtain a high-sensitivity voltage comparator with a compact structure that can obtain a logic level comparison result with a fast response speed and a small offset voltage.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention.

FIG. 2 is a time chart showing the state of signals of each part.

FIG. 3 is a circuit configuration diagram showing a configuration example of a conventional general voltage comparator.

[Explanation of symbols]

 M1, M5 input transistor M2, M6 positive feedback signal forming transistor M3, M4 transistor M1 load M7, M8 transistor M5 load S1a, S1b sampling switch S2a, S2b reset switch

Claims (1)

[Claims] 1. An amplifier circuit for differentially amplifying and outputting a differentially input signal, a circuit means for positively feeding back an output signal of the amplifier circuit to an input side, and a circuit means for variably controlling the feedback amount. A voltage comparator provided.