CN116781047B - Comparator suitable for Gao domain - Google Patents
Comparator suitable for Gao domain Download PDFInfo
- Publication number
- CN116781047B CN116781047B CN202310971207.2A CN202310971207A CN116781047B CN 116781047 B CN116781047 B CN 116781047B CN 202310971207 A CN202310971207 A CN 202310971207A CN 116781047 B CN116781047 B CN 116781047B
- Authority
- CN
- China
- Prior art keywords
- tube
- input
- nmos tube
- nmos
- pmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000003044 adaptive effect Effects 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims description 49
- 239000000758 substrate Substances 0.000 claims description 14
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
Abstract
The present invention relates to a comparator, and more particularly, to a comparator suitable for a high-voltage domain. According to the technical scheme provided by the invention, the comparator suitable for Gao domain comprises: the comparator body comprises an input pair pipe and a load unit which is connected with the input pair pipe IN an adapting way, wherein the input pair pipe is used for receiving an input signal IN1 and an input signal IN2 to be compared; the voltage limiting protection unit group comprises a plurality of voltage limiting protection units used for limiting and protecting input pair pipes, wherein the voltage limiting protection units in the voltage limiting protection unit group are in one-to-one correspondence and are connected with the input pipes in the input pair pipes in an adaptive mode, and the voltage limiting protection units are used for limiting the grid source voltage of the connected input pipes to be not higher than the withstand voltage value of the input pipes. The invention is suitable for the comparison of high-pressure regions and improves the comparison precision and reliability of the comparator.
Description
Technical Field
The present invention relates to a comparator, and more particularly, to a comparator suitable for a high-voltage domain.
Background
The comparator is an analog circuit with very wide application, and the working principle is to compare the magnitudes of two input signals and express the comparison result by outputting high and low levels. Comparators can be broadly divided into current comparators and voltage comparators, with voltage comparators being the most common.
The voltage comparator is generally applied to an analog-digital conversion circuit, a power supply voltage protection circuit, an oscillator circuit and the like, and indexes such as offset, hysteresis, speed, power consumption and the like need to be considered in circuit design. For the design of the high voltage domain comparator, attention is also paid to the voltage withstand capability of the circuit. In the current comparator circuit based on the CMOS process, the voltage withstand between the gate and the source of the field effect transistor is smaller, which makes the design of the high voltage comparator difficult.
The circuit structure of the conventional comparator is shown IN fig. 1, IN which the high voltage input signal IN1 and the input signal IN2 are divided by the resistors R1 to R4, and then the voltage signal V1 and the voltage signal V2 after the voltage reduction are connected to the input terminal of the comparator U1 respectively. The ratio of the resistor R1 to the resistor R3 is equal to the ratio of the resistor R2 to the resistor R4, and thus the ratio of the voltage signal V1 to the input signal IN1 is equal to the ratio of the voltage signal V2 to the input signal IN2.
When IN operation, if the input signal IN1 is greater than the input signal IN2, the voltage signal V1 is greater than the voltage signal V2, and the comparator U1 outputs a low level; if the input signal IN1 is smaller than the input signal IN2, the voltage signal V1 is smaller than the voltage signal V2, and the comparator U1 outputs a high level.
For the comparator circuit of fig. 1, only four resistors and one low-voltage domain comparator U1 are needed to realize the comparison processing of two high-voltage signals, and the structure is simple and easy to realize. However, since this circuit adopts the resistor voltage division method, a leakage current (a current is generated IN the resistor by the input signal IN1 and the input signal IN2 being both voltage signals), and IN order to reduce the leakage current, the resistor is usually designed to be very large, which leads to an increase IN the circuit area.
In addition, the voltage reduction processing is performed by means of resistor voltage division, so that the linearity of the input signal is deteriorated due to resistor mismatch and noise, and the comparison result is inaccurate.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a comparator suitable for a high-pressure domain, which can be suitable for comparison of the high-pressure domain and improves the comparison precision and reliability of the comparator.
According to the technical scheme provided by the invention, the comparator suitable for Gao domain comprises:
the comparator body comprises an input pair pipe and a load unit which is connected with the input pair pipe IN an adapting way, wherein the input pair pipe is used for receiving an input signal IN1 and an input signal IN2 to be compared;
the voltage limiting protection unit group comprises a plurality of voltage limiting protection units used for limiting and protecting input pair pipes, wherein the voltage limiting protection units in the voltage limiting protection unit group are in one-to-one correspondence with the input pipes in the input pair pipes and are connected in an adaptive manner, so that the voltage of the grid source of the connected input pipe is limited to be not higher than the withstand voltage value of the input pipe by the voltage limiting protection units;
the voltage limiting protection unit comprises two voltage limiting isolation type NMOS (N-channel metal oxide semiconductor) tubes which are sequentially connected in series, wherein the two voltage limiting isolation type NOMS tubes which are sequentially connected in series comprise a first voltage limiting isolation type NMOS tube and a second voltage limiting isolation type NMOS tube;
the gate terminal and the drain terminal of the first voltage limiting isolation type NMOS tube are connected with the gate terminal of the corresponding input tube, the substrate and the source terminal of the first voltage limiting isolation type NMOS tube are connected with the gate terminal and the drain terminal of the second voltage limiting isolation type NMOS tube, and the substrate and the source terminal of the second voltage limiting isolation type NMOS tube are connected with the source terminal of the corresponding input tube.
The voltage limiting protection unit also comprises a leakage protection NMOS tube, wherein the grid end, the source end and the substrate of the leakage protection NMOS tube are connected with the source end of the second voltage limiting isolation NMOS tube and the substrate of the second voltage limiting isolation NMOS tube;
the drain end of the leakage protection NMOS tube is connected with the source end of the input tube corresponding to the voltage limiting protection unit.
And the grid end of each input tube IN the input pair tube is connected with a current limiting resistor, and the grid end of the input tube receives an input signal IN1 or an input signal IN2 by using the connected current limiting resistor so as to perform current limiting protection on the voltage limiting protection unit by using the current limiting resistor.
The comparator body also includes a bias current unit for providing an operating current, wherein,
the bias current unit comprises a current source Iref and a current mirror which is connected with the current source Iref in an adapting way, and the current source Iref is connected with the source end of an input tube in the input pair tube in an adapting way through the current mirror.
The current mirror comprises a PMOS tube M5 and a PMOS tube M6, wherein,
the gate end of the PMOS tube M5, the gate end of the PMOS tube M6 and the drain end of the PMOS tube M6 are grounded through a current source Iref, the source end of the PMOS tube M6 and the source end of the PMOS tube M5 are connected with a power supply VDD, and the drain end of the PMOS tube M5 is adaptively connected with the source end of an input tube in the input pair tube and the voltage limiting protection unit.
The input pair tube comprises a PMOS input tube M1 and a PMOS input tube M2, and the source end of the PMOS input tube M1 is connected with the source end of the PMOS input tube M2;
the load unit comprises an NMOS tube M3 and an NMOS tube M4, wherein the gate end of the NMOS tube M3, the drain end of the NMOS tube M3 and the gate end of the NMOS tube M4 are connected with the drain end of the PMOS input tube M1, and the drain end of the NMOS tube M4 is connected with the drain end of the PMOS input tube M2 and forms an output end OUT of the comparator body;
the source terminal of the NMOS transistor M3 is grounded, and the source terminal of the NMOS transistor M4 is grounded.
The input pair tube comprises a PMOS input tube M1 and a PMOS input tube M2, and the source end of the PMOS input tube M1 is connected with the source end of the PMOS input tube M2;
the load unit comprises an NMOS tube M7, an NMOS tube M8, an NMOS tube M9 and an NMOS tube M10, wherein,
the drain end of the NMOS tube M7 is connected with the gate end of the NMOS tube M7, the gate end of the NMOS tube M9, the drain end of the NMOS tube M10 and the drain end of the PMOS input tube M1, and a differential output end OUT1 is formed;
the drain terminal of the NMOS tube M8 is connected with the gate terminal of the NMOS tube M8, the gate terminal of the NMOS tube M10, the drain terminal of the NMOS tube M9 and the drain terminal of the PMO input tube M2, and a differential output end OUT2 is formed;
the source terminal of NMOS tube M7, the source terminal of NMOS tube M8, the source terminal of NMOS tube M9 and the source terminal of NMOS tube M10 are all grounded.
The corresponding conducting channel width-to-length ratios of the NMOS tube M7, the NMOS tube M8, the NMOS tube M9 and the NMOS tube M10 are the same.
The invention has the advantages that: and for the input tube in the input pair tube, a voltage limiting protection unit is utilized to be connected with the source end of the input tube and the gate end of the input tube in an adaptive manner, so that the gate-source voltage of the connected input tube is limited to be not more than the withstand voltage value of the input tube by utilizing the voltage limiting isolation type NMOS tubes which are sequentially connected in series in the voltage limiting protection unit.
When the voltage limiting isolation type NMOS tube connected in series in the voltage limiting protection unit is conducted, the input tube can be in a self-protection state through the matching of the leakage protection NMOS tube and the voltage limiting isolation type NMOS tube.
The NMOS active load with positive feedback is used as a load unit, so that on one hand, the gain of the comparator can be increased, and the precision of the comparator can be further improved, on the other hand, because the NMOS active load is a low-impedance active load, the voltage on the active load is smaller when the power supply of the comparator is in a high-voltage domain, the load cannot be damaged by high voltage, namely, the comparator can be suitable for the comparison of the high-voltage domain, and the comparison precision and reliability of the comparator can be improved.
Drawings
Fig. 1 is a schematic diagram of an embodiment of a conventional voltage comparator.
FIG. 2 is a schematic diagram of a comparator according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of another embodiment of the comparator of the present invention.
Fig. 4 is a schematic diagram of a third embodiment of the comparator of the present invention.
Detailed Description
The invention will be further described with reference to the following specific drawings and examples.
In order to improve the comparison accuracy and reliability of the comparator, for the comparator suitable for Gao domain, in one embodiment of the present invention, the comparator comprises:
the comparator body comprises an input pair pipe and a load unit which is connected with the input pair pipe IN an adapting way, wherein the input pair pipe is used for receiving an input signal IN1 and an input signal IN2 to be compared;
the voltage limiting protection unit group comprises a plurality of voltage limiting protection units used for limiting and protecting input pair pipes, wherein the voltage limiting protection units in the voltage limiting protection unit group are in one-to-one correspondence with the input pipes in the input pair pipes and are connected in an adaptive manner, so that the voltage of the grid source of the connected input pipe is limited to be not higher than the withstand voltage value of the input pipe by the voltage limiting protection units;
the voltage limiting protection unit comprises two voltage limiting isolation type NMOS (N-channel metal oxide semiconductor) tubes which are sequentially connected in series, wherein the two voltage limiting isolation type NOMS tubes which are sequentially connected in series comprise a first voltage limiting isolation type NMOS tube and a second voltage limiting isolation type NMOS tube;
the gate terminal and the drain terminal of the first voltage limiting isolation type NMOS tube are connected with the gate terminal of the corresponding input tube, the substrate and the source terminal of the first voltage limiting isolation type NMOS tube are connected with the gate terminal and the drain terminal of the second voltage limiting isolation type NMOS tube, and the substrate and the source terminal of the second voltage limiting isolation type NMOS tube are connected with the source terminal of the corresponding input tube.
Specifically, the comparator body is a circuit capable of implementing a comparison function, and generally, the comparator body includes an input pair tube and a load unit adaptively connected to the input pair tube, and the input pair tube is used for receiving an input signal IN1 and an input signal IN2 to be compared, and as can be seen from the above description, the input signal IN1 and the input signal IN2 may be voltage signals.
Fig. 2 to 4 show an embodiment of an input pair tube, in which the input pair tube includes a PMOS input tube M1 and a PMOS input tube M2, that is, the PMOS input tube M1 and the PMOS input tube M2 are two input tubes in the input pair tube. The source terminal of the PMOS input tube M1 is connected to the source terminal of the PMOS input tube M2, the input signal IN1 is received by the gate terminal of the PMOS input tube M1, and the input signal IN2 is received by the gate terminal of the PMOS input tube M2. Of course, IN the implementation, other implementation forms of the input pair tube may be adopted, and may be specifically selected according to needs, so as to satisfy the receiving and comparing of the input signals IN1 and IN2.
As known to those skilled IN the art, when the input signal IN1 is far greater than the input signal IN2, the gate-source voltage of the PMOS input tube M1 will be so great that the PMOS input tube M1 will be damaged; alternatively, when the input signal IN2 is far greater than the input signal IN1, the gate-source voltage of the PMOS input transistor M2 may be so great that the PMOS input transistor M2 may be damaged. Here, the gate-source voltage of the PMOS input tube M1 specifically refers to a difference between the gate terminal of the PMOS input tube M1 and the voltage of the source terminal of the PMOS input tube M1, and the specific condition of the gate-source voltage of the PMOS input tube M2 is consistent with the condition of the gate-source voltage of the PMOS input tube M1.
IN order to avoid the damage of the PMOS input tube M1 and the PMOS input tube M2 IN the input pair tube caused by the input signal and the input signal IN2, IN one embodiment of the present invention, at least one voltage limiting protection unit is used to limit the voltage of the input tube IN the input pair tube, for example, at least one voltage limiting protection unit is used to limit the voltage of the PMOS input tube M1, and at the same time, one voltage limiting protection unit is used to limit the voltage of the PMOS input tube M2.
The number of the voltage limiting protection units in the voltage limiting protection unit group is generally two, the two voltage limiting protection units are respectively correspondingly and adaptively connected with the PMOS input tube M1 and the PMOS input tube M2, at the moment, the grid source voltage of the PMOS input tube can be limited to be not higher than the withstand voltage value of the PMOS input tube M1 by utilizing the voltage limiting protection units corresponding to the PMOS input tube M1, the purpose of protecting the PMOS input tube M1 is achieved by limiting the voltage of the voltage limiting protection units, and the voltage limiting protection condition of the PMOS input tube M2 can be described by referring to the PMOS input tube M1.
When the number of the voltage limiting protection units in the voltage limiting protection unit group is more than two, at least two voltage limiting protection units are selected to be respectively connected with the PMOS input tube M1 and the PMOS input tube M2 in an adaptive manner, and the specific adaptive connection condition can be referred to the above description. The rest voltage limiting protection units can be matched with the PMOS input tube M1 or the PMOS input tube M2 by adopting the same connection, and at the moment, the voltage limiting protection units distributed in parallel exist. Generally, the number of the voltage limiting protection units in the voltage limiting protection unit group is preferably two, that is, the voltage limiting protection units are correspondingly and adaptively connected with the PMOS input tube M1 and the PMOS input tube M2 respectively.
In addition, the withstand voltage value of the PMOS input tube M1 and the withstand voltage value of the PMOS input tube M2 can be generally determined according to the characteristic parameters of the PMOS input tube, and after the PMOS input tube M1 and the PMOS input tube M2 are selected, the corresponding voltage limiting protection unit can be selected so as to protect the PMOS input tube M1 and the PMOS input tube M2, thereby improving the reliability of the comparator during operation.
In one embodiment of the invention, each voltage limiting protection unit adopts the same form, namely at least comprises two voltage limiting isolation type NMOS (N-channel metal oxide semiconductor) tubes which are sequentially connected in series, and the two voltage limiting isolation type NMOS tubes are connected in series to clamp the gate-source voltage of the corresponding input tube. The two voltage limiting isolation type NMOS tubes are connected in series in sequence, namely a first voltage limiting isolation type NMOS tube and a second voltage limiting isolation type NMOS tube, namely the first voltage limiting isolation type NMOS tube and the second voltage limiting isolation type NMOS tube are connected in series to form a voltage limiting protection unit.
Fig. 2, fig. 3 and fig. 4 show an embodiment in which two voltage limiting isolation type NMOS tubes are sequentially connected in series by using a voltage limiting protection unit, and of course, a plurality of voltage limiting isolation type NMOS tubes may be further included in the voltage limiting protection unit.
In fig. 2 and 3, when the input pipes in the input pair pipe are the PMOS input pipe M1 and the PMOS input pipe M2, respectively, the voltage limiting protection unit corresponding to the PMOS input pipe M1 includes an NMOS pipe Mn1 and an NMOS pipe Mn2, and at this time, a first voltage limiting isolation type NMOS pipe is formed by using the NMOS pipe Mn1, and a second voltage limiting isolation type NMOS pipe is formed by using the NMOS pipe Mn 2. Meanwhile, the voltage limiting protection unit corresponding to the PMOS tube input tube M2 comprises an NMOS tube Mn3 and an NMOS tube Mn4, wherein the NMOS tube Mn3 is utilized to form a first voltage limiting isolation type NMOS tube, and the NMOS tube Mn4 is utilized to form a second voltage limiting isolation type NMOS tube.
The connection forms of the NMOS transistors Mn1, mn2, mn3, and Mn4 and the PMOS input transistors M1, M2 may refer to the description of the voltage limiting protection unit and the diagrams of fig. 2 to 4.
In one embodiment of the invention, the comparator body further comprises a bias current unit for providing an operating current, wherein,
the bias current unit comprises a current source Iref and a current mirror which is connected with the current source Iref in an adapting way, and the current source Iref is connected with the source end of an input tube in the input pair tube in an adapting way through the current mirror.
Also shown in fig. 2 is the coupling of the bias current cell to the input pair of tubes in the comparator body with which the operating current of the entire comparator can be provided. In fig. 2, the current mirror includes a PMOS transistor M5 and a PMOS transistor M6, wherein,
the gate end of the PMOS tube M5, the gate end of the PMOS tube M6 and the drain end of the PMOS tube M6 are grounded through a current source Iref, the source end of the PMOS tube M6 and the source end of the PMOS tube M5 are connected with a power supply VDD, and the drain end of the PMOS tube M5 is adaptively connected with the source end of an input tube in the input pair tube and the voltage limiting protection unit.
In practice, the current provided by the current source Iref can be selected according to the requirement. When the comparator is used in a high-voltage domain, the power supply VDD is specifically used as a high-voltage power supply, generally, the voltage range of the high voltage provided by the power supply VDD can be 10V-30V, and the voltage range provided by the power supply VDD can be selected according to the needs, so that the application scene requirement of the comparator can be met.
In fig. 2, the drain terminal of the PMOS transistor M5 is connected to the source terminal of the PMOS transistor M1, the source terminal of the PMOS transistor M2, the source terminal of the NMOS transistor Mn2, the substrate of the NMOS transistor Mn2, the source terminal of the NMOS transistor Mn4, and the substrate of the NMOS transistor Mn 4.
In addition, fig. 2 shows an embodiment of the load unit, specifically, the load unit includes an NMOS transistor M3 and an NMOS transistor M4, where a gate terminal of the NMOS transistor M3, a drain terminal of the NMOS transistor M3, a gate terminal of the NMOS transistor M4 are connected to a drain terminal of the PMOS input transistor M1, and a drain terminal of the NMOS transistor M4 is connected to a drain terminal of the PMOS input transistor M2, and forms an output terminal OUT of the comparator body;
the source terminal of the NMOS transistor M3 is grounded, and the source terminal of the NMOS transistor M4 is grounded.
As can be seen from the above description and the circuit form of the comparator in fig. 2, the comparator in fig. 2 does not have a resistor voltage division, and thus no leakage and no risk of signal distortion occur at the resistor voltage division. The NMOS tube Mn1 and the NMOS tube Mn2 are utilized to carry out voltage limiting protection on the PMOS input tube M1, the NMOS tube Mn3 and the NMOS tube Mn4 are utilized to carry out voltage limiting protection on the PMOS input tube M2, and the reliability of the comparator during operation is improved.
IN the comparator IN fig. 2, when the input signal IN1 is far greater than the input signal IN2, the gate-source voltage difference of the PMOS input tube M1 is very large, the NMOS tube Mn1 and the NMOS tube Mn2 are both IN the on state, the gate-source voltage difference of the PMOS input tube M1 is clamped based on the characteristics of the MOS tubes, and the clamping voltage formed by connecting the NMOS tube Mn1 and the NMOS tube Mn2 IN series is less than the voltage-withstanding value of the PMOS tube M1, so that the voltage-limiting protection of the PMOS input tube M1 can be realized. Similarly, when the input signal IN2 is far greater than the input signal IN1, the PMOS input tube M2 is protected by the NMOS tube Mn3 and the NMOS tube Mn4, and the PMOS input tube M2 is protected by the NMOS tube Mn3 and the NMOS tube Mn4, which can refer to the voltage limiting protection description of the PMOS input tube M1 by the NMOS tube Mn1 and the NMOS tube Mn 2.
As can be seen from the above description, the power supply VDD can provide a high voltage, and the provided voltage is greater than the withstand voltage corresponding to the low voltage NMOS transistor M3 and the NMOS transistor M4, while the drain terminals corresponding to the NMOS transistor M3 and the NMOS transistor M4 are respectively connected to the drain terminals corresponding to the PMOS input transistor M1 and the PMOS input transistor M2, the voltage of the power supply VDD is divided into a part of voltages by the PMOS transistor M5, the PMOS input transistor M1 and the PMOS input transistor M2, but the drain terminal of the NMOS transistor M4 is a high-resistance node, and the current may still generate an excessively high voltage through the high-resistance node, that is, the NMOS transistor M4 may be broken down.
In order to improve the reliability of the operation of the load circuit and improve the comparison precision of the comparator, in one embodiment of the present invention, the load unit includes an NMOS transistor M7, an NMOS transistor M8, an NMOS transistor M9, and an NMOS transistor M10, wherein,
the drain end of the NMOS tube M7 is connected with the gate end of the NMOS tube M7, the gate end of the NMOS tube M9, the drain end of the NMOS tube M10 and the drain end of the PMOS input tube M1, and a differential output end OUT1 is formed;
the drain terminal of the NMOS tube M8 is connected with the gate terminal of the NMOS tube M8, the gate terminal of the NMOS tube M10, the drain terminal of the NMOS tube M9 and the drain terminal of the PMO input tube M2, and a differential output end OUT2 is formed;
the source terminal of NMOS tube M7, the source terminal of NMOS tube M8, the source terminal of NMOS tube M9 and the source terminal of NMOS tube M10 are all grounded.
Fig. 3 and fig. 4 show another embodiment of the load unit in the case of using the same input pair tube, where the load unit is an NMOS active load with positive feedback, in the drawing, the drain end of the NMOS tube M9 and the drain end of the NMOS tube M10 are low-resistance nodes, and since the NMOS tube M7 and the NMOS tube M8 are all connected by diodes (the gates are connected with the drains), the high output impedance of the NMOS tube M10 is still parallel to the low output impedance of the NMOS tube M7 or still is low output impedance, and the high output impedance of the NMOS tube M9 is also parallel to the low output impedance of the NMOS tube M8, so that it can be ensured that the NMOS tube M7, the NMOS tube M8, the NMOS tube M9 and the NMOS tube M10 cannot be damaged by breakdown during operation.
In addition, as a load for the comparator, the cross-coupled NMOS transistor M9 and NMOS transistor M10 provide a negative output impedance of-2/gm 9,10 (NMOS tube M9 and NMOS tube M10 have the same conducting channel width to length ratio and gm 9 ＝gm 10 ＝gm 9,10 ) While NMOS transistors M7 and M8 provide a positive output impedance of 2/gm 7,8 (NMOS tube M7 and NMOS tube M8 have the same conducting channel width to length ratio and gm 7 ＝gm 8 ＝gm 7,8 ) When the corresponding conducting channel width-to-length ratios of the NMOS tube M7, the NMOS tube M8, the NMOS tube M9 and the NMOS tube M10 are the same, the output impedance is very large, and the precision of the comparator can be further improved. Specifically, gm is the transconductance of NMOS transistors, e.g., gm 9 For the transconductance of the NMOS transistor M9, reference may be made to the explanation of the NOMS transistor M9 for other cases, which will not be repeated here.
For the comparator IN fig. 3, when the gate voltage of the PMOS input transistor M1 is smaller than the source voltage of the PMOS input transistor M1, the NMOS transistor Mn1 and the NMOS transistor Mn2 are both IN the on state, which causes the current flowing through the NMOS transistors Mn1 and Mn2 to flow to the input signal IN2, thereby disturbing the input signal IN2.
Similarly, when the gate voltage of the PMOS input transistor M2 is smaller than the source voltage of the PMOS input transistor M2, the NMOS transistor Mn3 and the NMOS transistor Mn4 are both IN the on state, which causes the current flowing through the NMOS transistors Mn3 and Mn4 to flow to the input signal IN1, thereby disturbing the input signal IN1. In addition, when the voltage limiting isolation type NMOS tubes in the voltage limiting protection unit are all conducted, the conducted current may burn the voltage limiting isolation type NMOS tubes in the voltage limiting protection unit.
IN order to prevent leakage interference to the input signals IN1 and IN2, IN one embodiment of the present invention, the voltage limiting protection unit further includes a leakage protection NMOS, where a gate end, a source end and a substrate of the leakage protection NMOS are connected to a source end of a second voltage limiting isolation NMOS and a substrate of the second voltage limiting isolation NMOS;
the drain end of the leakage protection NMOS tube is connected with the source end of the input tube corresponding to the voltage limiting protection unit.
In the implementation, each voltage limiting protection unit at least comprises one leakage protection NMOS tube, and specifically, the leakage protection NMOS tube and the voltage limiting protection NMOS tube can adopt the same device form. Fig. 4 shows an embodiment of a leakage protection NMOS, in which the leakage protection NMOS in the voltage limiting protection unit where the NMOS Mn1 is located is an NMOS Mn5, the leakage protection NMOS in the voltage limiting protection where the NMOS Mn3 is located is an NMOS Mn6, and connection forms between the NMOS Mn5, the NMOS Mn6 and the input pipe in the input pair and the voltage limiting isolation NMOS in the voltage limiting protection unit are referred to the above description and the example of fig. 4.
IN fig. 4, the gate terminal of the PMOS input tube M1 is connected to one end of the current limiting resistor R5, the other end of the current limiting resistor R5 receives the input signal IN1, the gate terminal of the PMOS input tube M2 is connected to one end of the current limiting resistor R6, and the other end of the current limiting resistor R6 receives the input signal IN2. The resistance values of the current limiting resistor R5 and the current limiting resistor R6 can be selected according to the requirement, so that the required current limiting can be avoided.
For the comparator shown IN fig. 4, when the input signal IN1 is far greater than the input signal IN2, the voltage difference between the gate and the source of the PMOS input tube M1 is relatively large, at this time, the gate voltage of the PMOS input tube M1 is far greater than the source voltage, and the NMOS tube Mn1, the NMOS tube Mn2, and the NMOS tube Mn5 are all IN the on state, so that the gate-source voltage of the PMOS input tube M1 is clamped, thereby protecting the PMOS input tube M1 from being damaged by high voltage. Meanwhile, the NMOS tube Mn3 and the NMOS tube Mn4 are also in a conducting state, but the NMOS tube Mn6 is in a cutting-off state, a current path from the source electrode of the PMOS input tube M2 to the grid electrode is cut off, current generated by conducting the NMOS tube Mn1, the NMOS tube Mn2 and the NMOS tube Mn5 does not flow to the grid electrode of the PMOS input tube M2, and the current on the PMOS tube M5 flow to the ground through the channel of the PMOS input tube M2, and the PMOS input tube M2 is in a self-protection state.
When the input signal IN2 is far greater than the input signal IN1, the gate-source voltage difference of the PMOS input tube M2 is relatively large, and at this time, the gate voltage of the PMOS input tube M2 is far greater than the source voltage of the PMOS input tube M2, and the NMOS tube Mn3, the NMOS tube Mn4, and the NMOS tube Mn6 are all IN a conductive state, so that the gate source of the PMOS input tube M2 is clamped, thereby protecting the PMOS input tube M2 from being damaged by high voltage. Meanwhile, the NMOS tube Mn1 and the NMOS tube Mn2 are in a conducting state, the NMOS tube Mn5 is in a cutting-off state, a current path from the source electrode to the grid electrode of the PMOS input tube M1 is cut off, currents generated by conducting the NMOS tube Mn3, the NMOS tube Mn4 and the NMOS tube Mn6 cannot flow to the grid electrode of the PMOS input tube M1, and the currents on the PMOS tube M5 flow to the ground through the channel of the PMOS input tube M1, so that the PMOS input tube M1 is in a self-protection state.
When the difference between the input signal IN1 and the input signal IN2 is not large, weak leakage current exists IN the voltage limiting protection unit, that is, weak leakage current passes through the NMOS transistor Mn1, the NMOS transistor Mn2 and the NMOS transistor Mn5, and weak leakage current passes through the NMOS transistor Mn3, the NMOS transistor Mn4 and the NMOS transistor Mn 6.
Claims (8)
1. A comparator adapted for a high-voltage domain, the comparator comprising:
the comparator body comprises an input pair pipe and a load unit which is connected with the input pair pipe IN an adapting way, wherein the input pair pipe is used for receiving an input signal IN1 and an input signal IN2 to be compared;
the voltage limiting protection unit group comprises a plurality of voltage limiting protection units used for limiting and protecting input pair pipes, wherein the voltage limiting protection units in the voltage limiting protection unit group are in one-to-one correspondence with the input pipes in the input pair pipes and are connected in an adaptive manner, so that the voltage of the grid source of the connected input pipe is limited to be not higher than the withstand voltage value of the input pipe by the voltage limiting protection units;
the voltage limiting protection unit comprises two voltage limiting isolation type NMOS (N-channel metal oxide semiconductor) tubes which are sequentially connected in series, wherein the two voltage limiting isolation type NOMS tubes which are sequentially connected in series comprise a first voltage limiting isolation type NMOS tube and a second voltage limiting isolation type NMOS tube;
the gate terminal and the drain terminal of the first voltage limiting isolation type NMOS tube are connected with the gate terminal of the corresponding input tube, the substrate and the source terminal of the first voltage limiting isolation type NMOS tube are connected with the gate terminal and the drain terminal of the second voltage limiting isolation type NMOS tube, and the substrate and the source terminal of the second voltage limiting isolation type NMOS tube are connected with the source terminal of the corresponding input tube.
2. The comparator for Gao domain as claimed in claim 1, wherein: the voltage limiting protection unit also comprises a leakage protection NMOS tube, wherein the grid end, the source end and the substrate of the leakage protection NMOS tube are connected with the source end of the second voltage limiting isolation NMOS tube and the substrate of the second voltage limiting isolation NMOS tube;
the drain end of the leakage protection NMOS tube is connected with the source end of the input tube corresponding to the voltage limiting protection unit.
3. The comparator for Gao domain as claimed in claim 1, wherein: and the grid end of each input tube IN the input pair tube is connected with a current limiting resistor, and the grid end of the input tube receives an input signal IN1 or an input signal IN2 by using the connected current limiting resistor so as to perform current limiting protection on the voltage limiting protection unit by using the current limiting resistor.
4. The comparator for Gao domain as claimed in claim 1, wherein: the comparator body also includes a bias current unit for providing an operating current, wherein,
the bias current unit comprises a current source Iref and a current mirror which is connected with the current source Iref in an adapting way, and the current source Iref is connected with the source end of an input tube in the input pair tube in an adapting way through the current mirror.
5. The comparator for Gao domain as claimed in claim 4, wherein: the current mirror comprises a PMOS tube M5 and a PMOS tube M6, wherein,
the gate end of the PMOS tube M5, the gate end of the PMOS tube M6 and the drain end of the PMOS tube M6 are grounded through a current source Iref, the source end of the PMOS tube M6 and the source end of the PMOS tube M5 are connected with a power supply VDD, and the drain end of the PMOS tube M5 is adaptively connected with the source end of an input tube in the input pair tube and the voltage limiting protection unit.
6. A comparator for Gao domain according to any one of claims 1 to 4, characterised in that: the input pair tube comprises a PMOS input tube M1 and a PMOS input tube M2, and the source end of the PMOS input tube M1 is connected with the source end of the PMOS input tube M2;
the load unit comprises an NMOS tube M3 and an NMOS tube M4, wherein the gate end of the NMOS tube M3, the drain end of the NMOS tube M3 and the gate end of the NMOS tube M4 are connected with the drain end of the PMOS input tube M1, and the drain end of the NMOS tube M4 is connected with the drain end of the PMOS input tube M2 and forms an output end OUT of the comparator body;
the source terminal of the NMOS transistor M3 is grounded, and the source terminal of the NMOS transistor M4 is grounded.
7. A comparator for Gao domain according to any one of claims 1 to 4, characterised in that: the input pair tube comprises a PMOS input tube M1 and a PMOS input tube M2, and the source end of the PMOS input tube M1 is connected with the source end of the PMOS input tube M2;
the load unit comprises an NMOS tube M7, an NMOS tube M8, an NMOS tube M9 and an NMOS tube M10, wherein,
the drain end of the NMOS tube M7 is connected with the gate end of the NMOS tube M7, the gate end of the NMOS tube M9, the drain end of the NMOS tube M10 and the drain end of the PMOS input tube M1, and a differential output end OUT1 is formed;
the drain terminal of the NMOS tube M8 is connected with the gate terminal of the NMOS tube M8, the gate terminal of the NMOS tube M10, the drain terminal of the NMOS tube M9 and the drain terminal of the PMO input tube M2, and a differential output end OUT2 is formed;
the source terminal of NMOS tube M7, the source terminal of NMOS tube M8, the source terminal of NMOS tube M9 and the source terminal of NMOS tube M10 are all grounded.
8. The comparator for Gao domain as claimed in claim 7, wherein: the corresponding conducting channel width-to-length ratios of the NMOS tube M7, the NMOS tube M8, the NMOS tube M9 and the NMOS tube M10 are the same.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310971207.2A CN116781047B (en) | 2023-08-03 | 2023-08-03 | Comparator suitable for Gao domain |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310971207.2A CN116781047B (en) | 2023-08-03 | 2023-08-03 | Comparator suitable for Gao domain |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116781047A CN116781047A (en) | 2023-09-19 |
| CN116781047B true CN116781047B (en) | 2023-12-08 |
Family
ID=88013585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310971207.2A Active CN116781047B (en) | 2023-08-03 | 2023-08-03 | Comparator suitable for Gao domain |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116781047B (en) |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1482114A (en) * | 1973-08-02 | 1977-08-03 | Siemens Ag | Bistable trigger stages |
| JPH06109779A (en) * | 1992-09-28 | 1994-04-22 | Shimadzu Corp | Voltage comparator |
| JPH06273456A (en) * | 1993-03-22 | 1994-09-30 | Advantest Corp | Voltage comparison circuit |
| CN101282117A (en) * | 2007-04-05 | 2008-10-08 | 中国科学院微电子研究所 | Dynamic comparer |
| CN201345060Y (en) * | 2009-01-13 | 2009-11-11 | 北京时代民芯科技有限公司 | Negative feedback hysteresis comparator for controlling temperature |
| CN101692603A (en) * | 2009-04-21 | 2010-04-07 | 浙江大学 | Gain bootstrap type C class reverser and application circuit thereof |
| CN107370463A (en) * | 2017-06-15 | 2017-11-21 | 西安华泰半导体科技有限公司 | A kind of imbalance self-correcting amplifier based on back-gate effect and channel-length modulation |
| CN108574489A (en) * | 2017-03-09 | 2018-09-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of comparator and successive approximation analog-digital converter |
| CN110336546A (en) * | 2019-07-19 | 2019-10-15 | 电子科技大学 | A kind of low-power consumption high speed current comparator circuit |
| CN111565045A (en) * | 2020-05-26 | 2020-08-21 | 微龛(广州)半导体有限公司 | Comparator and analog-to-digital converter |
| CN111585550A (en) * | 2020-06-16 | 2020-08-25 | 成都信息工程大学 | Current comparison circuit for overvoltage protection |
| CN111711172A (en) * | 2020-06-22 | 2020-09-25 | 电子科技大学 | Undervoltage protection circuit with ultralow power consumption |
| CN114696802A (en) * | 2020-12-25 | 2022-07-01 | 上海贝岭股份有限公司 | Comparator circuit and chip comprising same |
| CN115276626A (en) * | 2022-08-29 | 2022-11-01 | 珠海普林芯驰科技有限公司 | PMOS drive circuit with grid voltage clamping protection function and enable translation circuit |
-
2023
- 2023-08-03 CN CN202310971207.2A patent/CN116781047B/en active Active
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1482114A (en) * | 1973-08-02 | 1977-08-03 | Siemens Ag | Bistable trigger stages |
| JPH06109779A (en) * | 1992-09-28 | 1994-04-22 | Shimadzu Corp | Voltage comparator |
| JPH06273456A (en) * | 1993-03-22 | 1994-09-30 | Advantest Corp | Voltage comparison circuit |
| CN101282117A (en) * | 2007-04-05 | 2008-10-08 | 中国科学院微电子研究所 | Dynamic comparer |
| CN201345060Y (en) * | 2009-01-13 | 2009-11-11 | 北京时代民芯科技有限公司 | Negative feedback hysteresis comparator for controlling temperature |
| CN101692603A (en) * | 2009-04-21 | 2010-04-07 | 浙江大学 | Gain bootstrap type C class reverser and application circuit thereof |
| CN108574489A (en) * | 2017-03-09 | 2018-09-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of comparator and successive approximation analog-digital converter |
| CN107370463A (en) * | 2017-06-15 | 2017-11-21 | 西安华泰半导体科技有限公司 | A kind of imbalance self-correcting amplifier based on back-gate effect and channel-length modulation |
| CN110336546A (en) * | 2019-07-19 | 2019-10-15 | 电子科技大学 | A kind of low-power consumption high speed current comparator circuit |
| CN111565045A (en) * | 2020-05-26 | 2020-08-21 | 微龛(广州)半导体有限公司 | Comparator and analog-to-digital converter |
| CN111585550A (en) * | 2020-06-16 | 2020-08-25 | 成都信息工程大学 | Current comparison circuit for overvoltage protection |
| CN111711172A (en) * | 2020-06-22 | 2020-09-25 | 电子科技大学 | Undervoltage protection circuit with ultralow power consumption |
| CN114696802A (en) * | 2020-12-25 | 2022-07-01 | 上海贝岭股份有限公司 | Comparator circuit and chip comprising same |
| CN115276626A (en) * | 2022-08-29 | 2022-11-01 | 珠海普林芯驰科技有限公司 | PMOS drive circuit with grid voltage clamping protection function and enable translation circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116781047A (en) | 2023-09-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20070188191A1 (en) | Differential amplifier with over-voltage protection and method | |
| US5115151A (en) | Triple comparator circuit | |
| US7498847B2 (en) | Output driver that operates both in a differential mode and in a single mode | |
| US6236270B1 (en) | Operational amplifier circuit including folded cascode circuit | |
| JP2004071681A (en) | Input protective network | |
| US8106706B2 (en) | DC biasing circuit for a metal oxide semiconductor transistor | |
| CN116781047B (en) | Comparator suitable for Gao domain | |
| CN113131886B (en) | Operational amplifier | |
| CN111416579B (en) | Receiver front-end circuit and operation method thereof | |
| CN115967360B (en) | Signal amplifying circuit for receiving end of capacitive isolator and capacitive isolator | |
| CN112825476A (en) | Operational amplifier | |
| US6911871B1 (en) | Circuit with voltage clamping for bias transistor to allow power supply over-voltage | |
| CN111817689B (en) | High-linearity attenuator | |
| Karthikeyan et al. | Design of low-voltage front-end interface for switched-op amp circuits | |
| US6933784B2 (en) | Output stage for high gain and low distortion operational amplifier | |
| CN114070207A (en) | Input stage of high-voltage operational amplifier | |
| CN113671236A (en) | Current detection circuit and equipment applied to load resistor | |
| JP5322758B2 (en) | Output circuit | |
| US6366168B1 (en) | Efficient ground noise and common-mode suppression network | |
| TW201630334A (en) | Circuit and amplifier with deterministic noise cancellation | |
| CN114362700B (en) | Differential amplifier and back gate control method thereof | |
| CN216672967U (en) | Input stage of high-voltage operational amplifier | |
| CN110492852B (en) | Differential input structure capable of improving operational amplifier performance | |
| CN216437171U (en) | Voltage translation circuit and detection circuit | |
| US20240039769A1 (en) | Systems and methods for improving common mode transient immunity in silicon digital isolators using capacitive barrier for galvanic isolation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |