CN114070207A - Input stage of high-voltage operational amplifier - Google Patents

Input stage of high-voltage operational amplifier Download PDF

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Publication number
CN114070207A
CN114070207A CN202111604217.XA CN202111604217A CN114070207A CN 114070207 A CN114070207 A CN 114070207A CN 202111604217 A CN202111604217 A CN 202111604217A CN 114070207 A CN114070207 A CN 114070207A
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China
Prior art keywords
tube
pmos tube
electrode
pmos
nmos
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付美俊
靳瑞英
鞠建宏
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Jiangsu Dior Microelectronics Co ltd
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Jiangsu Dior Microelectronics Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H03F1/48—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers
    • H03F1/483—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses an input stage of a high-voltage operational amplifier, which is applied to the technical field of operational amplifiers and comprises an input stage core circuit (100), a fast pull-down circuit (200) and a fast pull-up circuit (300). The rapid pull-up and pull-down circuit ensures that the withstand voltage of the input tube does not exceed the rated voltage by 5.5V even under the condition that the input signal is rapid and has large swing amplitude, and realizes that a 5V low-voltage MOS is used as the input stage of a high-voltage power supply and a high-voltage input operational amplifier; the matching, noise, transconductance and the like of the 5V device are far better than those of the high-voltage device, so that lower mismatch voltage, lower noise, higher bandwidth and stronger consistency can be obtained.

Description

Input stage of high-voltage operational amplifier
Technical Field
The invention relates to the technical field of operational amplifiers, in particular to an input stage of a high-voltage operational amplifier.
Background
The general operational amplifier works in a low-voltage power supply domain, such as 5V, and the amplitude of an input signal cannot exceed 5V. The voltage-resistant requirement can be met by adopting a 5V device at the input stage, so that an additional protection circuit is not needed, and the 5.5V device can resist the voltage of 5.5V. However, at the input stage of the high-voltage operational amplifier, the withstand voltage of the power supply voltage and the input and output voltages can reach dozens of volts or even hundreds of volts. The high-voltage P/NMOS adopting the BCD process can only bear high voltage at the drain terminal, and the source-grid voltage resistance is 5V, so a plurality of protection circuits are added in the circuit to support a high-voltage power supply and high-voltage input. Selecting a special fab process: the threshold voltage of the high-voltage PMOS is low, the grid of a 5V input geminate transistor can be directly connected with the grid of the high-voltage protection transistor, and the structure is simple, as shown in the figure 1. However, the structure can only be used for a special process with a low threshold voltage of the high-voltage PMOS, and the application range is narrow.
Therefore, it is an urgent need for those skilled in the art to provide an input stage of a high voltage operational amplifier to solve the current technical problems.
Disclosure of Invention
In view of the above, the present invention provides an input stage of a high-voltage operational amplifier, which solves the voltage withstanding problem of a high-voltage power supply and the high-voltage input operational amplifier.
In order to achieve the purpose, the invention adopts the following technical scheme:
an input stage of a high voltage operational amplifier, comprising:
the circuit comprises an input stage core circuit, a quick pull-down circuit and a quick pull-up circuit;
the input stage core circuit includes: the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the first NMOS tube, the second NMOS tube, the first series diode group and the second series diode group;
the drain electrode of the first NMOS tube and the positive input end V of the operational amplifierIN+The source electrode of the first NMOS tube is connected with the grid electrode of the third PMOS tube; the drain electrode of the second NMOS tube and the negative input end V of the operational amplifierIN-The source electrode of the second NMOS tube is connected with the grid electrode of the fourth PMOS tube; the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube are both connected with the output end of the fast pull-up circuit; the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube, the input end of the fast pull-up circuit and the source electrode of the second PMOS tubeThe drain electrode and the input end of the quick pull-down circuit share a terminal; the source electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube; the grid electrode of the second PMOS tube is connected with the second output end of the bias circuit; the source electrode and the V of the first PMOS tubeCCThe grid electrode of the first PMOS tube is connected with the first output end of the bias circuit; the source electrode of the fifth PMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are both connected with the output end of the fast pull-down circuit, and the drain electrode of the fifth PMOS tube is connected with the first connecting end of the cascode stage; the source electrode of the sixth PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the second connecting end of the cascode stage; the cathode of the first series diode group is connected with the drain electrode of the third PMOS tube, the cathode of the second series diode group is connected with the drain electrode of the fourth PMOS tube, the anode of the first series diode group is connected with the source electrode of the third PMOS tube, and the anode of the second series diode group is connected with the source electrode of the fourth PMOS tube.
Optionally, the fast pull-down circuit includes: a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube;
the drain electrode of the third NMOS tube is connected with VCCThe grid electrode of the third NMOS tube is the input end of the fast pull-down circuit, and the source electrode of the third NMOS tube, the source electrode of the seventh PMOS tube and the source electrode of the eighth PMOS tube share an endpoint; the grid electrode of the eighth PMOS tube, the drain electrode of the eighth PMOS tube, the source electrode of the ninth PMOS tube and the drain electrode of the tenth PMOS tube share a common endpoint and serve as the output end of the fast pull-down circuit; the grid electrode of the seventh PMOS tube is connected with the grid electrode of the eighth PMOS tube; the drain electrode of the seventh PMOS tube, the drain electrode of the fourth NMOS tube and the grid electrode of the ninth PMOS tube share a common endpoint; the grid electrode of the fourth NMOS tube is connected with the grid electrode of the tenth PMOS tube and then is connected to the seventh output end of the bias circuit; the source electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube, and the tenth PMOS tubeThe source electrode of the second NMOS tube is connected with the drain electrode of the sixth NMOS tube; the grid electrode of the fifth NMOS tube is connected with the grid electrode of the sixth NMOS tube and then is connected to the sixth output end of the bias circuit; and the drain electrode of the ninth PMOS tube, the source electrode of the fifth NMOS tube and the source electrode of the sixth NMOS tube are all connected with GND.
Optionally, the fast pull-up circuit includes: an eleventh PMOS (P-channel metal oxide semiconductor) tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, a seventh NMOS (N-channel metal oxide semiconductor) tube, an eighth NMOS tube and a ninth NMOS tube;
the grid electrode of the seventeenth PMOS tube is the input end of the fast pull-up circuit; the drain electrode of the seventeenth PMOS tube is connected with GND; a source electrode of the seventeenth PMOS tube, a source electrode of the eighth NMOS tube and a source electrode of the ninth NMOS tube share a common terminal; the grid electrode of the eighth NMOS tube is connected with the grid electrode of the ninth NMOS tube; the grid electrode of the eighth NMOS tube, the drain electrode of the fifteenth PMOS tube and the source electrode of the seventh NMOS tube share a common endpoint and serve as the output end of the fast pull-up circuit; the drain electrode of the ninth NMOS tube, the gate electrode of the seventh NMOS tube and the drain electrode of the sixteenth PMOS tube share a common terminal; the source electrode of the fifteenth PMOS tube is connected with the drain electrode of the thirteenth PMOS tube, and the source electrode of the thirteenth PMOS tube is connected with the drain electrode of the eleventh PMOS tube; a source electrode of the sixteenth PMOS tube is connected with a drain electrode of the fourteenth PMOS tube, and a source electrode of the fourteenth PMOS tube is connected with a drain electrode of the twelfth PMOS tube; a grid electrode of the fifteenth PMOS tube is connected with a grid electrode of the sixteenth PMOS tube and then connected to a fifth output end of the bias circuit, and a grid electrode of the thirteenth PMOS tube is connected with a grid electrode of the fourteenth PMOS tube and then connected to a fourth output end of the bias circuit; the grid electrode of the eleventh PMOS tube is connected with the grid electrode of the twelfth PMOS tube and then is connected to the third output end of the bias circuit; the source electrode of the eleventh PMOS tube, the source electrode of the twelfth PMOS tube and the drain electrode of the seventh NMOS tube are all connected with VCC。
As can be seen from the above technical solutions, compared with the prior art, the present invention provides an input stage of a high-voltage operational amplifier: the fast pull-up and pull-down circuits ensure that the withstand voltage of the input tube does not exceed the rated voltage by 5.5V even under the condition that the input signal is fast and has large swing amplitude, and 5V low-voltage MOS is used as the input stage of a high-voltage power supply and a high-voltage input operational amplifier; the matching, noise, transconductance and the like of the 5V device are far better than those of the high-voltage device, so that lower mismatch voltage, lower noise, higher bandwidth and stronger consistency can be obtained.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is an electrical schematic diagram of a structure in which a gate of a high voltage protection tube is connected to a gate of an input pair tube;
FIG. 2 is an electrical schematic diagram of an input stage structure of a high voltage operational amplifier according to the present invention;
FIG. 3 is an electrical schematic of the fast pulldown circuit of the present invention;
FIG. 4 is an electrical schematic of the fast pull-up circuit of the present invention;
FIG. 5 is a detailed electrical schematic diagram of an input stage of a high voltage operational amplifier according to the present invention;
fig. 6 is an electrical schematic diagram of a first stage high voltage operational amplifier according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2, the present invention discloses an input stage of a high voltage operational amplifier, including: an input stage core circuit 100, a fast pull-down circuit 200, and a fast pull-up circuit 300;
the input stage core circuit 100 includes: a first PMOS transistor 101, a second PMOS transistor 102, a third PMOS transistor 103, a fourth PMOS transistor 104, a fifth PMOS transistor 107, a sixth PMOS transistor 108, a first NMOS transistor 105, a second NMOS transistor 106, a first series diode group 109, and a second series diode group 110;
the drain of the first NMOS transistor 105 and the positive input terminal V of the operational amplifierIN+The source electrode of the first NMOS tube 105 is connected with the grid electrode of the third PMOS tube 103; the drain of the second NMOS transistor 106 and the negative input terminal V of the operational amplifierIN-The source of the second NMOS transistor 106 is connected to the gate of the fourth PMOS transistor 104; the grid electrode of the first NMOS tube 105 and the grid electrode of the second NMOS tube 106 are both connected with the output end of the fast pull-up circuit 300; the source electrode of the third PMOS transistor 103, the source electrode of the fourth PMOS transistor 104, the input terminal of the fast pull-up circuit 300, the drain electrode of the second PMOS transistor 102, and the input terminal of the fast pull-down circuit 200 share a terminal; the source electrode of the second PMOS tube 102 is connected with the drain electrode of the first PMOS tube 101; the grid electrode of the second PMOS tube 102 is connected with the second output end of the bias circuit; source and V of the first PMOS transistor 101CCThe grid electrode of the first PMOS tube 101 is connected with the first output end of the bias circuit; the source electrode of the fifth PMOS transistor 107 is connected with the drain electrode of the third PMOS transistor 103, the gate electrode of the fifth PMOS transistor 107 and the gate electrode of the sixth PMOS transistor 108 are both connected with the output end of the fast pull-down circuit 200, and the drain electrode of the fifth PMOS transistor 107 is connected with the first connection end of the cascode stage; the source electrode of the sixth PMOS transistor 108 is connected to the drain electrode of the fourth PMOS transistor 104, and the drain electrode of the sixth PMOS transistor 108 is connected to the second connection end of the cascode stage; the cathode of the first series diode group 109 is connected to the drain of the third PMOS transistor 103, the cathode of the second series diode group 110 is connected to the drain of the fourth PMOS transistor 104, the anode of the first series diode group 109 is connected to the source of the third PMOS transistor 103, and the anode of the second series diode group 110 is connected to the source of the fourth PMOS transistor 104.
The input stage core circuit 100 is a main part of the input stage of the operational amplifier. The third PMOS tube 103 and the fourth PMOS tube 104 are input differential pair tubes with the withstand voltage of 5V; the first PMOS tube 101 and the second PMOS tube 102 form a tail current source of the input stage and provide working current for the input stage; the fifth PMOS transistor 107 and the sixth PMOS transistor 108 are high-voltage transistors and are used for protecting the source-drain overvoltage of the input pair transistors of the third PMOS transistor 103 and the fourth PMOS transistor 104; the first NMOS transistor 105 and the second NMOS transistor 106 are high voltage transistors, and are used for transmitting input signals and protecting the gate-source and gate-drain overvoltage of the input pair transistors, the third PMOS transistor 103 and the fourth PMOS transistor 104; the drains of the fifth PMOS transistor 107 and the sixth PMOS transistor 108 are connected to the post-stage cascode circuit 400, so as to form a complete operational amplifier.
The first NMOS transistor 105 and the second NMOS transistor 106 are high-voltage protection devices of the third PMOS transistor 103 and the fourth PMOS transistor 104 of the input stage differential pair transistor, when V isIN+And VIN-When there is a large voltage difference between them, e.g. VIN+＝20V，VIN-0V, in which case Vg1The gate voltage V of the first NMOS transistor 105 is 3Vg1Lower than the drain terminal voltage VIN+And the differential pair transistors are turned off, and the voltage of 20V is not transmitted to the gate of the third PMOS transistor 103, that is, the high-voltage first NMOS transistor 105 resists the high voltage, so that the input-stage differential pair transistors of the first NMOS transistor 105 and the second NMOS transistor 106 are protected, and the difference between the gate-source voltage and the gate-drain voltage is less than 5V.
The fifth PMOS transistor 107 and the sixth PMOS transistor 108 are high voltage transistors, and are used for protecting the source-drain voltages of the input pair transistors of the third PMOS transistor 103 and the fourth PMOS transistor 104 from being less than 5V. When the input signal is relatively high, e.g. VIN+＝20V，VIN-20V, the gate voltage V of the fifth PMOS transistor 107 and the sixth PMOS transistor 108g2Will follow the input signal variation, Vg2＝VIN2++VGS103-VGS201-VGS203V of 5V withstand voltage MOSGSAbout 0.7V, V of high-pressure pipeGSAbout 1.1V. So Vg2And VIN+，VIN-The voltage difference is far lower than 5V, so that the gate-drain and source-drain voltage difference of the third PMOS transistor 103 and the fourth PMOS transistor 104 of the input pair transistor is within 5V, and the protection purpose is achieved.
The first series diode group 109 and the second series diode group 110 are two series diodes for protecting the source-drain voltages of the input pair transistors third PMOS transistor 103 and fourth PMOS transistor 104 from 5V.
The fast pull-up circuit 300 and the fast pull-down circuit 200 are used for protecting the source-drain, gate-drain and gate-source voltage difference of the low-voltage tube from exceeding 5V, so that when an input signal is fast and the amplitude of oscillation changes greatly, the node of an internal circuit can change fast.
In one embodiment, referring to fig. 3, the present invention discloses a fast pull-down circuit 200, comprising: a seventh PMOS transistor 202, an eighth PMOS transistor 203, a ninth PMOS transistor 204, a tenth PMOS transistor 206, a third NMOS transistor 201, a fourth NMOS transistor 205, a fifth NMOS transistor 207, and a sixth NMOS transistor 208;
the drain of the third NMOS transistor 201 is connected to VCCThe gate of the third NMOS transistor 201 is the input terminal of the fast pull-down circuit 200, and the source of the third NMOS transistor 201, the source of the seventh PMOS transistor 202, and the source of the eighth PMOS transistor 203 share a common node; the grid electrode of the eighth PMOS transistor 203, the drain electrode of the eighth PMOS transistor 203, the source electrode of the ninth PMOS transistor 204, and the drain electrode of the tenth PMOS transistor 206 share a common terminal and serve as the output end of the fast pull-down circuit 200; the grid electrode of the seventh PMOS tube 202 is connected with the grid electrode of the eighth PMOS tube 203; the drain of the seventh PMOS transistor 202, the drain of the fourth NMOS transistor 205, and the gate of the ninth PMOS transistor 204 share a common node; the grid electrode of the fourth NMOS transistor 205 is connected to the grid electrode of the tenth PMOS transistor 206 and then connected to the seventh output end of the bias circuit; the source of the fourth NMOS transistor 205 is connected to the drain of the fifth NMOS transistor 207, and the source of the tenth PMOS transistor 206 is connected to the drain of the sixth NMOS transistor 208; the grid electrode of the fifth NMOS tube 207 is connected with the grid electrode of the sixth NMOS tube 208 and then is connected to the sixth output end of the bias circuit; the drain of the ninth PMOS transistor 204, the source of the fifth NMOS transistor 207, and the source of the sixth NMOS transistor 208 are all connected to GND.
The fast pull-down circuit 200 is used for providing a voltage bias to the gates of the fifth PMOS transistor 107 and the sixth PMOS transistor 108, and can follow the fast-changing input signal. With reference to fig. 5, the working principle is analyzed: bias voltage Vg2＝VIN2++VGS103-VGS201-VGS203. When V isIN+When falling rapidly, VSWill follow the rapid fall, VS_201Also rapidly decreases, Vg2The current of the branch circuits of the fourth NMOS 205 and the fifth NMOS 207 is twice greater than that of the branch circuits of the tenth PMOS 206 and the sixth NMOS 208, and the currents of the eighth PMOS 203 and the ninth PMOS 204 are equal, so the gate voltage V of the ninth PMOS 204 drops rapidlyg_204Always will be higher than the source voltage Vg2One threshold voltage lower, i.e. the ninth PMOS transistor 204 is always on, Vg2Will be pulled quickly towards GND. This ensures that when the input signal changes rapidly downwards, Vg2The variation is quickly followed, so that the fifth PMOS transistor 107 and the sixth PMOS transistor 108 are always in a conducting state.
In one embodiment, referring to fig. 4, a fast pull-up circuit 300 includes: an eleventh PMOS transistor 301, a twelfth PMOS transistor 302, a thirteenth PMOS transistor 303, a fourteenth PMOS transistor 304, a fifteenth PMOS transistor 305, a sixteenth PMOS transistor 306, a seventeenth PMOS transistor 310, a seventh NMOS transistor 307, an eighth NMOS transistor 308, and a ninth NMOS transistor 309;
the gate of the seventeenth PMOS transistor 310 is the input terminal of the fast pull-up circuit 300; the drain of the seventeenth PMOS tube 310 is connected to GND; the source of the seventeenth PMOS tube 310, the source of the eighth NMOS tube 308, and the source of the ninth NMOS tube 309 share a common node; the gate of the eighth NMOS transistor 308 is connected to the gate of the ninth NMOS transistor 309; the grid electrode of the eighth NMOS tube 308, the drain electrode of the fifteenth PMOS tube 305 and the source electrode of the seventh NMOS tube 307 share a common terminal and serve as the output end of the fast pull-up circuit 300; the drain of the ninth NMOS transistor 309, the gate of the seventh NMOS transistor 307, and the drain of the sixteenth PMOS transistor 306 share a common node; the source electrode of the fifteenth PMOS transistor 305 is connected with the drain electrode of the thirteenth PMOS transistor 303, and the source electrode of the thirteenth PMOS transistor 303 is connected with the drain electrode of the eleventh PMOS transistor 301; the source of the sixteenth PMOS transistor 306 is connected to the drain of the fourteenth PMOS transistor 304, and the source of the fourteenth PMOS transistor 304 is connected to the drain of the twelfth PMOS transistor 302; the grid electrode of the fifteenth PMOS transistor 305 is connected with the grid electrode of the sixteenth PMOS transistor 306 and then connected to the fifth output end of the bias circuit, and the grid electrode of the thirteenth PMOS transistor 303 is connected with the grid electrode of the fourteenth PMOS transistor 304 and then connected to the fourth output end of the bias circuit; the grid electrode of the eleventh PMOS tube 301 is connected with the grid electrode of the twelfth PMOS tube 302 and then is connected to the third output end of the bias circuit; source electrode of eleventh PMOS tube 301The source electrode of the twelve PMOS tube 302 and the drain electrode of the seventh NMOS tube 307 are both connected with VCC。
The fast pull-up circuit 300 is used for providing voltage bias for the gates of the first NMOS transistor 105 and the second NMOS transistor 106, and can follow the fast-changing input signal. With reference to fig. 5, the working principle is analyzed: bias voltage Vg1＝VIN++VGS105+VGS310+VGS308. When V isIN+Or VIN-When the voltage rises rapidly, the current of the eighth NMOS tube 308 branch is equal to that of the ninth NMOS tube 309 branch, and the current of the twelfth PMOS tube 302, the fourteenth PMOS tube 304 and the sixteenth PMOS tube 306 branch is twice that of the eleventh PMOS tube 301, the thirteenth PMOS tube 303 and the fifteenth PMOS tube 305, so that V is equal to Vg_307Voltage ratio Vg1The seventh NMOS tube 307 is always in a conducting state when the threshold voltage is higher by one, and can quickly turn Vg1Upward pull direction VCC. This ensures that when the input signal changes rapidly upwards, Vg1The first NMOS transistor 105 and the second NMOS transistor 106 are always in a conducting state by following the change.
In one embodiment, referring to fig. 5, the present invention discloses a specific electrical schematic diagram of an input stage of a high-voltage operational amplifier, wherein an input terminal of a fast pull-down circuit 200 is a gate of a third NMOS transistor 201, and an output terminal of the fast pull-down circuit 200 is a drain of a tenth PMOS transistor 206; the input end of the fast pull-up circuit 300 is the gate of the seventeenth PMOS tube 310, and the output end of the fast pull-up circuit 300 is the common node of the gate of the eighth NMOS tube 308, the drain of the fifteenth PMOS tube 305, and the source of the seventh NMOS tube 307.
Wherein, the high-pressure tube is respectively: the second PMOS transistor 102, the first NMOS transistor 105, the second NMOS transistor 106, the fifth PMOS transistor 107, the sixth PMOS transistor 108, the third NMOS transistor 201, the ninth PMOS transistor 204, the fourth NMOS transistor 205, the tenth PMOS transistor 206, the fifteenth PMOS transistor 305, the sixteenth PMOS transistor 306, the seventh NMOS transistor 307, the seventeenth PMOS transistor 310, and the rest of the devices are 5V low-voltage devices.
By adopting the input stage structure, a PMOS input high-voltage operational amplifier with rail-to-rail voltage output is designed, a BCD process is adopted, a 36V device is adopted for a high-voltage tube, the power supply voltage and the input voltage range can reach 36V withstand voltage, the high-voltage operational amplifier can normally work under a rapid and large-swing signal, the high-voltage operational amplifier is aged for 500 hours under the large-swing working condition, the performance still meets the requirement, and the offset is extremely small. The invention is proposed to be applied to 36V, and is not limited to 36V in practice, and other voltages are applied. Fig. 6 is an example of practical implementation of the present invention.
In one embodiment, referring to fig. 6, the present invention further discloses an electrical schematic diagram of a first-stage high-voltage operational amplifier, comprising: an input stage core circuit 100, a fast pull-down circuit 200, a fast pull-up circuit 300 and a cascode stage circuit 400 (the circuit structure is not described in detail); the source of 406, the drain of 408 and the drain of the fifth PMOS transistor 107 share a terminal, which is the first connection terminal of the cascode stage circuit 400; the source of 405, the drain of 407, and the drain of the sixth PMOS transistor 108 share a terminal, which is the second connection terminal of the cascode stage circuit 400.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention in a progressive manner. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (3)

1. An input stage of a high voltage operational amplifier, comprising:
an input stage core circuit (100), a fast pull-down circuit (200) and a fast pull-up circuit (300);
the input stage core circuit (100) comprises: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) tube (101), a second PMOS tube (102), a third PMOS tube (103), a fourth PMOS tube (104), a fifth PMOS tube (107), a sixth PMOS tube (108), a first NMOS (N-channel metal oxide semiconductor) tube (105), a second NMOS tube (106), a first series diode group (109) and a second series diode group (110);
the first mentionedThe drain of an NMOS transistor (105) and the positive input terminal V of the operational amplifierIN+The source electrode of the first NMOS tube (105) is connected with the grid electrode of the third PMOS tube (103); the drain electrode of the second NMOS tube (106) and the negative input end V of the operational amplifierIN-The source electrode of the second NMOS tube (106) is connected with the grid electrode of the fourth PMOS tube (104); the grid electrode of the first NMOS tube (105) and the grid electrode of the second NMOS tube (106) are both connected with the output end of the fast pull-up circuit (300); the source electrode of the third PMOS tube (103), the source electrode of the fourth PMOS tube (104), the input end of the fast pull-up circuit (300), the drain electrode of the second PMOS tube (102) and the input end of the fast pull-down circuit (200) share a terminal; the source electrode of the second PMOS tube (102) is connected with the drain electrode of the first PMOS tube (101); the grid electrode of the second PMOS tube (102) is connected with the second output end of the bias circuit; the source electrode of the first PMOS tube (101) and VCCThe grid electrode of the first PMOS tube (101) is connected with the first output end of the bias circuit; the source electrode of the fifth PMOS tube (107) is connected with the drain electrode of the third PMOS tube (103), the grid electrode of the fifth PMOS tube (107) and the grid electrode of the sixth PMOS tube (108) are both connected with the output end of the fast pull-down circuit (200), and the drain electrode of the fifth PMOS tube (107) is connected with the first connection end of the cascode stage; the source electrode of the sixth PMOS tube (108) is connected with the drain electrode of the fourth PMOS tube (104), and the drain electrode of the sixth PMOS tube (108) is connected with the second connecting end of the cascode stage; the cathode of the first series diode group (109) is connected with the drain of the third PMOS tube (103), the cathode of the second series diode group (110) is connected with the drain of the fourth PMOS tube (104), the anode of the first series diode group (109) is connected with the source of the third PMOS tube (103), and the anode of the second series diode group (110) is connected with the source of the fourth PMOS tube (104).
2. An input stage of a high voltage operational amplifier according to claim 1,
the fast pull-down circuit (200) comprises: a seventh PMOS tube (202), an eighth PMOS tube (203), a ninth PMOS tube (204), a tenth PMOS tube (206), a third NMOS tube (201), a fourth NMOS tube (205), a fifth NMOS tube (207) and a sixth NMOS tube (208);
the drain electrode of the third NMOS tube (201) is connected with VCCThe grid electrode of the third NMOS tube (201) is the input end of the fast pull-down circuit (200), and the source electrode of the third NMOS tube (201), the source electrode of the seventh PMOS tube (202) and the source electrode of the eighth PMOS tube (203) share an endpoint; the grid electrode of the eighth PMOS tube (203), the drain electrode of the eighth PMOS tube (203), the source electrode of the ninth PMOS tube (204) and the drain electrode of the tenth PMOS tube (206) share a common endpoint and are used as the output end of the fast pull-down circuit (200); the grid electrode of the seventh PMOS tube (202) is connected with the grid electrode of the eighth PMOS tube (203); the drain electrode of the seventh PMOS tube (202), the drain electrode of the fourth NMOS tube (205) and the grid electrode of the ninth PMOS tube (204) share a common terminal; the grid electrode of the fourth NMOS tube (205) is connected with the grid electrode of the tenth PMOS tube (206) and then connected to a seventh output end of the bias circuit; the source electrode of the fourth NMOS tube (205) is connected with the drain electrode of the fifth NMOS tube (207), and the source electrode of the tenth PMOS tube (206) is connected with the drain electrode of the sixth NMOS tube (208); the grid electrode of the fifth NMOS tube (207) is connected with the grid electrode of the sixth NMOS tube (208) and then connected to the sixth output end of the bias circuit; the drain electrode of the ninth PMOS tube (204), the source electrode of the fifth NMOS tube (207) and the source electrode of the sixth NMOS tube (208) are all connected with GND.
3. An input stage of a high voltage operational amplifier according to claim 1,
the fast pull-up circuit (300) comprises: an eleventh PMOS (p-channel metal oxide semiconductor) tube (301), a twelfth PMOS tube (302), a thirteenth PMOS tube (303), a fourteenth PMOS tube (304), a fifteenth PMOS tube (305), a sixteenth PMOS tube (306), a seventeenth PMOS tube (310), a seventh NMOS tube (307), an eighth NMOS tube (308) and a ninth NMOS tube (309);
the grid electrode of the seventeenth PMOS tube (310) is the input end of the fast pull-up circuit (300); the drain electrode of the seventeenth PMOS tube (310) is connected with GND; a source electrode of the seventeenth PMOS tube (310), a source electrode of the eighth NMOS tube (308), and a source electrodeA source common terminal of the ninth NMOS transistor (309); the grid electrode of the eighth NMOS tube (308) is connected with the grid electrode of the ninth NMOS tube (309); the grid electrode of the eighth NMOS tube (308), the drain electrode of the fifteenth PMOS tube (305) and the source electrode of the seventh NMOS tube (307) share a common terminal and serve as the output end of the fast pull-up circuit (300); the drain electrode of the ninth NMOS tube (309), the gate electrode of the seventh NMOS tube (307) and the drain electrode of the sixteenth PMOS tube (306) share a common terminal; the source electrode of the fifteenth PMOS tube (305) is connected with the drain electrode of the thirteenth PMOS tube (303), and the source electrode of the thirteenth PMOS tube (303) is connected with the drain electrode of the eleventh PMOS tube (301); the source electrode of the sixteenth PMOS tube (306) is connected with the drain electrode of the fourteenth PMOS tube (304), and the source electrode of the fourteenth PMOS tube (304) is connected with the drain electrode of the twelfth PMOS tube (302); the grid electrode of the fifteenth PMOS tube (305) is connected with the grid electrode of the sixteenth PMOS tube (306) and then connected to the fifth output end of the bias circuit, and the grid electrode of the thirteenth PMOS tube (303) is connected with the grid electrode of the fourteenth PMOS tube (304) and then connected to the fourth output end of the bias circuit; the grid electrode of the eleventh PMOS tube (301) is connected with the grid electrode of the twelfth PMOS tube (302) and then is connected to the third output end of the bias circuit; the source electrode of the eleventh PMOS tube (301), the source electrode of the twelfth PMOS tube (302) and the drain electrode of the seventh NMOS tube (307) are all connected with VCC。
CN202111604217.XA 2021-12-24 2021-12-24 Input stage of high-voltage operational amplifier Pending CN114070207A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116366010A (en) * 2023-03-09 2023-06-30 苏州纳芯微电子股份有限公司 Operational amplifier, operational amplifying circuit, chip and electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116366010A (en) * 2023-03-09 2023-06-30 苏州纳芯微电子股份有限公司 Operational amplifier, operational amplifying circuit, chip and electronic device

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