CN116264460A - Structure for improving voltage withstand value of open drain output stage - Google Patents
Structure for improving voltage withstand value of open drain output stage Download PDFInfo
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- CN116264460A CN116264460A CN202111532890.7A CN202111532890A CN116264460A CN 116264460 A CN116264460 A CN 116264460A CN 202111532890 A CN202111532890 A CN 202111532890A CN 116264460 A CN116264460 A CN 116264460A
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- 230000000087 stabilizing effect Effects 0.000 claims abstract description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The structure for improving the withstand voltage of the Open Drain output stage can share the bearing pressure of the power supply voltage VDD from the subsequent stage for the Drain electrode of the NMOS tube of the output stage by connecting circuits such as a voltage stabilizing tube and the like between the Drain electrode of the NMOS tube of the output stage and an output voltage end, thereby improving the withstand voltage of the output stage, avoiding the direct action of the power supply voltage of the subsequent stage between Drain and Source of the MOS tube of the Open-Drain output stage, reducing the VDS of the MOS tube of the output stage and ensuring the correct output and pull-down driving capability.
Description
Technical Field
The invention relates to a voltage withstand technology of an output stage MOS tube, in particular to a structure for improving the voltage withstand value of an open drain output stage.
Background
The open-drain circuit is a circuit taking the drain electrode of the MOS tube as output. The voltage value of the Open-drain output stage can reach the power supply voltage of the later stage at the highest, and when the power supply voltage of the later stage exceeds the voltage withstand value of the output stage, the NMOS of the output stage can be damaged. The withstand voltage value of the output stage NMOS is generally determined by the withstand voltage capability between the drain electrode and the source electrode of the output MOS transistor, and is limited by the process. In the face of improving the voltage withstand value between the drain electrode and the source electrode of the MOS transistor, the ring spacing is generally increased on a layout (integrated circuit layout) of the layout, but the improvement amplitude is small, and the reliability is low. The process with higher voltage can be replaced to realize higher withstand voltage value, but the process with higher voltage has higher production cost.
Disclosure of Invention
Aiming at the defects or shortcomings in the prior art, the invention provides a structure for improving the withstand voltage value of an open drain output stage.
The technical scheme of the invention is as follows:
the structure for improving the withstand voltage value of the open drain output stage is characterized by comprising a drain electrode of an NMOS (N-channel metal oxide semiconductor) tube of the output stage as a first voltage node, wherein a first path of the first voltage node is connected with an output voltage end through a first voltage stabilizing tube in sequence, a second path of the first voltage node is connected with a grounding end through a first current source in sequence, a source electrode of the NMOS tube of the output stage is connected with the grounding end, a grid electrode of the NMOS tube of the output stage is connected with an output end of an inverter, and an input end of the inverter is connected with an input voltage end.
The first voltage node is connected with the drain electrode of the second NMOS tube in a third way, the source electrode of the second NMOS tube and the source electrode of the third NMOS tube are connected into a second voltage node and then connected with the grounding end through the second current source, the grid electrode of the second NMOS tube and the grid electrode of the third NMOS tube are connected with the grounding end through the first voltage source after being connected with each other, and the drain electrode of the third NMOS tube is connected with the output voltage end.
The output voltage end is connected with a power supply voltage end of a later stage through a pull-up resistor.
The first voltage source is 5.5V, and the reverse conducting voltage of the first voltage stabilizing tube is 5V.
The first current source is used for biasing the potential of the first voltage node, and the second current source is used for biasing the potential of the second voltage node.
The first voltage source is used for biasing the second NMOS tube and the third NMOS tube so as to enable the second NMOS tube and the third NMOS tube to be conducted.
The invention has the following technical effects: according to the structure for improving the withstand voltage value of the Open Drain output stage, the voltage stabilizing tube and other circuits are connected between the Drain electrode of the NMOS tube of the output stage and the output voltage end, so that the voltage bearing of the power supply voltage VDD from the later stage can be shared for the Drain electrode of the NMOS tube of the output stage, the withstand voltage value of the output stage is improved, the power supply voltage of the later stage is prevented from directly acting between Drain and Source of the MOS tube of the Open-Drain output stage, VDS of the MOS tube of the output stage is reduced, and correct output and pull-down driving capability can be ensured.
Drawings
Fig. 1 is a schematic circuit diagram of a structure for improving the withstand voltage of an open drain output stage according to the present invention.
Fig. 2 is a schematic diagram of the circuit of fig. 1 in normal use with a pull-up resistor Rpull connected between OUT and the post power supply VDD.
The reference numerals are listed below: VDD-supply voltage or supply voltage terminal; GND-ground; VIN-input voltage terminal or input voltage; an OUT-output voltage terminal or output voltage (or labeled VOUT); d0—a first voltage stabilizing tube (clamping tube, which shares the bearing of the power supply voltage VDD from the subsequent stage for the drain electrode of the output stage NMOS tube M0, that is, reduces the VDS of M0, or protects M0, or makes M0 realize a higher voltage withstanding value); M0-M2-first NMOS tube to third NMOS tube (wherein the first NMOS tube M0 is the output stage NMOS tube, its drain electrode is the open drain output stage); I1-I2-a first current source to a second current source; v0-a first voltage source; A-B-the first voltage node to the second voltage node; rmul-pull-up resistor.
Detailed Description
The invention will be described with reference to the accompanying drawings (fig. 1-2).
Fig. 1 is a schematic circuit diagram of a structure for improving the withstand voltage of an open drain output stage according to the present invention. Fig. 2 is a schematic diagram of the circuit of fig. 1 in normal use with a pull-up resistor Rpull connected between OUT and the post power supply VDD. Referring to fig. 1 to 2, a structure for improving the withstand voltage of an open drain output stage includes taking a drain electrode of an output stage NMOS (i.e., a first NMOS M0) as a first voltage node a, wherein a first path of the first voltage node a is connected to an output voltage terminal OUT by being connected to a first voltage stabilizing tube D0, a second path of the first voltage node a is connected to a ground terminal GND by being connected to a first current source I1, a source electrode of the output stage NMOS M0 is connected to the ground terminal GND, a gate electrode of the output stage NMOS M0 is connected to an output terminal of an inverter, and an input terminal of the inverter is connected to an input voltage terminal VIN. The first voltage node A is connected with the drain electrode of a second NMOS tube M1 in a third way, the source electrode of the second NMOS tube M1 and the source electrode of a third NMOS tube M2 are connected into a second voltage node B and then are connected with a grounding end GND through a second current source I2, the grid electrode of the second NMOS tube M1 and the grid electrode of the third NMOS tube M2 are connected with the grounding end GND through a first voltage source V0 after being connected with each other, and the drain electrode of the third NMOS tube M2 is connected with the output voltage end OUT.
The output voltage terminal OUT is connected with a power supply voltage terminal VDD of a later stage through a pull-up resistor Rmul. The first voltage source V0 is 5.5V (corresponding to vd0+1v, which may be other values), and the reverse conducting voltage of the first voltage stabilizing tube D0 is 5V (that is, the value of Vd0, which may be other values). The first current source I1 is used for biasing the potential of the first voltage node A, and the second current source I2 is used for biasing the potential of the second voltage node B. The first voltage source V0 is configured to bias the second NMOS transistor M1 and the third NMOS transistor M2, so that the second NMOS transistor M1 and the third NMOS transistor M2 are both turned on.
Fig. 2 shows a circuit connection mode in normal use of the present invention, in which a pull-up resistor Rpull is connected between OUT and the post-stage power supply VDD. The voltage V0 is 5.5V (equal to vd0+1v, but other values are also possible), the reverse conducting voltage for biasing M1 and M2, D0 is about 5V (i.e. the value of Vd0, but other values are also possible), I1 and I2 are current sources, the current value is very small, the potential for biasing the point a and the point B is very small, and M0 is the output stage NMOS.
Considering the situation where VIN is high, M0 is turned off, M1 and M2 of the V0 bias are on, the OUT voltage is equal to VDD minus the voltage drop generated by the bias currents I1 and I2 on the pull-up resistor, and VOUT is high due to the small values of the two bias currents. Point A is pull-down biased by I1 and the current through M1, D0 is in a reverse conducting state, and the point A voltage is equal to VDD minus the clamp voltage of D0, approximately equal to (VDD-5) V (i.e., approximately equal to VDD-Vd 0). The voltage at point B is equal to V0-Vth1, vth1 is approximately equal to 1V, and the VDS differential of M2 is equal to (VDD-4.5) V (namely, VDD-Vd 0).
When VIN is low, M0 is turned on, point a is low, which is approximately equal to GND, the gate voltage of M1 is equal to V0, then M1 is turned on, point B is approximately equal to GND, M2 is also turned on, M0, M1, M2 form a path through which the pull-down current of M0 forms a voltage drop across the pull-up resistor, and since the turn-on current of M0 is large, the voltage drop across the resistor is large, and OUT is low.
The circuit structure of the invention realizes the reduction of the VDS differential pressure of the MOS transistor of the output stage, when the output is high, the maximum VDS of the output pipe is equal to (VDD-4.5) V (namely VDD-Vd 0), and the withstand voltage value of the open drain output stage is improved by 4.5V (namely Vd 0).
What is not described in detail in the present specification belongs to the prior art known to those skilled in the art. It is noted that the above description is helpful for a person skilled in the art to understand the present invention, but does not limit the scope of the present invention. Any and all such equivalent substitutions, modifications and/or deletions as may be made without departing from the spirit and scope of the invention.
Claims (6)
1. The structure for improving the withstand voltage value of the open drain output stage is characterized by comprising a drain electrode of an NMOS (N-channel metal oxide semiconductor) tube of the output stage as a first voltage node, wherein a first path of the first voltage node is connected with an output voltage end through a first voltage stabilizing tube in sequence, a second path of the first voltage node is connected with a grounding end through a first current source in sequence, a source electrode of the NMOS tube of the output stage is connected with the grounding end, a grid electrode of the NMOS tube of the output stage is connected with an output end of an inverter, and an input end of the inverter is connected with an input voltage end.
2. The structure for improving the withstand voltage of an open drain output stage according to claim 1, wherein the first voltage node is connected to a drain electrode of a second NMOS transistor in a third way, a source electrode of the second NMOS transistor and a source electrode of a third NMOS transistor are connected to each other to form a second voltage node and then connected to a ground terminal through a second current source, a gate electrode of the second NMOS transistor and a gate electrode of the third NMOS transistor are connected to each other and then connected to the ground terminal through a first voltage source, and a drain electrode of the third NMOS transistor is connected to the output voltage terminal.
3. The structure for improving withstand voltage of open drain output stage according to claim 1, wherein said output voltage terminal is connected to a power supply voltage terminal of a subsequent stage through a pull-up resistor.
4. The structure for improving the withstand voltage of an open drain output stage according to claim 2, wherein the first voltage source is 5.5V, and the reverse turn-on voltage of the first voltage regulator is 5V.
5. The structure for improving a withstand voltage value of an open drain output stage according to claim 2, wherein the first current source is configured to bias a potential of the first voltage node, and the second current source is configured to bias a potential of the second voltage node.
6. The structure for improving a withstand voltage of an open drain output stage according to claim 2, wherein the first voltage source is configured to bias the second NMOS transistor and the third NMOS transistor so that both the second NMOS transistor and the third NMOS transistor are turned on.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111532890.7A CN116264460A (en) | 2021-12-15 | 2021-12-15 | Structure for improving voltage withstand value of open drain output stage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111532890.7A CN116264460A (en) | 2021-12-15 | 2021-12-15 | Structure for improving voltage withstand value of open drain output stage |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116264460A true CN116264460A (en) | 2023-06-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111532890.7A Pending CN116264460A (en) | 2021-12-15 | 2021-12-15 | Structure for improving voltage withstand value of open drain output stage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116264460A (en) |
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2021
- 2021-12-15 CN CN202111532890.7A patent/CN116264460A/en active Pending
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