CN212381194U - Low-voltage power-on reset circuit - Google Patents
Low-voltage power-on reset circuit Download PDFInfo
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- CN212381194U CN212381194U CN201921819806.8U CN201921819806U CN212381194U CN 212381194 U CN212381194 U CN 212381194U CN 201921819806 U CN201921819806 U CN 201921819806U CN 212381194 U CN212381194 U CN 212381194U
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Abstract
The utility model discloses a low-voltage's last electric reset circuit belongs to the upper reset circuit field, including electric current source, MOS pipe MN0, MOS pipe MN1 and last electric reset circuit, MOS pipe MN0, MOS pipe MN1 are established ties, MOS pipe MN 0's grid and drain electrode, MOS pipe MN 1's grid connect the electric current source, MOS pipe MN 0's source electrode is connected to MOS pipe MN 1's drain electrode, MOS pipe MN 0's drain electrode and MOS pipe MN 1's drain electrode provide different voltage values for last electric reset circuit respectively, it feeds back extremely to go up electric reset circuit output reset signal the electric current source. The utility model discloses produce the voltage difference power supply of two differences, very big reduction power-on reset circuit operating voltage.
Description
Technical Field
The utility model relates to a power-on reset circuit field especially indicates a power-on reset circuit of low-voltage.
Background
In electronic circuits, power-on reset circuits (POR) are often used to detect a power-on process and generate a reset signal to cause the entire circuit to enter a certain state. A simple power-on reset circuit can be realized by charging a capacitor C through a resistor R in the power-on process of a power supply, and when the charging voltage on the capacitor C reaches the threshold voltage of a rear hysteresis comparator, a reset signal is generated. In a conventional power-on reset circuit, the lowest operating voltage is generally determined by the sum of the NMOS threshold voltage and the PMOS threshold voltage of the process. In order to reduce the operating voltage, a low threshold voltage tube can be generally used, such as a native tube, but the cost is high.
SUMMERY OF THE UTILITY MODEL
The utility model provides a power-on reset circuit of low voltage has solved among the prior art in order to reduce operating voltage, generally can use low threshold voltage's pipe, for example consume although, native pipe realizes, but the higher problem of cost ratio.
The technical scheme of the utility model is realized like this:
the utility model provides a power-on reset circuit of low-voltage, includes current source, MOS pipe MN0, MOS pipe MN1 and power-on reset circuit, MOS pipe MN0, MOS pipe MN1 are established ties, MOS pipe MN 0's grid and drain-source resistance, MOS pipe MN 1's grid connection current source, MOS pipe MN 1's drain-source resistance connects MOS pipe MN 0's source electrode, MOS pipe MN 0's drain-source resistance and MOS pipe MN 1's drain-source resistance provide different voltage values for power-on reset circuit respectively, power-on reset circuit output reset signal feeds back to the current source.
As a preferred embodiment of the present invention, the power-on reset circuit includes an MOS transistor MP3-MP7 and an MOS transistor MN2-MN6, the MOS transistor MP3 is connected to the MOS transistor MN2, the MOS transistor MP4 is connected to the MOS transistor MN3, the MOS transistor MP7 is connected to the MOS transistor MN4 and connected to the capacitor C0, the MOS transistor MP5 is connected to the MOS transistor MN5, the MOS transistor MP6 is connected to the MOS transistor MN6, branches formed by the MOS transistors are sequentially connected, a drain of the MOS transistor MN0 is connected to a gate of the MOS transistor MN2, and a drain of the MOS transistor MN1 is connected to a gate of the MOS transistor MN 3; the source of the MOS transistor MP6 and the drain of the MOS transistor MN6 output reset signals to the current source.
As a preferred embodiment of the present invention, the current source includes a first current source and a second current source, the first current source is connected to the gate and the drain of the MOS transistor MN0, the second current source is connected to the gate and the drain of the MOS transistor MN0 through a switch, and the switch is connected to the power-on reset circuit output terminal.
As a preferred embodiment of the present invention, the power-on reset circuit includes an MOS transistor MP3-MP7 and an MOS transistor MN2-MN6, the MOS transistor MP3 is connected to the MOS transistor MN2, the MOS transistor MP4 is connected to the MOS transistor MN3, the MOS transistor MP7 is connected to the MOS transistor MN4 and connected to the capacitor C0, the MOS transistor MP5 is connected to the MOS transistor MN5, the MOS transistor MP6 is connected to the MOS transistor MN6, branches formed by the MOS transistors are sequentially connected, a drain of the MOS transistor MN0 is connected to a gate of the MOS transistor MN2, and a drain of the MOS transistor MN1 is connected to a gate of the MOS transistor MN 3; the source of the MOS transistor MP6 and the drain of the MOS transistor MN6 output a reset signal to a current source, and the output of the current source is connected to the gate of the MOS transistor MP 7.
As a preferred embodiment of the present invention, the current source includes a MOS transistor MP0 and a resistor R0, a source of the MOS transistor MP0 is connected to one end of the resistor R0, the other end of the resistor R0 is grounded, and a drain of the MOS transistor MP0 is connected to drains of the MOS transistors MP3-MP7, respectively.
As a preferred embodiment of the present invention, still include MOS transistor MP1 and MP2, MOS transistor MP 0's source is connected with MOS transistor MP1, MOS transistor MP2 and MOS transistor MP 7's grid respectively, MOS transistor MP 0's grid still connects MOS transistor MP 1's grid, MOS transistor MP 1's source is connected MOS transistor MN 0's drain electrode, MOS transistor MP 2's source is connected through MOS transistor MP8 and is gone up the output of electric reset circuit.
The beneficial effects of the utility model reside in that: two different voltages are generated to supply power respectively, so that the working voltage of the power-on reset circuit is greatly reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a schematic circuit diagram of a first embodiment of a low-voltage power-on reset circuit according to the present invention;
FIG. 2 is a schematic diagram of a power supply voltage and a reset signal;
fig. 3 is a schematic circuit diagram of a second embodiment of the low-voltage power-on reset circuit of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
As shown in fig. 1-3, the utility model provides a low-voltage power-on reset circuit, including the current source, MOS pipe MN0, MOS pipe MN1 and power-on reset circuit, MOS pipe MN0, MOS pipe MN1 establishes ties, MOS pipe MN 0's grid and drain electrode, MOS pipe MN 1's grid connection current source, MOS pipe MN 0's source electrode is connected to MOS pipe MN 1's drain electrode, MOS pipe MN 0's drain electrode and MOS pipe MN 1's drain electrode provide different voltage values for power-on reset circuit respectively, power-on reset circuit outputs reset signal and feeds back to the current source.
Example one
The power-on reset circuit comprises an MOS tube MP3-MP7 and an MOS tube MN2-MN6, wherein the MOS tube MP3 is connected with an MOS tube MN2, an MOS tube MP4 is connected with an MOS tube MN3, the MOS tube MP7 is connected with an MOS tube MN4 and connected with a capacitor C0, an MOS tube MP5 is connected with the MOS tube MN5, an MOS tube MP6 is connected with an MOS tube MN6, branches formed by the MOS tubes are sequentially connected, the drain electrode of the MOS tube MN0 is connected with the gate electrode of the MOS tube MN2, and the drain electrode of the MOS tube MN1 is connected with the gate electrode of the MOS tube MN 3; the source of the MOS transistor MP6 and the drain of the MOS transistor MN6 output reset signals to the current source.
The current source comprises a first current source and a second current source, the first current source is connected with the grid electrode and the drain electrode of the MOS tube MN0, the second current source is connected with the grid electrode and the drain electrode of the MOS tube MN0 through a switch, and the switch is connected with the output end of the power-on reset circuit.
The principle of operation of this circuit is that when the supply voltage rises from zero, the voltage on capacitor C0 is 0V, causing the POR _ OUT output to be low, causing I0 and I2 to begin charging the gates of NMOS MN0 and MN1 at the same time. The gate voltages of the NMOS transistor MN2 and the PMOS transistor MP3 are low, so that the gate voltages of the NMOS transistor MN3 and the PMOS transistor MP4 are high, the NMOS transistor MN4 works in an off state, the PMOS transistor MP7 works in an on state, and the capacitor C0 starts to charge; when the voltage at C0 is high, NMOS transistor MN5 turns on and PMOS transistor MP5 turns off, causing POR _ OUT to toggle from low to high.
When the power supply voltage is reduced from high, the current source I2 is in an off state, and the current source I0 enables the gate voltages of the NMOS transistors MN0 and MN1 to be gradually reduced along with the reduction of the power supply voltage. When the power supply voltage is smaller than VTH2, the gate voltages of MN3 and MP4 change from high to low, so that the NMOS transistor MN4 is turned on, the PMOS transistor MP4 is turned off, and the voltage on the capacitor C0 decreases rapidly. The output of POR _ OUT toggles from high to low.
Example two
The power-on reset circuit comprises an MOS tube MP3-MP7 and an MOS tube MN2-MN6, wherein the MOS tube MP3 is connected with an MOS tube MN2, an MOS tube MP4 is connected with an MOS tube MN3, the MOS tube MP7 is connected with an MOS tube MN4 and connected with a capacitor C0, an MOS tube MP5 is connected with the MOS tube MN5, an MOS tube MP6 is connected with an MOS tube MN6, branches formed by the MOS tubes are sequentially connected, the drain electrode of the MOS tube MN0 is connected with the gate electrode of the MOS tube MN2, and the drain electrode of the MOS tube MN1 is connected with the gate electrode of the MOS tube MN 3; the source of the MOS transistor MP6 and the drain of the MOS transistor MN6 output a reset signal to the current source, and the output of the current source is connected to the gate of the MOS transistor MP 7.
The current source comprises a MOS tube MP0 and a resistor R0, the source electrode of the MOS tube MP0 is connected with one end of the resistor R0, the other end of the resistor R0 is grounded, and the drain electrode of the MOS tube MP0 is respectively connected with the drain electrodes of the MOS tubes MP3-MP 7. The power-on reset circuit further comprises MOS tubes MP1 and MP2, the source electrode of the MOS tube MP0 is connected with the grid electrodes of the MOS tube MP1, the MOS tube MP2 and the MOS tube MP7 respectively, the grid electrode of the MOS tube MP0 is also connected with the grid electrode of the MOS tube MP1, the source electrode of the MOS tube MP1 is connected with the drain electrode of the MOS tube MN0, and the source electrode of the MOS tube MP2 is connected with the output end of the power-on reset circuit through the MOS tube MP 8. The resistor R0 and the PMOS transistor MP0 form a simple current source generating circuit. The current source generates currents with corresponding proportion in MP1, MP2 and MP7 respectively through a current mirror structure formed by PMOS tubes. The innovation of the circuit is that two voltages are generated by using a method of connecting MN0 and MN1 in series and are respectively connected to the gate of MN2 and the gate of MP 3. When the power supply voltage starts to rise from 0, MN0 and MN1 operate in the linear region, so the gate voltage of MN2 is twice the gate voltage of MP 3. When the power supply voltage rises so that MN1 turns on, the gate voltage of MP3 is close to zero and the gate voltage of MN2 is close to the turn-on voltage of MN 1. Compared with the scheme that the gates of the MP3 and the MN2 are connected together, the scheme circuit ensures that the power-on reset circuit can work under lower power supply voltage.
The utility model discloses produce the voltage difference power supply of two differences, very big reduction power-on reset circuit operating voltage.
The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A low-voltage power-on reset circuit is characterized in that: including current source, MOS pipe MN0, MOS pipe MN1 and power-on reset circuit, MOS pipe MN0, MOS pipe MN1 are established ties, MOS pipe MN 0's grid and drain electrode, MOS pipe MN 1's grid connection current source, MOS pipe MN 1's drain electrode connection MOS pipe MN 0's source electrode, MOS pipe MN 0's drain electrode and MOS pipe MN 1's drain electrode provide different voltage values for power-on reset circuit respectively, power-on reset circuit output reset signal feeds back to the current source.
2. A low voltage power-on-reset circuit according to claim 1, wherein: the power-on reset circuit comprises an MOS tube MP3-MP7 and an MOS tube MN2-MN6, wherein the MOS tube MP3 is connected with an MOS tube MN2, the MOS tube MP4 is connected with an MOS tube MN3, the MOS tube MP7 is connected with an MOS tube MN4 and connected with a capacitor C0, the MOS tube MP5 is connected with an MOS tube MN5, the MOS tube MP6 is connected with an MOS tube MN6, branches formed by the MOS tubes are sequentially connected, the drain electrode of the MOS tube MN0 is connected with the gate electrode of the MOS tube MN2, and the drain electrode of the MOS tube MN1 is connected with the gate electrode of the MOS tube MN 3; the source of the MOS transistor MP6 and the drain of the MOS transistor MN6 output reset signals to the current source.
3. A low voltage power-on-reset circuit according to claim 2, wherein: the current source comprises a first current source and a second current source, the first current source is connected with the grid electrode and the drain electrode of the MOS tube MN0, the second current source is connected with the grid electrode and the drain electrode of the MOS tube MN0 through a switch, and the switch is connected with the output end of the power-on reset circuit.
4. A low voltage power-on-reset circuit according to claim 1, wherein: the power-on reset circuit comprises an MOS tube MP3-MP7 and an MOS tube MN2-MN6, wherein the MOS tube MP3 is connected with an MOS tube MN2, the MOS tube MP4 is connected with an MOS tube MN3, the MOS tube MP7 is connected with an MOS tube MN4 and connected with a capacitor C0, the MOS tube MP5 is connected with an MOS tube MN5, the MOS tube MP6 is connected with an MOS tube MN6, branches formed by the MOS tubes are sequentially connected, the drain electrode of the MOS tube MN0 is connected with the gate electrode of the MOS tube MN2, and the drain electrode of the MOS tube MN1 is connected with the gate electrode of the MOS tube MN 3; the source of the MOS transistor MP6 and the drain of the MOS transistor MN6 output a reset signal to a current source, and the output of the current source is connected to the gate of the MOS transistor MP 7.
5. A low voltage power-on-reset circuit according to claim 4, wherein: the current source comprises an MOS tube MP0 and a resistor R0, the source electrode of the MOS tube MP0 is connected with one end of the resistor R0, the other end of the resistor R0 is grounded, and the drain electrode of the MOS tube MP0 is respectively connected with the drain electrodes of the MOS tubes MP3-MP 7.
6. A low voltage power-on-reset circuit according to claim 5, wherein: the power-on reset circuit further comprises MOS tubes MP1 and MP2, the source electrode of the MOS tube MP0 is connected with the grid electrodes of the MOS tube MP1, the MOS tube MP2 and the MOS tube MP7 respectively, the grid electrode of the MOS tube MP0 is also connected with the grid electrode of the MOS tube MP1, the source electrode of the MOS tube MP1 is connected with the drain electrode of the MOS tube MN0, and the source electrode of the MOS tube MP2 is connected with the output end of the power-on reset circuit through the MOS tube MP 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921819806.8U CN212381194U (en) | 2019-10-28 | 2019-10-28 | Low-voltage power-on reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921819806.8U CN212381194U (en) | 2019-10-28 | 2019-10-28 | Low-voltage power-on reset circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212381194U true CN212381194U (en) | 2021-01-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921819806.8U Active CN212381194U (en) | 2019-10-28 | 2019-10-28 | Low-voltage power-on reset circuit |
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| Country | Link |
|---|---|
| CN (1) | CN212381194U (en) |
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2019
- 2019-10-28 CN CN201921819806.8U patent/CN212381194U/en active Active
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Address after: Room 1210-11, 198 Wudong Road, Yangpu District, Shanghai 200433 Patentee after: Shanghai Xinyan Microelectronics Co., Ltd. Address before: Room 1210-11, 198 Wudong Road, Yangpu District, Shanghai 200433 Patentee before: GOCHIP ELECTRONICS TECHNOLOGY CO.,LTD. |