CN103001480A - Soft starting circuit applied in buck type direct current (DC)-DC switch power supply - Google Patents
Soft starting circuit applied in buck type direct current (DC)-DC switch power supply Download PDFInfo
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- CN103001480A CN103001480A CN2012105591441A CN201210559144A CN103001480A CN 103001480 A CN103001480 A CN 103001480A CN 2012105591441 A CN2012105591441 A CN 2012105591441A CN 201210559144 A CN201210559144 A CN 201210559144A CN 103001480 A CN103001480 A CN 103001480A
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Abstract
The invention discloses a soft starting circuit applied in a buck type direct current (DC)-DC switch power supply. The soft starting circuit mainly resolves the problem that overshoot voltage and surge current exist in the existing starting circuit, and static power consumption is too large. The starting circuit comprises a frequency converter circuit, a control circuit and a current-voltage conversion circuit. The first output end of the frequency converter circuit is connected with the control circuit to output a soft starting ending signal OVER, and the second output end of the frequency converter circuit si connected with a current-voltage conversion circuit to output digital signals F1-F7. The first output end of the control circuit is connected with the frequency converter circuit to output a clearing signal clr, the second output end and the third output end of the control circuit are connected with the current-voltage conversion circuit to respectively output a digital signal F8 and a digital signal XF8, and the current-voltage conversion circuit outputs voltage signals VSS. The soft starting circuit adopts the current-voltage conversion circuit, improves output voltage stability, reduces static power consumption, shortens domain area, reduces cost and can be used for simulating an integrated circuit.
Description
Technical field
The invention belongs to the electronic circuit technology field, particularly be applied to the soft starting circuit in the buck DC-DC Switching Power Supply, can be used for analog integrated circuit.
Background technology
In field of switch power, buck DC-DC is simple with it, and efficient, the advantages such as low-power consumption are particularly suitable for Switching Power Supply, but have surge current and overshoot voltage in the circuit start stage, damage internal structure and the external circuit thereof of its place chip.
With reference to Fig. 1, soft starting circuit comprises divider circuit and D/A converting circuit, the first input end of this divider circuit links to each other with the reset signal clr of its place chip, the second input of this divider circuit links to each other with the clock signal clk of its place chip, eight outputs of this divider circuit link to each other with D/A converting circuit respectively, export respectively 8 position digital signal D0～D7; The first input end of this D/A converting circuit links to each other with the reference voltage signal VREF of its place chip, and the second input of this D/A converting circuit links to each other with soft start end signal SS_OVER, the output output voltage signal V of this D/A converting circuit
SSDivider circuit is controlled the clock signal clk of its place chip by the reset signal clr of its place chip, export 8 position digital signal D0～D7 and control respectively conducting and the shutoff of 8 switching tubes in the digital-to-analogue conversion circuit, when soft start end signal SS_OVER works, reference voltage signal VREF and soft start output voltage signal V
SSEnd value identical.
The shortcoming of above-mentioned soft starting circuit mainly is the soft start output voltage V
SSCan not be greater than the reference voltage V REF of its place chip; the reference voltage V REF that is only applicable to its place chip compares as the input of error amplifier and the feedback voltage of its place chip; the reference voltage V REF that is not suitable for its place chip compares as the input of PWM comparator and oblique wave compensation voltage and current sample voltage sum; and the output of error amplifier needs high clamp circuit to carry out high clamping protection; not only increase quiescent current and power consumption, and increased chip area and cost.
Summary of the invention
The object of the present invention is to provide a kind of soft starting circuit that is applied in the buck DC-DC Switching Power Supply, the prior art quiescent current is large, power consumption is large to solve, and the large and high problem of cost of chip area simplifies the complexity of its place chip.
For achieving the above object, the present invention includes: divider circuit 1 and control circuit 2, the first output C of divider circuit 1 links to each other with the first input end E of control circuit 2, exports the soft end signal OVER that opens; The first output G of control circuit 2 links to each other with the first input end B of divider circuit 1, output reset signal clr, it is characterized in that: the second output D of divider circuit 1 and the second output H of control circuit 2, the 3rd output M are connected with respectively current-voltage conversion circuit 3, are used for output voltage signal V
SS
Described current-voltage conversion circuit 3 comprises current source circuit 31, resistor network 32 and high clamped circuit 33, wherein:
High clamped circuit 33 is provided with two inputs and an output, and its output is as the output L of current-voltage conversion circuit 3, output voltage signal V
SS
As preferably, the current source circuit 31 of above-mentioned soft starting circuit is connected to form by 12 PMOS pipe MP1～MP12 and 11 NMOS pipe MN1～MN11, wherein:
The 9th NMOS pipe MN9, the tenth NMOS pipe MN10 and the 11 NMOS pipe MN11, its grid links to each other respectively and consists of current-mirror structure, and its source electrode links to each other respectively, and is connected to ground; The 9th NMOS manages the drain electrode of MN9 as the first input end N of current-voltage conversion circuit 3, and links to each other with the current source IREF of its place chip; The drain electrode of the tenth NMOS pipe MN10 links to each other with the drain electrode of the 12 PMOS pipe MP12;
The one PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the 7th PMOS pipe MP7 and the 12 PMOS pipe MP12, its grid links to each other respectively and consists of current-mirror structure, its source electrode links to each other respectively, and links to each other with the supply voltage VIN of its place chip; The drain electrode of the one PMOS pipe MP1 links to each other with the drain electrode of NMOS pipe MN1; The drain electrode of the 2nd PMOS pipe MP2 links to each other with the drain electrode of the 2nd NMOS pipe MN2; The drain electrode of the 3rd PMOS pipe MP3 links to each other with the drain electrode of the 3rd NMOS pipe MN3; The drain electrode of the 4th PMOS pipe MP4 links to each other with the drain electrode of the 4th NMOS pipe MN4; The drain electrode of the 5th PMOS pipe MP5 links to each other with the drain electrode of the 5th NMOS pipe MN5; The drain electrode of the 6th PMOS pipe MP6 links to each other with the drain electrode of the 6th NMOS pipe MN6; The drain electrode of the 7th PMOS pipe MP7 links to each other with the drain electrode of the 7th NMOS pipe MN7;
The 8th PMOS pipe MP8, the 9th PMOS pipe MP9 and the tenth PMOS pipe MP10, its grid links to each other respectively and consists of current-mirror structure, and its source electrode links to each other respectively, and links to each other with the supply voltage VIN of its place chip; The drain electrode of the 8th PMOS pipe MP8 links to each other with the drain electrode of the 11 NMOS pipe MN11; The drain electrode of the 9th PMOS pipe MP9 links to each other with the drain electrode of the 8th NMOS pipe MN8; The drain electrode of the tenth PMOS pipe MP10 is as the 3rd output of current source circuit 31, output voltage signal V2;
The 11 PMOS manages MP11, and its grid is as the four-input terminal I of current-voltage conversion circuit 3, and links to each other with the digital signal XF8 of control circuit 2 inputs, and its drain electrode links to each other with the grid that the 7th PMOS manages MP7; Its source electrode links to each other with the supply voltage VIN of its place chip;
The one NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 6th NMOS pipe MN6 and the 7th NMOS pipe MN7, its grid links to each other with seven railway digital signal F1～F7 of divider circuit 1 input respectively; Its source electrode is exported respectively seven road current signal I1～I7;
The 8th NMOS manages MN8, and its grid is as the 3rd input J of current-voltage conversion circuit 3, and links to each other with the digital signal F8 of control circuit 2 inputs, and its source electrode is as the second output of current source circuit 31, output current signal I8.
As preferably, the resistor network 32 of above-mentioned soft starting circuit is connected to form by 19 resistance R 1～R19, wherein:
The first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6 and 7 series connection of the 7th resistance R are connected across between the end and ground of the 18 resistance R 18, and an end of the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6 and the 7th resistance R 7 respectively with the corresponding connection of seven road current signal I1～I7 of current source circuit 31 inputs;
The 12 resistance R 12 and 15 series connection of the 15 resistance R are connected across between the other end and ground of the 3rd resistance R 3;
The 9th resistance R 9 and 8 series connection of the 8th resistance R are connected across between the other end and ground of the 4th resistance R 4;
The tenth resistance R 10 and 11 series connection of the 11 resistance R are connected across between the other end and ground of the 5th resistance R 5;
The 13 resistance R 13 and 14 series connection of the 14 resistance R are connected across between the other end and ground of the 6th resistance R 6;
The 16 resistance R 16 and 17 series connection of the 17 resistance R are connected across between the other end and ground of the 7th resistance R 7;
One end of the 18 resistance R 18 is as the output of resistor network 32, output voltage signal V1; The 19 resistance R 19 is connected across between the other end and ground of the 18 resistance R 18.
As preferably, the high clamped circuit 33 of above-mentioned soft starting circuit comprises triode PNP1, the 20 resistance R 20 and capacitor C 1;
Described triode PNP1, its base stage is as the first input end of the clamped circuit 33 of height, and links to each other with the voltage signal V1 of resistor network 32 inputs; Its emitter-base bandgap grading is as the second input of the clamped circuit 33 of height, and links to each other with the voltage signal V2 of current source circuit 31 inputs; Its collector electrode is connected to ground;
1 series connection of described the 20 resistance R 20 and capacitor C is connected across between the emitter-base bandgap grading and ground of triode PNP1, and the common port of the 20 resistance R 20 and capacitor C 1 is as the output L of current-voltage conversion circuit 3, output voltage signal V
SS
As preferably, the control circuit 2 of above-mentioned soft starting circuit comprises rest-set flip-flop RS1, the first inverter I1, the second inverter I2 and NOR gate N1;
Described rest-set flip-flop RS1, its input R be as the first input end E of control circuit 2, and link to each other with the soft end signal OVER that opens of divider circuit 1 input; Its input S is as the second input F of control circuit 2, and links to each other with the cut-off signals SHUT of its place chip; Its output Q links to each other with the input of the first inverter I1;
The output of described the first inverter I1 links to each other output digit signals F8 as the first output H of control circuit 2 with the input of the second inverter I2; The output of the second inverter I2 is as the second output M of control circuit 2, output digit signals XF8;
Described NOR gate N1, its first input end links to each other with the output of the first inverter I1; Its second input links to each other with the cut-off signals SHUT of its place chip; Its output is exported reset signal clr as the 3rd output G of control circuit 2.
The present invention compared with prior art has the following advantages:
1. the present invention has reduced overshoot voltage and surge current owing to adopt current-voltage conversion circuit, has improved the stability of output voltage.
2. the present invention has reduced quiescent current and power consumption owing to be provided with high clamp circuit in current-voltage conversion circuit, has reduced cost, has simplified the complexity of its place chip.
Description of drawings
Fig. 1 is the structured flowchart of conventional softer start-up circuit;
Fig. 2 is the structured flowchart of soft starting circuit of the present invention;
Fig. 3 is control circuit schematic diagram among Fig. 2;
Fig. 4 is the structured flowchart of current-voltage conversion circuit among Fig. 2;
Fig. 5 is the schematic diagram of Fig. 4.
Embodiment
The invention will be further described below in conjunction with accompanying drawing and embodiment.
With reference to Fig. 2, soft starting circuit of the present invention comprises: divider circuit 1, control circuit 2 and current-voltage conversion circuit 3, wherein current-voltage conversion circuit 3 block diagrams as shown in Figure 4, it comprises current source circuit 31, resistor network 32 and high clamped circuit 33, the first input end of this current source circuit 31 is as the first input end N of current-voltage conversion circuit 3, and link to each other with the current source IREF of its place chip, the second input of this current source circuit 31 is as the second input K of current-voltage conversion circuit 3, and link to each other with the digital signal F1 of divider circuit 1 input～F7, the 3rd input of this current source circuit 31 is as the 3rd input J of current-voltage conversion circuit 3, and link to each other with the digital signal F8 of control circuit 2 input, the four-input terminal of this current source circuit 31 is as the four-input terminal I of current-voltage conversion circuit 3, and link to each other with the digital signal XF8 of control circuit 2 input, the first output of this current source circuit 31 links to each other with resistor network 32, output current signal I1～I7, the second output of this current source circuit 31 links to each other with resistor network 32, output current signal I8, the 3rd output of this current source circuit 31 links to each other output voltage signal V2 with the clamped circuit 33 of height; The output of this resistor network 32 links to each other output voltage signal V1 with the clamped circuit 33 of height; The output of the clamped circuit 33 of this height is as the output L of current-voltage conversion circuit 3, output voltage signal V
SSThe first output C of this divider circuit 1 links to each other with the first input end E of control circuit 2, exports the soft end signal OVER that opens; The first output G of control circuit 2 links to each other with the first input end B of divider circuit 1, output reset signal clr.
With reference to Fig. 3, control circuit 2 of the present invention comprises rest-set flip-flop RS1, the first inverter I1, the second inverter I2 and NOR gate N1, wherein:
Rest-set flip-flop RS1, its input R be as the first input end E of control circuit 2, and link to each other with the soft end signal OVER that opens of divider circuit 1 input; Its input S is as the second input F of control circuit 2, and links to each other with the cut-off signals SHUT of its place chip; Its output Q links to each other with the input of the first inverter I1, the soft end signal OVER initial value that opens is low level, when if the cut-off signals SHUT of its place chip is high level, reset signal clr is low level, and divider circuit 1 is not worked, after normal operation recovers in system, cut-off signals SHUT is low, the R end of rest-set flip-flop is low level, and output remains unchanged, and cut-off signals SHUT and digital signal F8 start working frequency divider by two input NOR gate; When divider circuit 1 output soft opened end signal OVER and be high level, the R end of rest-set flip-flop was high level, and the output of rest-set flip-flop is low level, and digital signal F8 becomes high level, and to make reset signal clr be low level, turn-offs divider circuit 1;
The first inverter I1, its output link to each other output digit signals F8 as the first output H of control circuit 2 with the input of the second inverter I2; The output of the second inverter I2 is as the second output M of control circuit 2, output digit signals XF8, and this digital signal F8 and digital signal XF8 are a pair of inversion signals, are used for the size of current of control current source circuit 31;
NOR gate N1, its first input end links to each other with the output of the first inverter I1; Its second input links to each other with the cut-off signals SHUT of its place chip; Its output is exported reset signal clr as the 3rd output G of control circuit 2.
With reference to Fig. 5, the current source circuit 31 in the current-voltage conversion circuit 3 of the present invention, resistor network 32 and high clamped circuit 33, its circuit structure is as follows:
Described current source circuit 31, connected to form by 12 PMOS pipes and 11 NMOS pipes, namely a PMOS manages MP1, the 2nd PMOS manages MP2, the 3rd PMOS manages MP3, the 4th PMOS manages MP4, the 5th PMOS manages MP5, the 6th PMOS manages MP6, the 7th PMOS manages MP7, the 8th PMOS manages MP8, the 9th PMOS manages MP9, the tenth PMOS manages MP10, the 11 PMOS manages MP11, the 12 PMOS manages MP12, the one NMOS manages MN1, the 2nd NMOS manages MN2, the 3rd NMOS manages MN3, the 4th NMOS manages MN4, the 5th NMOS manages MN5, the 6th NMOS manages MN6, the 7th NMOS manages MN7, the 8th NMOS manages MN8, the 9th NMOS manages MN9, the tenth NMOS pipe MN10 and the 11 NMOS pipe MN11, wherein:
The grid of the 9th NMOS pipe MN9, the tenth NMOS pipe MN10 and the 11 NMOS pipe MN11 links to each other respectively and consists of current-mirror structure; The source electrode of the 9th NMOS pipe MN9, the tenth NMOS pipe MN10 and the 11 NMOS pipe MN11 links to each other respectively, and is connected to ground; The 9th NMOS manages the drain electrode of MN9 as the first input end N of current-voltage conversion circuit 3, and links to each other with the current source IREF of its place chip; The drain electrode of the tenth NMOS pipe MN10 links to each other with the drain electrode of the 12 PMOS pipe MP12, and the 9th NMOS pipe MN9, the tenth NMOS pipe MN10 and the 11 NMOS pipe MN11 provide the reference current signal for current source circuit 31;
The grid of the one PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the 7th PMOS pipe MP7 and the 12 PMOS pipe MP12 links to each other respectively and consists of current-mirror structure; The source electrode of the one PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the 7th PMOS pipe MP7 and the 12 PMOS pipe MP12 links to each other respectively, and links to each other with the supply voltage VIN of its place chip; The drain electrode of the one PMOS pipe MP1 links to each other with the drain electrode of NMOS pipe MN1; The drain electrode of the 2nd PMOS pipe MP2 links to each other with the drain electrode of the 2nd NMOS pipe MN2; The drain electrode of the 3rd PMOS pipe MP3 links to each other with the drain electrode of the 3rd NMOS pipe MN3; The drain electrode of the 4th PMOS pipe MP4 links to each other with the drain electrode of the 4th NMOS pipe MN4; The drain electrode of the 5th PMOS pipe MP5 links to each other with the drain electrode of the 5th NMOS pipe MN5; The drain electrode of the 6th PMOS pipe MP6 links to each other with the drain electrode of the 6th NMOS pipe MN6; The drain electrode of the 7th PMOS pipe MP7 links to each other with the drain electrode of the 7th NMOS pipe MN7, and a PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the 7th PMOS pipe MP7 is respectively seven branch roads provides the image current signal;
The grid of the 8th PMOS pipe MP8, the 9th PMOS pipe MP9 and the tenth PMOS pipe MP10 links to each other respectively and consists of current-mirror structure, the source electrode of the 8th PMOS pipe MP8, the 9th PMOS pipe MP9 and the tenth PMOS pipe MP10 links to each other respectively, and links to each other with the supply voltage VIN of its place chip; The drain electrode of the 8th PMOS pipe MP8 links to each other with the drain electrode of the 11 NMOS pipe MN11; The drain electrode of the 9th PMOS pipe MP9 links to each other with the drain electrode of the 8th NMOS pipe MN8; The drain electrode of the tenth PMOS pipe MP10 is as the 3rd output of current source circuit 31, output voltage signal V2;
The 11 PMOS manages MP11, and its grid is as the four-input terminal I of current-voltage conversion circuit 3, and links to each other with the digital signal XF8 of control circuit 2 inputs, and its drain electrode links to each other with the grid that the 7th PMOS manages MP7; Its source electrode links to each other with the supply voltage VIN of its place chip, and the 11 PMOS pipe MP11 is as switching tube, and the digital signal XF8 that is inputted by control circuit 2 controls its turn-on and turn-off;
The grid of the one NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 6th NMOS pipe MN6 and the 7th NMOS pipe MN7 links to each other with seven railway digital signal F1～F7 of divider circuit 1 input respectively; The source electrode of the one NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 6th NMOS pipe MN6 and the 7th NMOS pipe MN7 is exported respectively seven road current signal I1～I7, the one NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 6th NMOS pipe MN6 and the 7th NMOS pipe MN7 be as switching tube, controls conducting and the shutoff of its switching tube by the digital signal F1 of added divider circuit 1 input of its grid～F7;
The 8th NMOS manages MN8, its grid is as the 3rd input J of current-voltage conversion circuit 3, and link to each other with the digital signal F8 of control circuit 2 input, its source electrode is as the second output of current source circuit 31, output current signal I8, the 8th NMOS pipe MN8 is as switching tube, and the digital signal F8 that is inputted by control circuit 2 controls its turn-on and turn-off.
Described resistor network 32, connected to form by 19 resistance R 1～R19, i.e. the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7, the 8th resistance R 8, the 9th resistance R 9, the tenth resistance R 10, the 11 resistance R 11, the 12 resistance R 12, the 13 resistance R 13, the 14 resistance R 14, the 15 resistance R 15, the 16 resistance R 16, the 17 resistance R 17 the 18 resistance R 18 and the 19 resistance R 19, wherein:
The first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6 and 7 series connection of the 7th resistance R are connected across between the end and ground of the 18 resistance R 18, and an end of the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6 and the 7th resistance R 7 respectively with the corresponding connection of seven road current signal I1～I7 of current source circuit 31 inputs;
The 12 resistance R 12 and 15 series connection of the 15 resistance R are connected across between the other end and ground of the 3rd resistance R 3;
The 9th resistance R 9 and 8 series connection of the 8th resistance R are connected across between the other end and ground of the 4th resistance R 4;
The tenth resistance R 10 and 11 series connection of the 11 resistance R are connected across between the other end and ground of the 5th resistance R 5;
The 13 resistance R 13 and 14 series connection of the 14 resistance R are connected across between the other end and ground of the 6th resistance R 6;
The 16 resistance R 16 and 17 series connection of the 17 resistance R are connected across between the other end and ground of the 7th resistance R 7;
One end of the 18 resistance R 18 is as the output of resistor network 32, output voltage signal V1; The 19 resistance R 19 is connected across between the other end and ground of the 18 resistance R 18;
Just start working the stage at soft starting circuit, divider circuit 1 is not worked, and the 8th PMOS pipe MP8 with on the pipe of current mirror to the ten PMOS on its branch road MP10 branch road, makes triode PNP1 work by current-mirror structure, there is not electric current on resistance R 1～R19, voltage signal V
SSEmitter voltage V for triode PNP1
EWhen the cut-off signals SHUT of its place chip is low level, the divider circuit 1 output digit signals F1～F7 that starts working, and conducting and the shutoff of NMOS pipe MN1～the 7th NMOS pipe in the control current-voltage conversion circuit 3.
The clamped circuit 33 of described height comprises triode PNP1, the 20 resistance R 20 and capacitor C 1, wherein:
Triode PNP1, its base stage is as the first input end of the clamped circuit 33 of height, and links to each other with the voltage signal V1 of resistor network 32 inputs; Its emitter-base bandgap grading is as the second input of the clamped circuit 33 of height, and links to each other with the voltage signal V2 of current source circuit 31 inputs; Its collector electrode is connected to ground;
1 series connection of the 20 resistance R 20 and capacitor C is connected across between the emitter-base bandgap grading and ground of triode PNP1, and the common port of the 20 resistance R 20 and capacitor C 1 is as the output L of current-voltage conversion circuit 3, output voltage signal V
SS, after soft start finishes, voltage signal V
SSAs the high clamp signal of soft starting circuit, improved the high efficiency of soft starting circuit.
Specific works principle of the present invention is as follows:
When soft starting circuit has just been started working, the reset signal clr of control circuit 2 outputs is high level, 7 position digital signal F1～F7 and the soft end signal OVER that opens of divider circuit 1 output are low level, behind a clock signal clk, digital signal F1 becomes high level and all the other signals are low level, digital signal F7～F1 is expressed as 0000001 according to binary mode, behind second clock signal clk, the first position digital signal F1 becomes low level, second-order digit signal F2 becomes high level and all the other signals are low level, digital signal F7～F1 is expressed as 0000010 according to binary mode, behind the 3rd clock signal clk, the first position digital signal F1 and second-order digit signal F2 become high level and all the other digital signals are low level, digital signal F7～F1 is expressed as 0000011 according to binary mode, behind clock signal clk of every mistake, binary number adds 1, digital signal F7～F1 represents to change to 1111111 from 0000000 with binary mode, as digital signal F7～when the F1 binary mode is expressed as 1111111, again through behind the clock signal clk, the end signal OVER of divider circuit 1 output is high level, digital signal F7～F1 binary mode is expressed as 0000000, the voltage signal V of digital signal F7～F1 control current-voltage conversion circuit 3 outputs
SSApproximately linear rises, and the soft end signal OVER that opens makes the reset signal clr of control circuit 2 outputs become low level, turn-offs divider circuit 1; After divider circuit 1 recovers normal operation, cut-off signals SHUT is low level, the R end of rest-set flip-flop is low level, output remains unchanged, it is high level that cut-off signals SHUT and digital signal F8 make the soft end signal OVER that opens of divider circuit 1 output by two input NOR gate, and the R end of rest-set flip-flop is high level, and the output of rest-set flip-flop is low level, digital signal F8 becomes high level, and to make reset signal clr be low level, turn-offs divider circuit 1; Digital signal XF8 and digital signal F8 acting in conjunction make the voltage signal V of current-voltage conversion circuit 3 outputs
SSStable, soft start-up process finishes.When if cut-off signals SHUT is high level at any time, reset signal clr is low level, turn-offs divider circuit 1, and the output of rest-set flip-flop remains unchanged, and then digital signal F8 and digital signal XF8 are also constant, the voltage signal V of current-voltage conversion circuit 3 outputs
SSConstant, soft start-up process finishes, voltage signal V
SSCan be used as high clamp signal.
Just start working the stage at soft starting circuit, divider circuit 1 is not worked, the 8th PMOS pipe MP8 in the current-voltage conversion circuit 3 manages current mirror to the ten PMOS on its branch road on the MP10 branch road by current-mirror structure, make triode PNP1 work, there is not electric current on resistance R 1～R19, so output voltage is the emitter voltage V of triode PNP1
EWhen cut-off signals SHUT is low level, conducting and the shutoff of NMOS pipe MN1～MN7 in the digital signal F1 of divider circuit 1 output～F7 control current-voltage conversion circuit 3.7 road electric currents of digital signal F1～F7 control correspond to respectively I1～I7, and the resistance of establishing resistance first resistance R 1～the 19 resistance R 19 is identical all to be R, by Dai Weinan equivalence, the output voltage V of current-voltage conversion circuit 3 in the soft start-up process
SSFor:
V wherein
BEBe the voltage difference between triode PNP1 emitter-base bandgap grading and the base stage.
If the value of the electric current I 1～I7 on PMOS pipe MP1～the 7th PMOS pipe MP7 branch road is I
IN1, electric current is I on the 9th NMOS pipe MN9, the tenth NMOS pipe MN10 and the 11 NMOS pipe MN11 branch road
IN2, make I
IN1=I
IN2=I, conducting and shutoff according to digital signal F1～F7 controls NMOS pipe MN1～the 8th NMOS pipe MN8 make output voltage V
SSThe approximately linear ladder rises, when through 127 all after date output voltage V
SSBe reduced to:
In the formula, V
BEBe the voltage difference between triode PNP1 emitter-base bandgap grading and the base stage.Through behind the clock signal clk, the voltage of digital signal F7～F1 becomes low level by high level again, and the voltage of digital signal F8 becomes high level by low level, and the voltage of digital signal XF8 becomes low level by high level.This moment is by the 11 PMOS pipe MP11 conducting of digital signal XF8 end control, the grid voltage of the one PMOS pipe MP1～the 7th PMOS pipe MP7 and the 20 PMOS pipe MP20 is drawn high, digital signal F8 controls the 8th NMOS pipe MN8 conducting, 2 times of electric current I flow through resistor network 32, make the output voltage ladder that risen again, then the output voltage of soft start by 128 all after dates is:
V
SS=2IR+V
BE
Be the voltage signal V that guarantees that soft starting circuit is exported in temperature range
SSStable, the temperature coefficient of resistance in the resistance in the resistance network and its place chip base modules is consistent.
Below only be a preferred example of the present invention, do not consist of any limitation of the invention, obviously under design of the present invention, can carry out different changes and improvement to its circuit, but these are all at the row of protection of the present invention.
Claims (5)
1. soft starting circuit that is applied in the buck DC-DC Switching Power Supply, comprise divider circuit (1) and control circuit (2), the first output C of divider circuit (1) links to each other with the first input end E of control circuit (2), exports the soft end signal OVER that opens; The first output G of control circuit (2) links to each other with the first input end B of divider circuit (1), output reset signal clr, it is characterized in that: the second output D of divider circuit (1) and the second output H of control circuit (2), the 3rd output M are connected with respectively current-voltage conversion circuit (3), are used for output voltage signal V
SS
Described current-voltage conversion circuit (3) comprises current source circuit (31), resistor network (32) and high clamped circuit (33), wherein:
Current source circuit (31), be provided with four inputs and three outputs, its first input end is as the first input end N of current-voltage conversion circuit (3), and link to each other with the current source IREF of its place chip, its second input is as the second input K of current-voltage conversion circuit (3), and link to each other with the digital signal F1 of divider circuit (1) input～F7, its the 3rd input is as the 3rd input J of current-voltage conversion circuit (3), and link to each other with the digital signal F8 of control circuit (2) input, its four-input terminal is as the four-input terminal I of current-voltage conversion circuit (3), and link to each other with the digital signal XF8 of control circuit (2) input, its first output links to each other with resistor network (32), output current signal I1～I7, its second output links to each other with resistor network (32), output current signal I8, its 3rd output links to each other output voltage signal V2 with high clamped circuit (33);
Resistor network (32) is provided with two inputs and an output, and its output links to each other output voltage signal V1 with high clamped circuit (33);
High clamped circuit (33) is provided with two inputs and an output, and its output is as the output L of current-voltage conversion circuit (3), output voltage signal V
SS
2. soft starting circuit according to claim 1 is characterized in that current source circuit (31), connected to form by 12 PMOS pipe MP1～MP12 and 11 NMOS pipe MN1～MN11, wherein:
The 9th NMOS pipe MN9, the tenth NMOS pipe MN10 and the 11 NMOS pipe MN11, its grid links to each other respectively and consists of current-mirror structure, and its source electrode links to each other respectively, and is connected to ground; The 9th NMOS manages the drain electrode of MN9 as the first input end N of current-voltage conversion circuit (3), and links to each other with the current source IREF of its place chip; The drain electrode of the tenth NMOS pipe MN10 links to each other with the drain electrode of the 12 PMOS pipe MP12;
The one PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the 7th PMOS pipe MP7 and the 12 PMOS pipe MP12, its grid links to each other respectively and consists of current-mirror structure, its source electrode links to each other respectively, and links to each other with the supply voltage VIN of its place chip; The drain electrode of the one PMOS pipe MP1 links to each other with the drain electrode of NMOS pipe MN1; The drain electrode of the 2nd PMOS pipe MP2 links to each other with the drain electrode of the 2nd NMOS pipe MN2; The drain electrode of the 3rd PMOS pipe MP3 links to each other with the drain electrode of the 3rd NMOS pipe MN3; The drain electrode of the 4th PMOS pipe MP4 links to each other with the drain electrode of the 4th NMOS pipe MN4; The drain electrode of the 5th PMOS pipe MP5 links to each other with the drain electrode of the 5th NMOS pipe MN5; The drain electrode of the 6th PMOS pipe MP6 links to each other with the drain electrode of the 6th NMOS pipe MN6; The drain electrode of the 7th PMOS pipe MP7 links to each other with the drain electrode of the 7th NMOS pipe MN7;
The 8th PMOS pipe MP8, the 9th PMOS pipe MP9 and the tenth PMOS pipe MP10, its grid links to each other respectively and consists of current-mirror structure, and its source electrode links to each other respectively, and links to each other with the supply voltage VIN of its place chip; The drain electrode of the 8th PMOS pipe MP8 links to each other with the drain electrode of the 11 NMOS pipe MN11; The drain electrode of the 9th PMOS pipe MP9 links to each other with the drain electrode of the 8th NMOS pipe MN8; The drain electrode of the tenth PMOS pipe MP10 is as the 3rd output of current source circuit (31), output voltage signal V2;
The 11 PMOS manages MP11, and its grid is as the four-input terminal I of current-voltage conversion circuit (3), and links to each other with the digital signal XF8 of control circuit (2) input, and its drain electrode links to each other with the grid that the 7th PMOS manages MP7; Its source electrode links to each other with the supply voltage VIN of its place chip;
The one NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 6th NMOS pipe MN6 and the 7th NMOS pipe MN7, its grid links to each other with seven railway digital signal F1～F7 of divider circuit (1) input respectively; Its source electrode is exported respectively seven road current signal I1～I7;
The 8th NMOS manages MN8, its grid is as the 3rd input J of current-voltage conversion circuit (3), and link to each other with the digital signal F8 of control circuit (2) input, its source electrode is as the second output of current source circuit (31), output current signal I8.
3. soft starting circuit according to claim 1 is characterized in that resistor network (32), connected to form by 19 resistance R 1～R19, wherein:
The first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6 and 7 series connection of the 7th resistance R are connected across between the end and ground of the 18 resistance R 18, and an end of the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6 and the 7th resistance R 7 respectively with the corresponding connection of seven road current signal I1～I7 of current source circuit (31) input;
The 12 resistance R 12 and 15 series connection of the 15 resistance R are connected across between the other end and ground of the 3rd resistance R 3;
The 9th resistance R 9 and 8 series connection of the 8th resistance R are connected across between the other end and ground of the 4th resistance R 4;
The tenth resistance R 10 and 11 series connection of the 11 resistance R are connected across between the other end and ground of the 5th resistance R 5;
The 13 resistance R 13 and 14 series connection of the 14 resistance R are connected across between the other end and ground of the 6th resistance R 6;
The 16 resistance R 16 and 17 series connection of the 17 resistance R are connected across between the other end and ground of the 7th resistance R 7;
One end of the 18 resistance R 18 is as the output of resistor network (32), output voltage signal V1; The 19 resistance R 19 is connected across between the other end and ground of the 18 resistance R 18.
4. soft starting circuit according to claim 1 is characterized in that high clamped circuit (33), comprises triode PNP1, the 20 resistance R 20 and capacitor C 1;
Described triode PNP1, its base stage is as the first input end of the clamped circuit of height (33), and links to each other with the voltage signal V1 of resistor network (32) input; Its emitter-base bandgap grading is as the second input of the clamped circuit of height (33), and links to each other with the voltage signal V2 of current source circuit (31) input; Its collector electrode is connected to ground;
1 series connection of described the 20 resistance R 20 and capacitor C is connected across between the emitter-base bandgap grading and ground of triode PNP1, and the common port of the 20 resistance R 20 and capacitor C 1 is as the output L of current-voltage conversion circuit (3), output voltage signal V
SS
5. soft starting circuit according to claim 1 is characterized in that control circuit (2), comprises rest-set flip-flop RS1, the first inverter I1, the second inverter I2 and NOR gate N1;
Described rest-set flip-flop RS1, its input R be as the first input end E of control circuit (2), and link to each other with the soft end signal OVER that opens of divider circuit (1) input; Its input S is as the second input F of control circuit (2), and links to each other with the cut-off signals SHUT of its place chip; Its output Q links to each other with the input of the first inverter I1;
The output of described the first inverter I1 links to each other output digit signals F8 as the first output H of control circuit (2) with the input of the second inverter I2; The output of the second inverter I2 is as the second output M of control circuit (2), output digit signals XF8;
Described NOR gate N1, its first input end links to each other with the output of the first inverter I1; Its second input links to each other with the cut-off signals SHUT of its place chip; Its output is exported reset signal clr as the 3rd output G of control circuit (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201210559144.1A CN103001480B (en) | 2012-12-20 | 2012-12-20 | Soft starting circuit applied in buck type direct current (DC)-DC switch power supply |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210559144.1A CN103001480B (en) | 2012-12-20 | 2012-12-20 | Soft starting circuit applied in buck type direct current (DC)-DC switch power supply |
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| CN103001480A true CN103001480A (en) | 2013-03-27 |
| CN103001480B CN103001480B (en) | 2015-04-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210559144.1A Active CN103001480B (en) | 2012-12-20 | 2012-12-20 | Soft starting circuit applied in buck type direct current (DC)-DC switch power supply |
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| CN108769873A (en) * | 2018-05-23 | 2018-11-06 | 歌尔股份有限公司 | A kind of signal switching circuit and electronic equipment |
| CN113904309A (en) * | 2021-10-15 | 2022-01-07 | 无锡力芯微电子股份有限公司 | Soft start circuit capable of suppressing surge current and overshoot voltage |
| CN116566368A (en) * | 2023-05-24 | 2023-08-08 | 韬润半导体(无锡)有限公司 | Switching circuit and multiplexer |
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| CN108769873A (en) * | 2018-05-23 | 2018-11-06 | 歌尔股份有限公司 | A kind of signal switching circuit and electronic equipment |
| CN108769873B (en) * | 2018-05-23 | 2020-08-25 | 歌尔股份有限公司 | Signal switching circuit and electronic equipment |
| CN113904309A (en) * | 2021-10-15 | 2022-01-07 | 无锡力芯微电子股份有限公司 | Soft start circuit capable of suppressing surge current and overshoot voltage |
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| CN116566368A (en) * | 2023-05-24 | 2023-08-08 | 韬润半导体(无锡)有限公司 | Switching circuit and multiplexer |
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| Publication number | Publication date |
|---|---|
| CN103001480B (en) | 2015-04-08 |
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