CN105092937A - Full-cycle current detection circuit - Google Patents
Full-cycle current detection circuit Download PDFInfo
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Abstract
The invention relates to the field of microelectronics technology, and particularly relates to a full-cycle current detection circuit. The full-cycle current detection circuit comprises an inductive current rising pattern current detection circuit and an inductive current declining pattern current detection circuit. According to the technical scheme of the invention, the full-cycle current detection circuit is designed based on the circuit multiplexing manner, thus being simple in structure, small in circuit size and low in power consumption. In the inductive current rising detection mode, the channel resistance of a power MOS transistor is adopted as the sampling resistance, so that the power loss caused by the extra adoption of the sampling resistance can be eliminated. In the inductive current declining detection mode, the inductive current can be sampled based on the current mirror detection method. The value of the sampled current is equal to the value of the inductive current that is scaled down by 4000 times. Therefore, the power consumption of the sampling circuit is reduced.
Description
Technical field
The invention belongs to microelectronics technology, particularly a kind of complete period current detection circuit.
Background technology
Dc-dc a kind ofly DC input voitage is transformed into the electric pressure converter effectively exporting fixing DC voltage, and because of it, to have efficiency high, and volume is little, the advantage that output ripple is little, and is widely used in various portable mobile termianl.
In order to improve the dynamic response of dc-dc, there has been proposed current-mode control mode, common mainly contains: Peak Current Mode, average current mould and sluggish current-mode three kinds of control modes.The loop stability that sluggish current-mode control mode has had, dynamic response faster, is therefore usually used in high precision dc-dc.But how efficiently sluggish current-mode control mode needs to carry out complete period detection to inductive current, detect inductive current accurately, most important to the design of high precision dc-dc.
Summary of the invention
Goal of the invention: the object of the invention is to design one simply, efficiently, complete period current detection circuit accurately, thus solve the problem of current detecting in sluggish current-mode DC-DC converter.
Technical scheme: a kind of complete period current detection circuit, comprises inductive current ascending fashion current detection circuit and inductive current drop mode current detection circuit,
Inductive current ascending fashion current detection circuit comprises inductance L, NMOS power tube M1, NMOS tube Mn1, NMOS tube Mn2, NMOS tube Mn3, NMOS tube Mn4, NMOS tube Mn7, PMOS Mp1, PMOS Mp2, PMOS Mp3, PMOS Mp4, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5 and electric capacity C
One termination input voltage vin of inductance L, the drain electrode of another termination NMOS power tube M1, the source ground of NMOS power tube M1, the grid of NMOS power tube M1 meets control signal NPG01;
The grid of NMOS tube Mn3 and the drain electrode short circuit of NMOS tube Mn3, the grid of NMOS tube Mn4 and the drain electrode short circuit of NMOS tube Mn4, the grid of NMOS tube Mn3 is connected with the grid of NMOS tube Mn1, the grid of NMOS tube Mn2, the drain electrode of PMOS Mp3 respectively, the grid of NMOS tube Mn4 is connected with the grid of NMOS tube Mn1, the grid of NMOS tube Mn2, the drain electrode of PMOS Mp3 respectively, one end of the source electrode connecting resistance R1 of PMOS Mp3, another termination output voltage Vout of resistance R1, the grid of PMOS Mp3 meets bias voltage bias1;
The source electrode of NMOS tube Mn1, the source ground of NMOS tube Mn3, the source electrode of NMOS tube Mn2, the source electrode of NMOS tube Mn4 connect the drain electrode of NMOS power tube M1; The grid of PMOS Mp1 and the drain electrode short circuit of PMOS Mp1, the grid of PMOS Mp1 is connected with the grid of PMOS Mp2, the drain electrode of NMOS tube Mn1 respectively, one end of the source electrode connecting resistance R2 of PMOS Mp1, another termination output voltage Vout of resistance R2;
The drain electrode of NMOS tube Mn2 and the drain electrode short circuit of PMOS Mp2, the drain electrode of NMOS tube Mn2 is connected with the grid of NMOS tube Mn7, one end of electric capacity C respectively, the other end ground connection of electric capacity C, one end of the source electrode connecting resistance R3 of PMOS Mp2, another termination output voltage Vout of resistance R3;
The drain electrode of PMOS Mp4 and the drain electrode short circuit of NMOS tube Mn7 are as the output of current detecting, one end of the source electrode connecting resistance R5 of NMOS tube Mn7, the other end ground connection of resistance R5, one end of the source electrode connecting resistance R4 of PMOS Mp4, another termination output voltage Vout of resistance R4, the grid of PMOS Mp4 meets bias voltage bias2
Inductive current drop mode current detection circuit, comprise inductance L, NMOS synchronous rectification power tube M2, NMOS sampling pipe Ms2, NMOS tube Mn1, NMOS tube Mn2, NMOS tube Mn3, NMOS tube Mn4, NMOS tube Mn7, PMOS Mp1, PMOS Mp2, PMOS Mp3, PMOS Mp4, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5 and electric capacity C
One termination input voltage vin of inductance L, the other end of inductance L connects the drain electrode of NMOS synchronous rectification power tube M2, the drain electrode of NMOS sampling pipe Ms2 respectively, the source electrode of NMOS tube Mn2 meets output voltage Vout, the grid of NMOS synchronous rectifier M2 meets control signal NPG02, the source electrode of NMOS sampling pipe Ms2 is connected with one end of resistance R3, PMOS Mp2 source electrode respectively, the grid of NMOS sampling pipe Ms2 meets control signal NPG02, another termination output voltage Vout of resistance R3;
The grid of NMOS tube Mn3 and the drain electrode short circuit of NMOS tube Mn3, the grid of NMOS tube Mn4 and the drain electrode short circuit of NMOS tube Mn4, the grid of NMOS tube Mn4 is connected with the drain electrode of PMOS Mp3 with the grid of NMOS tube Mn1, the grid of NMOS tube Mn2 respectively, the grid of NMOS tube Mn3 is connected with the drain electrode of PMOS Mp3 with the grid of NMOS tube Mn1, the grid of NMOS tube Mn2 respectively, one end of the source electrode connecting resistance R1 of PMOS Mp3, another termination output voltage Vout of resistance R1, the grid of PMOS Mp3 meets bias voltage bias1;
The source electrode of NMOS tube Mn1, the source electrode of NMOS tube Mn2, the source electrode of NMOS tube Mn3, the source grounding of NMOS tube Mn4;
The grid of PMOS Mp1 and the drain electrode short circuit of PMOS Mp1, the grid of PMOS Mp1 is connected with the grid of PMOS Mp2, the drain electrode of NMOS tube Mn1 respectively, one end of the source electrode connecting resistance R2 of PMOS Mp1, another termination output voltage Vout of resistance R2;
The drain electrode of NMOS tube Mn2 and the drain electrode short circuit of PMOS Mp2, the drain electrode of NMOS tube Mn2 is connected with the grid of NMOS tube Mn7 one end with electric capacity C, the other end ground connection of electric capacity C;
The drain electrode of PMOS Mp4 and the drain electrode short circuit of NMOS tube Mn7 are as the output of current detecting, one end of the source electrode connecting resistance R5 of NMOS tube Mn7, the other end ground connection of resistance R5, one end of the source electrode connecting resistance R4 of PMOS Mp4, another termination output voltage Vout of resistance R4, the grid of PMOS Mp4 meets bias voltage bias2.
A kind of preferred version as complete period current detection circuit a kind of in the present invention: described inductive current ascending fashion current detection circuit adopts the parasitic channel resistance of NMOS power tube M1 to sample to inductive current.
A kind of preferred version as complete period current detection circuit a kind of in the present invention: described inductive current drop mode current detection circuit adopts current mirror sensed method to sample to inductive current.
A kind of preferred version as complete period current detection circuit a kind of in the present invention: in inductive current drop mode current detection circuit, the source electrode of NMOS sampling pipe Ms2 and NMOS synchronous rectification power tube M2 is held with SW and is connected, the drain terminal connecting resistance R3 of NMOS sampling pipe Ms2, the drain terminal of NMOS synchronous rectifier M2 and the other end of resistance R3 all meet output voltage Vout; Wherein the breadth length ratio of NMOS sampling pipe Ms2 and NMOS synchronous rectification power tube M2 is 1:4000.
A kind of preferred version as complete period current detection circuit a kind of in the present invention: when carrying out inductive current rise detection, the source electrode of NMOS tube Mn2 connects SW end, and now two inputs of amplifier are respectively the source electrode of Mn1 and the source electrode of Mn2; When carry out inductive current decline detect time, the source ground of NMOS tube Mn2, now two of the amplifier two ends being input as resistance R3.
Further, R4 and Mp4 is current source load, and R5 is source degeneration resistor.
Realize of the present inventionly devising a kind of new complete period current detection circuit structure, described current detecting adopts the mode of circuit multiplexer, reduces circuit scale, reduces overall power.Whole circuit comprises inductive current rise detection pattern and inductive current decline detecting pattern, exports and is connected to a two-stage calculation amplifier.Wherein inductive current rise detection pattern adopts power tube parasitic channel resistance to sample to inductive current, and inductive current decline detecting pattern adopts current mirror sensed method to sample to inductive current.First order amplifier is common gate operational amplifier configuration, and the second level adopts the commonsource amplifier structure of current source load.
Beneficial effect: a kind of complete period current detection circuit disclosed by the invention has following beneficial effect:
1, complete period current detection circuit adopts the mode of circuit multiplexer, and structure is simple, and circuit scale is little, low in energy consumption;
2, inductive current rise detection pattern utilizes self channel resistance of power MOS pipe as sampling resistor, eliminates the power attenuation that additional sampling resistor brings;
3, inductive current decline detecting pattern adopts current mirror sensed method to sample to inductive current, and sample rate current is the value after inductive current scaled down 4000 times, is conducive to the power consumption reducing sample circuit.
Accompanying drawing explanation
Fig. 1 is the application of a kind of complete period current detection circuit disclosed by the invention in dc-dc;
Fig. 2 is the circuit diagram of a kind of complete period current detection circuit disclosed by the invention;
Fig. 3 a is the circuit reduction under inductive current rise detection pattern of the present invention;
Fig. 3 b is the detailed circuit diagram at P place in Fig. 3 a;
Fig. 4 a is the circuit reduction under inductive current decline detecting pattern of the present invention;
Fig. 4 b is the detailed circuit diagram at Q place in Fig. 4 a;
Fig. 5 is the circuit simulation under inductive current rise detection pattern of the present invention;
Fig. 6 is the circuit simulation under inductive current decline detecting pattern of the present invention;
Fig. 7 is complete period current detection circuit emulation of the present invention.
Embodiment:
Below the specific embodiment of the present invention is described in detail.
As shown in figures 1-4, a kind of complete period current detection circuit, comprises inductive current ascending fashion current detection circuit and inductive current drop mode current detection circuit,
Inductive current ascending fashion current detection circuit comprises inductance L, NMOS power tube M1, NMOS tube Mn1, NMOS tube Mn2, NMOS tube Mn3, NMOS tube Mn4, NMOS tube Mn7, PMOS Mp1, PMOS Mp2, PMOS Mp3, PMOS Mp4, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5 and electric capacity C
One termination input voltage vin of inductance L, the drain electrode of another termination NMOS power tube M1, the source ground of NMOS power tube M1, the grid of NMOS power tube M1 meets control signal NPG01;
The grid of NMOS tube Mn3 and the drain electrode short circuit of NMOS tube Mn3, the grid of NMOS tube Mn4 and the drain electrode short circuit of NMOS tube Mn4, the grid of NMOS tube Mn3 is connected with the grid of NMOS tube Mn1, the grid of NMOS tube Mn2, the drain electrode of PMOS Mp3 respectively, the grid of NMOS tube Mn4 is connected with the grid of NMOS tube Mn1, the grid of NMOS tube Mn2, the drain electrode of PMOS Mp3 respectively, one end of the source electrode connecting resistance R1 of PMOS Mp3, another termination output voltage Vout of resistance R1, the grid of PMOS Mp3 meets bias voltage bias1;
The source electrode of NMOS tube Mn1, the source ground of NMOS tube Mn3, the source electrode of NMOS tube Mn2, the source electrode of NMOS tube Mn4 connect the drain electrode of NMOS power tube M1; The grid of PMOS Mp1 and the drain electrode short circuit of PMOS Mp1, the grid of PMOS Mp1 is connected with the grid of PMOS Mp2, the drain electrode of NMOS tube Mn1 respectively, one end of the source electrode connecting resistance R2 of PMOS Mp1, another termination output voltage Vout of resistance R2;
The drain electrode of NMOS tube Mn2 and the drain electrode short circuit of PMOS Mp2, the drain electrode of NMOS tube Mn2 is connected with the grid of NMOS tube Mn7, one end of electric capacity C respectively, the other end ground connection of electric capacity C, one end of the source electrode connecting resistance R3 of PMOS Mp2, another termination output voltage Vout of resistance R3;
The drain electrode of PMOS Mp4 and the drain electrode short circuit of NMOS tube Mn7 are as the output of current detecting, one end of the source electrode connecting resistance R5 of NMOS tube Mn7, the other end ground connection of resistance R5, one end of the source electrode connecting resistance R4 of PMOS Mp4, another termination output voltage Vout of resistance R4, the grid of PMOS Mp4 meets bias voltage bias2
Inductive current drop mode current detection circuit, comprise inductance L, NMOS synchronous rectification power tube M2, NMOS sampling pipe Ms2, NMOS tube Mn1, NMOS tube Mn2, NMOS tube Mn3, NMOS tube Mn4, NMOS tube Mn7, PMOS Mp1, PMOS Mp2, PMOS Mp3, PMOS Mp4, resistance R1, resistance R2, resistance R3 (under this pattern, R3 is sampling resistor), resistance R4, resistance R5 and electric capacity C
One termination input voltage vin of inductance L, the other end of inductance L connects the drain electrode of NMOS synchronous rectification power tube M2, the drain electrode of NMOS sampling pipe Ms2 respectively, the source electrode of NMOS tube Mn2 meets output voltage Vout, the grid of NMOS synchronous rectifier M2 meets control signal NPG02, the source electrode of NMOS sampling pipe Ms2 is connected with one end of resistance R3, PMOS Mp2 source electrode respectively, the grid of NMOS sampling pipe Ms2 meets control signal NPG02, another termination output voltage Vout of resistance R3;
The grid of NMOS tube Mn3 and the drain electrode short circuit of NMOS tube Mn3, the grid of NMOS tube Mn4 and the drain electrode short circuit of NMOS tube Mn4, the grid of NMOS tube Mn4 is connected with the drain electrode of PMOS Mp3 with the grid of NMOS tube Mn1, the grid of NMOS tube Mn2 respectively, the grid of NMOS tube Mn3 is connected with the drain electrode of PMOS Mp3 with the grid of NMOS tube Mn1, the grid of NMOS tube Mn2 respectively, one end of the source electrode connecting resistance R1 of PMOS Mp3, another termination output voltage Vout of resistance R1, the grid of PMOS Mp3 meets bias voltage bias1;
The source electrode of NMOS tube Mn1, the source electrode of NMOS tube Mn2, the source electrode of NMOS tube Mn3, the source grounding of NMOS tube Mn4;
The grid of PMOS Mp1 and the drain electrode short circuit of PMOS Mp1, the grid of PMOS Mp1 is connected with the grid of PMOS Mp2, the drain electrode of NMOS tube Mn1 respectively, one end of the source electrode connecting resistance R2 of PMOS Mp1, another termination output voltage Vout of resistance R2;
The drain electrode of NMOS tube Mn2 and the drain electrode short circuit of PMOS Mp2, the drain electrode of NMOS tube Mn2 is connected with the grid of NMOS tube Mn7 one end with electric capacity C, the other end ground connection of electric capacity C;
The drain electrode of PMOS Mp4 and the drain electrode short circuit of NMOS tube Mn7 are as the output of current detecting, one end of the source electrode connecting resistance R5 of NMOS tube Mn7, the other end ground connection of resistance R5, one end of the source electrode connecting resistance R4 of PMOS Mp4, another termination output voltage Vout of resistance R4, the grid of PMOS Mp4 meets bias voltage bias2.
Further, inductive current ascending fashion current detection circuit adopts the parasitic channel resistance of NMOS power tube M1 to sample to inductive current.
Further, inductive current drop mode current detection circuit adopts current mirror sensed method to sample to inductive current.
Further, in inductive current drop mode current detection circuit, the source electrode of NMOS sampling pipe Ms2 and NMOS synchronous rectification power tube M2 is held with SW and is connected, the drain terminal connecting resistance R3 of NMOS sampling pipe Ms2, and the drain terminal of NMOS synchronous rectifier M2 and the other end of resistance R3 all meet output voltage Vout; Wherein the breadth length ratio of NMOS sampling pipe Ms2 and NMOS synchronous rectification power tube M2 is 1:4000.
Further, when carrying out inductive current rise detection, the source electrode of NMOS tube Mn2 connects SW end, and now two inputs of amplifier are respectively the source electrode of Mn1 and the source electrode of Mn2; When carry out inductive current decline detect time, the source ground of NMOS tube Mn2, now two of the amplifier two ends being input as resistance R3.
Further, R4 and Mp4 is current source load, and R5 is source degeneration resistor.
With reference to Fig. 1, the application example of complete period current detection circuit of the present invention in dc-dc.
With reference to Fig. 2, complete period current detection circuit of the present invention comprises: inductive current ascent stage sample circuit, inductive current decline stage sample circuit, multiplexing common gate operational amplifier and output common source operational amplifier.Wherein:
Inductive current ascent stage sample circuit is large scale NMOS power tube with reference to Fig. 3 a and Fig. 3 b:M1; NMOS tube Mn1, Mn2, PMOS Mp1, Mp2 and resistance R2, R3 form common gate operational amplifier, and positive-negative input end connects the source electrode of Mn2 and Mn1 respectively; Mp3 and R1 be common gate amplifier produce bias current, Mn3 and Mn4 by bias current mirror image for common gate amplifier provides biased.
Inductive current decline stage sample circuit is NMOS synchronous rectification power tube with reference to Fig. 4 a and Fig. 4 b:M2, and Ms2 is image current sampling pipe, and R3 is sampling resistor; NMOS tube Mn1, Mn2, PMOS Mp1, Mp2 and resistance R1 form common gate operational amplifier, the source electrode of positive-negative input end difference R2 and Mp2; Mp3 and R1 is that common gate amplifier produces bias current, Mn3 and Mn4 is by the current mirror load of bias current mirror image as common gate amplifier.
Export the current source load that common source operational amplifier is second level amplifier with reference to Fig. 2, Mp4 and R4, Mn7 is the input pipe of second level common source amplifier, and R5 is source degeneration resistance.
With reference to Fig. 2, total current testing circuit principle of work of the present invention is as follows:
When NPG01 is high level, because NPG01 and NPG02 is two-phase high level non-overlapping clock, now NPG02 is low level, NMOS power tube M1 opens, and inductive current rises.Mn6 turns off, and Mn5 opens, and the source electrode of Mn2 and Mn4 connects SW signal, the source ground of Mn1 and Mn3, after circuit reduction as shown in Figure 3 a.
When NPG02 is high level, now NPG01 is low level, and M2 opens, and inductive current declines.Mn7 and Mn6 opens, and Mn5 turns off, the source grounding of Mn1-Mn4, after circuit reduction as shown in fig. 4 a.
With reference to Fig. 3 a and Fig. 3 b, inductive current ascent stage sample circuit principle of work of the present invention is as follows:
When NPG01 saltus step is high, NMOS power tube M1 opens, and inductive current rises; Pass through, the parasitic channel resistance effect of NMOS power tube M1 obtains voltage Vsw:
Wherein Ron is, NMOS power tube M1 parasitic channel resistance.Due to, NMOS power tube M1 is in dark linear zone, so parasitic channel resistance value is substantially constant, therefore voltage Vsw linearly rises with inductive current IL.Finally by two stage amplifer by Vsw Linear Amplifer.
With reference to Fig. 4, inductive current decline stage sample circuit principle of work of the present invention is as follows:
When NPG02 saltus step is high, M2 and NMOS sampling pipe Ms2 opens, and inductive current is that output load is powered, and electric current declines; NMOS sampling pipe Ms2 mirror image inductive current, by resistance R3, is converted into sampled voltage Vs by sample rate current.
Inductive current drop mode current detection circuit adopts current mirror sensed method to sample to inductive current.Implementation method as shown in Figure 4, wherein NMOS synchronous rectification power tube M2, NMOS sampling pipe Ms2 and resistance R3 forms current mirror sample circuit, due to the drain and gate short circuit respectively of NMOS synchronous rectification power tube M2, NMOS sampling pipe Ms2, therefore the electric current flowing through NMOS sampling pipe Ms2 flows through the electric current of NMOS synchronous rectification power tube M2 by the scaled mirror of 1:4000, then converts electric current to voltage Vsen by resistance R3.
In order to reduce the power consumption of sample circuit, the value of sample rate current and sampling resistor is all very little, and therefore sampled voltage is also very little, finally by two stage amplifer by sampled voltage Linear Amplifer.
The main simulation results of low voltage operational amplifier of the present invention is as follows:
Give the simulation result of inductive current ascent stage current sample with reference to Fig. 5, can find out, be in dark linear zone, the channel resistance of NMOS power tube M1 is about 0.2 Ω, and Vsen is the output of current detecting.
The simulation result of inductive current decline stage current sample is given with reference to Fig. 6, can find out, sample rate current has gone out inductive current with the good mirror image of the ratio of 1:4000, then converts sampled voltage to by sampling resistor, then obtains current detecting through two stage amplifer and exports Vsen.
With reference to the main output waveform that Fig. 7 is complete period current detection circuit, can find out, inductive current IL is well converted to sampling and outputting voltage Vsen.
By above design and simulation result test, achieve the characteristic of complete period current detecting.
Above embodiments of the present invention are elaborated.But the present invention is not limited to above-mentioned embodiment, in the ken that art those of ordinary skill possesses, can also make a variety of changes under the prerequisite not departing from present inventive concept.
Claims (5)
1. a complete period current detection circuit, is characterized in that, comprises inductive current ascending fashion current detection circuit and inductive current drop mode current detection circuit,
Inductive current ascending fashion current detection circuit comprises inductance L, NMOS power tube M1, NMOS tube Mn1, NMOS tube Mn2, NMOS tube Mn3, NMOS tube Mn4, NMOS tube Mn7, PMOS Mp1, PMOS Mp2, PMOS Mp3, PMOS Mp4, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5 and electric capacity C
One termination input voltage vin of inductance L, the drain electrode of another termination NMOS power tube M1, the source ground of NMOS power tube M1, the grid of NMOS power tube M1 meets control signal NPG01; The grid of NMOS tube Mn3 and the drain electrode short circuit of NMOS tube Mn3, the grid of NMOS tube Mn4 and the drain electrode short circuit of NMOS tube Mn4, the grid of NMOS tube Mn3 is connected with the grid of NMOS tube Mn1, the grid of NMOS tube Mn2, the drain electrode of PMOS Mp3 respectively, the grid of NMOS tube Mn4 is connected with the grid of NMOS tube Mn1, the grid of NMOS tube Mn2, the drain electrode of PMOS Mp3 respectively, one end of the source electrode connecting resistance R1 of PMOS Mp3, another termination output voltage Vout of resistance R1, the grid of PMOS Mp3 meets bias voltage bias1; The source electrode of NMOS tube Mn1, the source ground of NMOS tube Mn3, the source electrode of NMOS tube Mn2, the source electrode of NMOS tube Mn4 connect the drain electrode of NMOS power tube M1; The grid of PMOS Mp1 and the drain electrode short circuit of PMOS Mp1, the grid of PMOS Mp1 is connected with the grid of PMOS Mp2, the drain electrode of NMOS tube Mn1 respectively, one end of the source electrode connecting resistance R2 of PMOS Mp1, another termination output voltage Vout of resistance R2; The drain electrode of NMOS tube Mn2 and the drain electrode short circuit of PMOS Mp2, the drain electrode of NMOS tube Mn2 is connected with the grid of NMOS tube Mn7, one end of electric capacity C respectively, the other end ground connection of electric capacity C, one end of the source electrode connecting resistance R3 of PMOS Mp2, another termination output voltage Vout of resistance R3; The drain electrode of PMOS Mp4 and the drain electrode short circuit of NMOS tube Mn7 are as the output of current detecting, one end of the source electrode connecting resistance R5 of NMOS tube Mn7, the other end ground connection of resistance R5, one end of the source electrode connecting resistance R4 of PMOS Mp4, another termination output voltage Vout of resistance R4, the grid of PMOS Mp4 meets bias voltage bias2;
Inductive current drop mode current detection circuit, comprise inductance L, NMOS synchronous rectification power tube M2, NMOS sampling pipe Ms2, NMOS tube Mn1, NMOS tube Mn2, NMOS tube Mn3, NMOS tube Mn4, NMOS tube Mn7, PMOS Mp1, PMOS Mp2, PMOS Mp3, PMOS Mp4, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5 and electric capacity C
One termination input voltage vin of inductance L, the other end of inductance L connects the drain electrode of NMOS synchronous rectification power tube M2, the drain electrode of NMOS sampling pipe Ms2 respectively, the source electrode of NMOS tube Mn2 meets output voltage Vout, the grid of NMOS synchronous rectifier M2 meets control signal NPG02, the source electrode of NMOS sampling pipe Ms2 is connected with one end of resistance R3, PMOS Mp2 source electrode respectively, the grid of NMOS sampling pipe Ms2 meets control signal NPG02, another termination output voltage Vout of resistance R3; The grid of NMOS tube Mn3 and the drain electrode short circuit of NMOS tube Mn3, the grid of NMOS tube Mn4 and the drain electrode short circuit of NMOS tube Mn4, the grid of NMOS tube Mn4 is connected with the drain electrode of PMOS Mp3 with the grid of NMOS tube Mn1, the grid of NMOS tube Mn2 respectively, the grid of NMOS tube Mn3 is connected with the drain electrode of PMOS Mp3 with the grid of NMOS tube Mn1, the grid of NMOS tube Mn2 respectively, one end of the source electrode connecting resistance R1 of PMOS Mp3, another termination output voltage Vout of resistance R1, the grid of PMOS Mp3 meets bias voltage bias1; The source electrode of NMOS tube Mn1, the source electrode of NMOS tube Mn2, the source electrode of NMOS tube Mn3, the source grounding of NMOS tube Mn4; The grid of PMOS Mp1 and the drain electrode short circuit of PMOS Mp1, the grid of PMOS Mp1 is connected with the grid of PMOS Mp2, the drain electrode of NMOS tube Mn1 respectively, one end of the source electrode connecting resistance R2 of PMOS Mp1, another termination output voltage Vout of resistance R2; The drain electrode of NMOS tube Mn2 and the drain electrode short circuit of PMOS Mp2, the drain electrode of NMOS tube Mn2 is connected with the grid of NMOS tube Mn7 one end with electric capacity C, the other end ground connection of electric capacity C; The drain electrode of PMOS Mp4 and the drain electrode short circuit of NMOS tube Mn7 are as the output of current detecting, one end of the source electrode connecting resistance R5 of NMOS tube Mn7, the other end ground connection of resistance R5, one end of the source electrode connecting resistance R4 of PMOS Mp4, another termination output voltage Vout of resistance R4, the grid of PMOS Mp4 meets bias voltage bias2.
2. a kind of complete period current detection circuit according to claim 1, is characterized in that, described inductive current ascending fashion current detection circuit adopts the parasitic channel resistance of NMOS power tube M1 to sample to inductive current.
3. a kind of complete period current detection circuit according to claim 1, it is characterized in that, in inductive current drop mode current detection circuit, the source electrode of NMOS sampling pipe Ms2 and NMOS synchronous rectification power tube M2 is held with SW and is connected, the drain terminal connecting resistance R3 of NMOS sampling pipe Ms2, the drain terminal of NMOS synchronous rectifier M2 and the other end of resistance R3 all meet output voltage Vout; Wherein the breadth length ratio of NMOS sampling pipe Ms2 and NMOS synchronous rectification power tube M2 is 1:4000.
4. a kind of complete period current detection circuit according to claim 1, is characterized in that, when carrying out inductive current rise detection, the source electrode of NMOS tube Mn2 connects SW end, and now two inputs of amplifier are respectively the source electrode of Mn1 and the source electrode of Mn2; When carry out inductive current decline detect time, the source ground of NMOS tube Mn2, now two of the amplifier two ends being input as resistance R3.
5. a kind of complete period current detection circuit according to claim 4, it is characterized in that, R4 and Mp4 is current source load, and R5 is source degeneration resistor.
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| CN108226609A (en) * | 2017-12-27 | 2018-06-29 | 上海贝岭股份有限公司 | For the current detection circuit of DC-DC converter |
| CN108957102A (en) * | 2018-08-28 | 2018-12-07 | 长沙理工大学 | A kind of current detection circuit of no amplifier |
| CN111200369A (en) * | 2018-11-16 | 2020-05-26 | 恩智浦有限公司 | Low-voltage-drop rectifier |
| CN114167125A (en) * | 2021-07-29 | 2022-03-11 | 沈阳工业大学 | Current detection circuit |
| CN114640247A (en) * | 2022-04-26 | 2022-06-17 | 合肥工业大学 | Full-period inductive current sampling circuit |
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| CN106950414A (en) * | 2017-02-24 | 2017-07-14 | 深圳陆巡科技有限公司 | Metal-oxide-semiconductor current sampling circuit and push-pull circuit |
| CN106950414B (en) * | 2017-02-24 | 2020-11-17 | 深圳陆巡科技有限公司 | MOS tube current sampling circuit and push-pull circuit |
| CN108226609A (en) * | 2017-12-27 | 2018-06-29 | 上海贝岭股份有限公司 | For the current detection circuit of DC-DC converter |
| CN108226609B (en) * | 2017-12-27 | 2020-02-07 | 上海贝岭股份有限公司 | Current detection circuit for DC-DC converter |
| CN108957102A (en) * | 2018-08-28 | 2018-12-07 | 长沙理工大学 | A kind of current detection circuit of no amplifier |
| CN108957102B (en) * | 2018-08-28 | 2024-03-08 | 长沙理工大学 | Current detection circuit without operational amplifier |
| CN111200369A (en) * | 2018-11-16 | 2020-05-26 | 恩智浦有限公司 | Low-voltage-drop rectifier |
| CN111200369B (en) * | 2018-11-16 | 2023-03-10 | 恩智浦有限公司 | Low-voltage-drop rectifier |
| CN114167125A (en) * | 2021-07-29 | 2022-03-11 | 沈阳工业大学 | Current detection circuit |
| CN114167125B (en) * | 2021-07-29 | 2023-12-12 | 沈阳工业大学 | Current detection circuit |
| CN114640247A (en) * | 2022-04-26 | 2022-06-17 | 合肥工业大学 | Full-period inductive current sampling circuit |
| CN114640247B (en) * | 2022-04-26 | 2024-03-29 | 合肥工业大学 | Full-period inductive current sampling circuit |
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