CN103066851B - Control circuit for primary side flyback type converter - Google Patents

Abstract

The invention discloses a control circuit for a primary side flyback type converter. The control circuit for the primary side flyback type converter mainly solves the problem of output linear pressure dropping existing in a prior primary side flyback type converter. The circuit comprises an error amplifier EA, a voltage sampling module (1), a current sampling module (2), a pulse width modulation (PWM) comparator (3), an oblique wave compensation module (4), a logic drive module (5) and an output linear pressure dropping compensation circuit (8). The voltage sampling module (1) and the output linear pressure dropping compensation circuit (8) are respectively connected with the error amplifier EA. The current sampling module (2) is connected with the oblique wave compensation module (4). The error amplifier EA and the oblique wave compensation module (4) are respectively connected with the PWM comparator (3). An output end of the PWM comparator (3) is connected with the logic drive module (5). The logic drive module (5) outputs a drive signal to control a first N-mental oxide semiconductor (NMOS) tube MN1 at the periphery. The control circuit for the primary side flyback type converter is capable of effectively compensating the output linear pressure dropping of the primary side flyback type converter.

Description

For the control circuit of former limit inverse excitation type converter

Technical field

The invention belongs to electronic circuit technology field, relate to analog integrated circuit, particularly a kind of control circuit for former limit inverse excitation type converter.

Background technology

Former limit inverse excitation type converter, as one very important power management class circuit, because it has the advantages such as structure is simple, with low cost, is widely used in small-power power and various power supply adaptor.Former limit inverse excitation type converter utilizes primary side to assist winding, output voltage is sampled, avoid and directly output voltage is sampled in primary side, effectively can reduce the component number of transformation system, the PCB surface reducing transformation system circuit board is amassed and can the operating efficiency of Lifting Transform system.Part most crucial in the inverse excitation type converter of former limit is control circuit, and the research therefore for the control circuit of former limit inverse excitation type converter is more and more concerned.

Figure 1 shows that the topology diagram of control circuit for former limit inverse excitation type converter and peripheral components, comprise voltage sample module, current sample module, PWM comparator, error amplifier EA, oblique wave compensation module, logical drive module, peripheral three end transformers, peripheral NMOS tube and peripheral output line; Voltage sample module assists winding L to peripheral three end transformers _aon voltage sample, the drain current of current sample module to peripheral NMOS tube is sampled, output current sampled signal V4 is to oblique wave compensation module, oblique wave compensation module and error amplifier EA are all connected with PWM comparator, PWM comparator exports control signal V6 to logical drive module, this logical drive module output drive signal V7, this drive singal V7 controls the drain current of peripheral NMOS tube.

In practical application, because peripheral output line is longer, when peripheral output line flows through electric current, voltage drop will be produced on peripheral output line, the under-voltage protection of former limit inverse excitation type converter late-class circuit may be triggered, cause whole converting system not work.

Summary of the invention:

The object of the invention is to the deficiency for above-mentioned control circuit, propose a kind of control circuit for former limit inverse excitation type converter, to realize compensating the output line pressure drop of former limit inverse excitation type converter, ensure that the late-class circuit of former limit inverse excitation type converter and whole converting system normally work.

For achieving the above object, the present invention includes: error amplifier EA, voltage sample module 1, current sample module 2, PWM comparator 3, oblique wave compensation module 4 and logical drive module 5; Voltage sample module 1 output voltage sampled signal V2 is to the inverting input of error amplifier EA, first output output current sampled signal V4 of current sample module 2 is to oblique wave compensation module 4, the output of oblique wave compensation module 4 and error amplifier EA is all connected with PWM comparator 3, PWM comparator 3 exports control signal V6 to logical drive module 5, is controlled the normal work of former limit inverse excitation type converter by logical drive module 5 output drive signal V7; It is characterized in that: the second output of current sample module 2 is connected with output line voltage-drop compensation circuit 8, this output line voltage-drop compensation circuit 8 output reference voltage VREF1 to the in-phase input end of error amplifier EA, to compensate the output line pressure drop of former limit inverse excitation type converter;

Described output line voltage-drop compensation circuit 8, comprises Voltage to current transducer module 81 and reference voltage compensation module 82; The compensating signal VIO that second output of current sample module 2 exports is converted to current signal I4 to reference voltage compensation module 82 by Voltage to current transducer module 81; Current signal I4 is converted to the in-phase input end that reference voltage V REF1 inputs to error amplifier EA by reference voltage compensation module 82.

As preferably, above-mentioned Voltage to current transducer module 81, comprising: the first operational amplifier OP1, the first PMOS MP1, the second PMOS MP2, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 3rd resistance R3 and the first reference current I1; Wherein:

The compensating signal VIO that in-phase input end and current sample module 2 second output of described first operational amplifier OP1 export is connected, its inverting input is connected with the source electrode of the second NMOS tube MN2 with one end of the 3rd resistance R3 respectively, the other end ground connection of the 3rd resistance R3, the output of the first operational amplifier OP1 is connected with the grid of the second NMOS tube MN2;

The grid of described second PMOS MP2 is connected with the drain electrode of the drain electrode of the first PMOS MP1, grid and the second NMOS tube MN2 respectively, the drain electrode of the second PMOS MP2 is connected with the drain electrode of the 4th NMOS tube MN4, as the output output current signal I4 of Voltage to current transducer module 81;

The grid of the grid of described 3rd NMOS tube MN3, drain electrode and the 4th NMOS tube MN4 is all connected with the negative terminal of the first reference current I1, the anode of the first reference current I1 is connected with the supply voltage VDD of its place chip, first PMOS MP1 is all connected with the supply voltage VDD of its place chip with the source electrode of the second PMOS MP2, the source grounding of the 3rd NMOS tube MN3 and the 4th NMOS tube MN4.

As preferably, said reference voltage compensation module 82, comprising: the second operational amplifier OP2, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 5th NMOS tube MN5, the 3rd PMOS MP3, the 4th PMOS MP4 and buffer 821;

The current signal I4 that the in-phase input end of described second operational amplifier OP2 and one end of the 4th resistance R4 all input with Voltage to current transducer module 81 is connected, the inverting input of the second operational amplifier OP2 is connected with the source electrode of the 5th NMOS tube MN5 with one end of the 5th resistance R5 respectively, and the output of the second operational amplifier OP2 is connected with the grid of the 5th NMOS tube MN5;

The grid of described 4th PMOS MP4 is connected with the drain electrode of the drain electrode of the 3rd PMOS MP3, grid and the 5th NMOS tube MN5 respectively, the drain electrode of the 4th PMOS MP4 is connected with one end of the 6th resistance R6, as the output output reference signal VREF1 of reference voltage compensation module 82, the 3rd PMOS MP3 is all connected with the supply voltage VDD of its place chip with the source electrode of the 4th PMOS MP4;

The input of described buffer 821 is connected with the input voltage VREF of its place chip, and its output is connected to the other end of the 6th resistance R6;

The other end of described 4th resistance R4 and the equal ground connection of the other end of the 5th resistance R5.

The present invention, owing to the addition of output line voltage-drop compensation circuit, can compensate the output line pressure drop of former limit inverse excitation type converter, ensure that the late-class circuit of former limit inverse excitation type converter and whole converting system normally work.

Accompanying drawing explanation

Fig. 1 is the topology diagram of existing control circuit;

Fig. 2 is topology diagram of the present invention;

Fig. 3 is instance graph of the present invention;

Fig. 4 is the circuit theory diagrams of Voltage to current transducer module in the present invention;

Fig. 5 is the circuit theory diagrams of reference voltage compensation module in the present invention.

Embodiment

Referring to accompanying drawing and embodiment, the invention will be further described.

With reference to Fig. 2, control circuit of the present invention comprises: error amplifier EA, voltage sample module 1, current sample module 2, PWM comparator 3, oblique wave compensation module 4, logical drive module 5 and output line voltage-drop compensation circuit 8; Voltage sample module 1 is all connected with error amplifier EA with output line voltage-drop compensation circuit 8, current sample module 2 is connected to oblique wave compensation module 4, error amplifier EA is all connected with PWM comparator 3 with oblique wave compensation module 4, the output of PWM comparator 3 is connected to logical drive module 5, and logical drive module 5 output drive signal V7 controls the drain current of the first NMOS tube MN1.

Described output line voltage-drop compensation circuit 8, comprises Voltage to current transducer module 81 and reference voltage compensation module 82; Voltage to current transducer module 81 is connected with reference voltage compensation module 82, and the output of reference voltage compensation module 82 is connected to error amplifier EA as the output of output line voltage-drop compensation circuit 8.

Fig. 3 gives an application example of control circuit of the present invention, input voltage V _aCoutput filtering signal V after the rectification of rectifier bridge BR ₁to the primary side coil L of three end transformers 9 _p, three end transformer 9 primary side coil L _pbe connected with the first NMOS tube MN1, three end transformer 9 secondary side coil L _son voltage through rectifier diode D _rrectification after output transform voltage V8 to output line 6, the voltage sample module 1 in control circuit is to three end transformer 9 primary side coil L _pon voltage sample, output voltage sampled signal V2 is to the inverting input of error amplifier EA, and this voltage sampling signal V2 obtains the in-phase input end that error signal V3 is input to PWM comparator 3 after the preliminary amplification of error amplifier EA; The drain current of current sample module 2 to the first NMOS tube MN1 in control circuit is sampled, first output output current sampled signal V4 of this current sample module 2 is to oblique wave compensation module 4, and its second output exports compensating signal VIO to Voltage to current transducer module 81; Oblique wave compensation module 4 couples of current sampling signal V4 carry out oblique wave compensation, and export ramp signal V5 to the inverting input of PWM comparator 3, oblique wave compensation module 4 improves the stability of whole control circuit; Voltage on reference voltage compensation module 82 pairs of output lines 6 compensates, and output reference voltage VREF1 is to the in-phase input end of error amplifier EA; The output of oblique wave compensation module 4 and the output of error amplifier EA are all connected with PWM comparator 3, PWM comparator 3 is by comparing ramp signal V5 and error signal V3, export control signal V6 to logical drive module 5, logical drive module 5 improves the driving force of control signal V6, and this logical drive module 5 output controls the size of the first NMOS tube MN1 drain current as the output output drive signal V7 of control circuit.

With reference to Fig. 4, Voltage to current transducer module 81 of the present invention, including, but not limited to the first operational amplifier OP1, the first PMOS MP1, the second PMOS MP2, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 3rd resistance R3 and the first reference current I1;

The described normal phase input end of the first operational amplifier OP1 is connected with the second output of current sample module 2, its inverting input is connected with the source electrode of the second NMOS tube MN2 with one end of the 3rd resistance R3 respectively, the other end ground connection of the 3rd resistance R3, the output of the first operational amplifier OP1 is connected with the grid of the second NMOS tube MN2, and the compensating signal VIO that current sample module 2 second output exports is converted to the electric current flowing through the 3rd resistance R3 by the second NMOS tube MN2 by the first operational amplifier OP1;

The grid of described second PMOS MP2 is connected with the drain electrode of the drain electrode of the first PMOS MP1, grid and the second NMOS tube MN2 respectively, first PMOS MP1 and the second PMOS MP2 forms current mirror, the drain electrode of the second PMOS MP2 is connected with the drain electrode of the 4th NMOS tube MN4, as the output output current signal I4 of Voltage to current transducer module 81;

The grid of the grid of described 3rd NMOS tube MN3, drain electrode and the 4th NMOS tube MN4 is all connected with the negative terminal of the first reference current I1,3rd NMOS tube MN3 and the 4th NMOS tube MN4 forms current mirror, the anode of the first reference current I1, the source electrode of the first PMOS MP1 are all connected with the supply voltage VDD of its place chip with the source electrode of the second PMOS MP2, the source grounding of the 3rd NMOS tube MN3 and the 4th NMOS tube MN4.

With reference to Fig. 5, reference voltage compensation module 82 of the present invention, including, but not limited to the second operational amplifier OP2, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 5th NMOS tube MN5, the 3rd PMOS MP3, the 4th PMOS MP4 and buffer 821;

The current signal I4 that the in-phase input end of described second operational amplifier OP2 all inputs with Voltage to current transducer module 81 with one end of the 4th resistance R4 is connected, the inverting input of the second operational amplifier OP2 is connected with the source electrode of the 5th NMOS tube MN5 with one end of the 5th resistance R5 respectively, the output of the second operational amplifier OP2 is connected with the grid of the 5th NMOS tube MN5, and current signal I4 is converted to by the 5th NMOS tube MN5 the electric current flowing through the 5th resistance R5 by the second operational amplifier OP2;

The grid of described 4th PMOS MP4 is connected with the drain electrode of the drain electrode of the 3rd PMOS MP3, grid and the 5th NMOS tube MN5 respectively, 3rd PMOS MP3 is all connected with the supply voltage VDD of its place chip with the source electrode of the 4th PMOS MP4,3rd PMOS MP3 and the 4th PMOS MP4 forms current mirror, the drain electrode of the 4th PMOS MP4 is connected with one end of the 6th resistance R6, as the output output reference signal VREF1 of reference voltage compensation module 82, this reference signal VREF1 is the reference signal containing output line voltage-drop compensation;

The input of described buffer 821 is connected with the input voltage VREF of its place chip, and its output is connected to the other end of the 6th resistance R6, and buffer 821 improves the driving force of the input voltage VREF of its place chip;

The other end of described 4th resistance R4 and the equal ground connection of the other end of the 5th resistance R5.

Operation principle of the present invention is as follows:

With reference to Fig. 3, rectifier diode D _rthe voltage of transformation V8 exported can be expressed as:

V8=Vo+Io·R _cable1)

Wherein, Vo is the load voltage that output line 6 exports, and Io is the electric current that load 7 is flow through, R _cablefor the equivalent resistance of output line 6.

Rectifier diode D _rthe difference of the load voltage that the voltage of transformation V8 exported and output line 6 export is output line pressure drop Δ V, and output line pressure drop Δ V can be expressed as:

ΔV=Io·R _cable2)

The voltage variety Δ V that output line pressure drop Δ V causes at the inverting input of error amplifier EA _fBcan be expressed as:

Wherein, N _abe that winding L assisted by three end transformers 9 _athe number of turn, N _sbe three end transformer 9 secondary side coil L _sthe number of turn, R1, R2 are respectively the first resistance R1, the second resistance R2, V _dRfor rectifier diode D _ron voltage.

Simultaneous formula 2) and formula 3), by the voltage variety Δ V that output line pressure drop Δ V causes at the inverting input of error amplifier EA _fBcan be expressed as:

${\mathrm{\ΔV}}_{\mathrm{FB}}=\frac{N_A}{N_S}\·\frac{R2}{R1+R2}\·(\mathrm{Io}\·R_{\mathrm{cable}}-V_{\mathrm{DR}})---4)$

With reference to Fig. 4, the current signal I4 that Voltage to current transducer module 81 exports can be expressed as:

$I4=\frac{\mathrm{kp}2}{\mathrm{kp}1}\·\frac{\mathrm{VIO}}{R3}-\frac{\mathrm{kn}4}{\mathrm{kn}3}\·\mathrm{Ibias}1---5)$

Wherein, kp1 is the breadth length ratio of the first PMOS MP1, and kp2 is the breadth length ratio of the second PMOS MP2, and kn3 is the breadth length ratio of the 3rd NMOS tube MN3, and kn4 is the breadth length ratio of the 4th NMOS tube MN4, and R3 is the 3rd resistance R3, I1 is the first reference current I1.

With reference to Fig. 5, the difference DELTA V of the input voltage VREF of the reference voltage V REF1 that reference voltage compensation module 82 exports and its place chip _rEFcan be expressed as:

${\mathrm{\ΔV}}_{\mathrm{REF}}=\frac{\mathrm{kp}4\·\mathrm{kp}2}{\mathrm{kp}3\·\mathrm{kp}1}\·\frac{R4\·R6}{R5\·R3}\·\mathrm{VIO}-\frac{\mathrm{kp}4\·\mathrm{kn}4}{\mathrm{kp}3\·\mathrm{kn}3}\·\frac{R4}{R5}\·R6\·\mathrm{Ibias}1---6)$

Wherein, kp3 is the breadth length ratio of the 3rd PMOS MP3, and kp4 is the breadth length ratio of the 4th PMOS MP4, and R4, R5 and R6 are respectively the 4th resistance R4, the 5th resistance R5 and the 6th resistance R6.

In practical application, the selection of kp1, kp2, kp3, kp4, kn3, kn4, R4, R5, R6 and I1 need meet formula 7) and formula 8):

$\frac{\mathrm{kp}4\·\mathrm{kp}2}{\mathrm{kp}3\·\mathrm{kp}1}\·\frac{R4\·R6}{R5\·R3}=\frac{N_A}{N_S}\·\frac{R2}{R1+R2}\·\frac{\mathrm{VIO}}{\mathrm{Io}}\·R_{\mathrm{cable}}---7)$

$\frac{\mathrm{kp}4\·\mathrm{kn}4}{\mathrm{kp}3\·\mathrm{kn}3}\·\frac{R4}{R5}\·R6\·\mathrm{Ibias}1=\frac{N_A}{N_S}\·\frac{R2}{R1+R2}\·V_{\mathrm{DR}}---8)$

Simultaneous formula 4), formula 6), formula 7) and formula 8), the difference DELTA V of input voltage VREF of the reference voltage V REF1 that reference voltage compensation module 82 exports and its place chip _rEFcan be expressed as:

ΔV _REF＝ΔV _FB9)

From formula 9), the difference DELTA V of the input voltage VREF of the reference voltage V REF1 that reference voltage compensation module 82 exports and its place chip _rEFthe output line pressure drop of former limit inverse excitation type converter is compensated, ensure that the late-class circuit of former limit inverse excitation type converter and whole converting system normally work.

Below be only a preferred example of the present invention, do not form any limitation of the invention, obviously under design of the present invention, different changes and improvement can be carried out to its circuit, but these are all at the row of protection of the present invention.

Claims (3)

1., for a control circuit for former limit inverse excitation type converter, comprise error amplifier EA, voltage sample module (1), current sample module (2), PWM comparator (3), oblique wave compensation module (4) and logical drive module (5); Voltage sample module (1) output voltage sampled signal V2 is to the inverting input of error amplifier EA, first output output current sampled signal V4 of current sample module (2) is to oblique wave compensation module (4), the output of oblique wave compensation module (4) and error amplifier EA is all connected with PWM comparator (3), PWM comparator (3) exports control signal V6 to logical drive module (5), is controlled the normal work of former limit inverse excitation type converter by logical drive module (5) output drive signal V7; It is characterized in that: the second output of current sample module (2) is connected with output line voltage-drop compensation circuit (8), this output line voltage-drop compensation circuit (8) output reference voltage VREF1 to the in-phase input end of error amplifier EA, to compensate the output line pressure drop of former limit inverse excitation type converter;

Described output line voltage-drop compensation circuit (8), comprises Voltage to current transducer module (81) and reference voltage compensation module (82); The compensating signal VIO that second output of current sample module (2) exports is converted to current signal I4 to reference voltage compensation module (82) by Voltage to current transducer module (81); Current signal I4 is converted to the in-phase input end that reference voltage V REF1 inputs to error amplifier EA by reference voltage compensation module (82); The difference DELTA V of the input voltage VREF of this reference voltage V REF1 and its place chip _rEFthe output line pressure drop of former limit inverse excitation type converter is compensated, ensure that the late-class circuit of former limit inverse excitation type converter and whole converting system normally work.

2. the control circuit according to claims 1, it is characterized in that Voltage to current transducer module (81), comprising: the first operational amplifier OP1, the first PMOS MP1, the second PMOS MP2, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 3rd resistance R3 and the first reference current I1;

The compensating signal VIO that in-phase input end and current sample module (2) second output of described first operational amplifier OP1 export is connected, its inverting input is connected with the source electrode of the second NMOS tube MN2 with one end of the 3rd resistance R3 respectively, the other end ground connection of the 3rd resistance R3, the output of the first operational amplifier OP1 is connected with the grid of the second NMOS tube MN2;

The grid of described second PMOS MP2 is connected with the drain electrode of the drain electrode of the first PMOS MP1, grid and the second NMOS tube MN2 respectively, the drain electrode of the second PMOS MP2 is connected with the drain electrode of the 4th NMOS tube MN4, as the output output current signal I4 of Voltage to current transducer module (81);

The grid of the grid of described 3rd NMOS tube MN3, drain electrode and the 4th NMOS tube MN4 is all connected with the negative terminal of the first reference current I1, the anode of the first reference current I1 is connected with the supply voltage VDD of its place chip, first PMOS MP1 is all connected with the supply voltage VDD of its place chip with the source electrode of the second PMOS MP2, the source grounding of the 3rd NMOS tube MN3 and the 4th NMOS tube MN4.

3. the control circuit according to claims 1, it is characterized in that reference voltage compensation module (82), comprising: the second operational amplifier OP2, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 5th NMOS tube MN5, the 3rd PMOS MP3, the 4th PMOS MP4 and buffer (821);

The current signal I4 that the in-phase input end of described second operational amplifier OP2 and one end of the 4th resistance R4 all input with Voltage to current transducer module (81) is connected, the inverting input of the second operational amplifier OP2 is connected with the source electrode of the 5th NMOS tube MN5 with one end of the 5th resistance R5 respectively, and the output of the second operational amplifier OP2 is connected with the grid of the 5th NMOS tube MN5;

The grid of described 4th PMOS MP4 is connected with the drain electrode of the drain electrode of the 3rd PMOS MP3, grid and the 5th NMOS tube MN5 respectively, the drain electrode of the 4th PMOS MP4 is connected with one end of the 6th resistance R6, as the output output reference signal VREF1 of reference voltage compensation module (82), the 3rd PMOS MP3 is all connected with the supply voltage VDD of its place chip with the source electrode of the 4th PMOS MP4;

The input of described buffer (821) is connected with the input voltage VREF of its place chip, and its output is connected to the other end of the 6th resistance R6;

The other end of described 4th resistance R4 and the equal ground connection of the other end of the 5th resistance R5.